hw/mthca/kernel/mthca_cq.c

   1 /*
   2  * Copyright (c) 2004, 2005 Topspin Communications.  All rights reserved.
   3  * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
   4  * Copyright (c) 2005 Cisco Systems, Inc. All rights reserved.
   5  * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
   6  * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
   7  *
   8  * This software is available to you under a choice of one of two
   9  * licenses.  You may choose to be licensed under the terms of the GNU
  10  * General Public License (GPL) Version 2, available from the file
  11  * COPYING in the main directory of this source tree, or the
  12  * OpenIB.org BSD license below:
  13  *
  14  *     Redistribution and use in source and binary forms, with or
  15  *     without modification, are permitted provided that the following
  16  *     conditions are met:
  17  *
  18  *      - Redistributions of source code must retain the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer.
  21  *
  22  *      - Redistributions in binary form must reproduce the above
  23  *        copyright notice, this list of conditions and the following
  24  *        disclaimer in the documentation and/or other materials
  25  *        provided with the distribution.
  26  *
  27  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  28  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  29  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  30  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  31  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  32  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  33  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  34  * SOFTWARE.
  35  *
  36  * $Id$
  37  */
  38
  39 #include <ib_pack.h>
  40
  41 #include "mthca_dev.h"
  42 #if defined(EVENT_TRACING)
  43 #ifdef offsetof
  44 #undef offsetof
  45 #endif
  46 #include "mthca_cq.tmh"
  47 #endif
  48 #include "mthca_cmd.h"
  49 #include "mthca_memfree.h"
  50
  51
  52 #ifdef ALLOC_PRAGMA
  53 #pragma alloc_text (PAGE, mthca_init_cq_table)
  54 #pragma alloc_text (PAGE, mthca_cleanup_cq_table)
  55 #endif
  56
  57 enum {
  58         MTHCA_MAX_DIRECT_CQ_SIZE = 4 * PAGE_SIZE
  59 };
  60
  61 /*
  62  * Must be packed because start is 64 bits but only aligned to 32 bits.
  63  */
  64 #pragma pack(push,1)
  65 struct mthca_cq_context {
  66         __be32 flags;
  67         __be64 start;
  68         __be32 logsize_usrpage;
  69         __be32 error_eqn;       /* Tavor only */
  70         __be32 comp_eqn;
  71         __be32 pd;
  72         __be32 lkey;
  73         __be32 last_notified_index;
  74         __be32 solicit_producer_index;
  75         __be32 consumer_index;
  76         __be32 producer_index;
  77         __be32 cqn;
  78         __be32 ci_db;           /* Arbel only */
  79         __be32 state_db;        /* Arbel only */
  80         u32    reserved;
  81 };
  82 #pragma pack(pop)
  83
  84 #define MTHCA_CQ_STATUS_OK          ( 0 << 28)
  85 #define MTHCA_CQ_STATUS_OVERFLOW    ( 9 << 28)
  86 #define MTHCA_CQ_STATUS_WRITE_FAIL  (10 << 28)
  87 #define MTHCA_CQ_FLAG_TR            ( 1 << 18)
  88 #define MTHCA_CQ_FLAG_OI            ( 1 << 17)
  89 #define MTHCA_CQ_STATE_DISARMED     ( 0 <<  8)
  90 #define MTHCA_CQ_STATE_ARMED        ( 1 <<  8)
  91 #define MTHCA_CQ_STATE_ARMED_SOL    ( 4 <<  8)
  92 #define MTHCA_EQ_STATE_FIRED        (10 <<  8)
  93
  94 enum {
  95         MTHCA_ERROR_CQE_OPCODE_MASK = 0xfe
  96 };
  97
  98 enum {
  99         SYNDROME_LOCAL_LENGTH_ERR        = 0x01,
 100         SYNDROME_LOCAL_QP_OP_ERR         = 0x02,
 101         SYNDROME_LOCAL_EEC_OP_ERR        = 0x03,
 102         SYNDROME_LOCAL_PROT_ERR          = 0x04,
 103         SYNDROME_WR_FLUSH_ERR            = 0x05,
 104         SYNDROME_MW_BIND_ERR             = 0x06,
 105         SYNDROME_BAD_RESP_ERR            = 0x10,
 106         SYNDROME_LOCAL_ACCESS_ERR        = 0x11,
 107         SYNDROME_REMOTE_INVAL_REQ_ERR    = 0x12,
 108         SYNDROME_REMOTE_ACCESS_ERR       = 0x13,
 109         SYNDROME_REMOTE_OP_ERR           = 0x14,
 110         SYNDROME_RETRY_EXC_ERR           = 0x15,
 111         SYNDROME_RNR_RETRY_EXC_ERR       = 0x16,
 112         SYNDROME_LOCAL_RDD_VIOL_ERR      = 0x20,
 113         SYNDROME_REMOTE_INVAL_RD_REQ_ERR = 0x21,
 114         SYNDROME_REMOTE_ABORTED_ERR      = 0x22,
 115         SYNDROME_INVAL_EECN_ERR          = 0x23,
 116         SYNDROME_INVAL_EEC_STATE_ERR     = 0x24
 117 };
 118
 119 struct mthca_cqe {
 120         __be32 my_qpn;
 121         __be32 my_ee;
 122         __be32 rqpn;
 123         __be16 sl_g_mlpath;
 124         __be16 rlid;
 125         __be32 imm_etype_pkey_eec;
 126         __be32 byte_cnt;
 127         __be32 wqe;
 128         u8     opcode;
 129         u8     is_send;
 130         u8     reserved;
 131         u8     owner;
 132 };
 133
 134 struct mthca_err_cqe {
 135         __be32 my_qpn;
 136         u32    reserved1[3];
 137         u8     syndrome;
 138         u8     vendor_err;
 139         __be16 db_cnt;
 140         u32    reserved2;
 141         __be32 wqe;
 142         u8     opcode;
 143         u8     reserved3[2];
 144         u8     owner;
 145 };
 146
 147 #define MTHCA_CQ_ENTRY_OWNER_SW      (0 << 7)
 148 #define MTHCA_CQ_ENTRY_OWNER_HW      (1 << 7)
 149
 150 #define MTHCA_TAVOR_CQ_DB_INC_CI       (1 << 24)
 151 #define MTHCA_TAVOR_CQ_DB_REQ_NOT      (2 << 24)
 152 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL  (3 << 24)
 153 #define MTHCA_TAVOR_CQ_DB_SET_CI       (4 << 24)
 154 #define MTHCA_TAVOR_CQ_DB_REQ_NOT_MULT (5 << 24)
 155
 156 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL  (1 << 24)
 157 #define MTHCA_ARBEL_CQ_DB_REQ_NOT      (2 << 24)
 158 #define MTHCA_ARBEL_CQ_DB_REQ_NOT_MULT (3 << 24)
 159
 160 static inline struct mthca_cqe *get_cqe(struct mthca_cq *cq, int entry)
 161 {
 162         if (cq->is_direct)
 163                 return (struct mthca_cqe *)((u8*)cq->queue.direct.page + (entry * MTHCA_CQ_ENTRY_SIZE));
 164         else
 165                 return (struct mthca_cqe *)((u8*)cq->queue.page_list[entry * MTHCA_CQ_ENTRY_SIZE / PAGE_SIZE].page
 166                         + (entry * MTHCA_CQ_ENTRY_SIZE) % PAGE_SIZE);
 167 }
 168
 169 static inline struct mthca_cqe *cqe_sw(struct mthca_cq *cq, int i)
 170 {
 171         struct mthca_cqe *cqe = get_cqe(cq, i);
 172         return MTHCA_CQ_ENTRY_OWNER_HW & cqe->owner ? NULL : cqe;
 173 }
 174
 175 static inline struct mthca_cqe *next_cqe_sw(struct mthca_cq *cq)
 176 {
 177         return cqe_sw(cq, cq->cons_index & cq->ibcq.cqe);
 178 }
 179
 180 static inline void set_cqe_hw(struct mthca_cqe *cqe)
 181 {
 182         cqe->owner = MTHCA_CQ_ENTRY_OWNER_HW;
 183 }
 184
 185 static void dump_cqe(u32 print_lvl, struct mthca_dev *dev, void *cqe_ptr)
 186 {
 187         __be32 *cqe = cqe_ptr;
 188         UNREFERENCED_PARAMETER(dev);
 189
 190         (void) cqe;     /* avoid warning if mthca_dbg compiled away... */
 191         HCA_PRINT(print_lvl,HCA_DBG_CQ,("CQE contents \n"));
 192         HCA_PRINT(print_lvl,HCA_DBG_CQ,("\t[%2x] %08x %08x %08x %08x\n",0,
 193                 cl_ntoh32(cqe[0]), cl_ntoh32(cqe[1]), cl_ntoh32(cqe[2]), cl_ntoh32(cqe[3])));
 194         HCA_PRINT(print_lvl,HCA_DBG_CQ,("\t[%2x] %08x %08x %08x %08x \n",16,
 195                 cl_ntoh32(cqe[4]), cl_ntoh32(cqe[5]), cl_ntoh32(cqe[6]), cl_ntoh32(cqe[7])));
 196 }
 197
 198 /*
 199  * incr is ignored in native Arbel (mem-free) mode, so cq->cons_index
 200  * should be correct before calling update_cons_index().
 201  */
 202 static inline void update_cons_index(struct mthca_dev *dev, struct mthca_cq *cq,
 203                                      int incr)
 204 {
 205         __be32 doorbell[2];
 206
 207         if (mthca_is_memfree(dev)) {
 208                 *cq->set_ci_db = cl_hton32(cq->cons_index);
 209                 wmb();
 210         } else {
 211                 doorbell[0] = cl_hton32(MTHCA_TAVOR_CQ_DB_INC_CI | cq->cqn);
 212                 doorbell[1] = cl_hton32(incr - 1);
 213
 214                 mthca_write64(doorbell,
 215                               dev->kar + MTHCA_CQ_DOORBELL,
 216                               MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
 217         }
 218 }
 219
 220 void mthca_cq_completion(struct mthca_dev *dev, u32 cqn)
 221 {
 222         struct mthca_cq *cq;
 223
 224         cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
 225
 226         if (!cq) {
 227                 HCA_PRINT(TRACE_LEVEL_WARNING  ,HCA_DBG_LOW  ,("Completion event for bogus CQ %08x\n", cqn));
 228                 return;
 229         }
 230
 231         if (mthca_is_memfree(dev)) {
 232                 if (cq->ibcq.ucontext)
 233                         ++*cq->p_u_arm_sn;
 234                 else
 235                         ++cq->arm_sn;
 236         }
 237
 238         cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
 239 }
 240
 241 void mthca_cq_event(struct mthca_dev *dev, u32 cqn,
 242                     enum ib_event_type event_type)
 243 {
 244         struct mthca_cq *cq;
 245         struct ib_event event;
 246         SPIN_LOCK_PREP(lh);
 247
 248         spin_lock(&dev->cq_table.lock, &lh);
 249
 250         cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
 251
 252         if (cq)
 253                 atomic_inc(&cq->refcount);
 254         spin_unlock(&lh);
 255
 256         if (!cq) {
 257                 HCA_PRINT(TRACE_LEVEL_WARNING  ,HCA_DBG_LOW  ,("Async event for bogus CQ %08x\n", cqn));
 258                 return;
 259         }
 260
 261         event.device      = &dev->ib_dev;
 262         event.event       = event_type;
 263         event.element.cq  = &cq->ibcq;
 264         if (cq->ibcq.event_handler)
 265                 cq->ibcq.event_handler(&event, cq->ibcq.cq_context);
 266
 267         if (atomic_dec_and_test(&cq->refcount))
 268                 wake_up(&cq->wait);
 269 }
 270
 271 void mthca_cq_clean(struct mthca_dev *dev, u32 cqn, u32 qpn,
 272                     struct mthca_srq *srq)
 273 {
 274         struct mthca_cq *cq;
 275         struct mthca_cqe *cqe;
 276         u32 prod_index;
 277         int nfreed = 0;
 278         SPIN_LOCK_PREP(lht);
 279         SPIN_LOCK_PREP(lh);
 280
 281         spin_lock_irq(&dev->cq_table.lock, &lht);
 282         cq = mthca_array_get(&dev->cq_table.cq, cqn & (dev->limits.num_cqs - 1));
 283         if (cq)
 284                 atomic_inc(&cq->refcount);
 285         spin_unlock_irq(&lht);
 286
 287         if (!cq)
 288                 return;
 289
 290         spin_lock_irq(&cq->lock, &lh);
 291
 292         /*
 293          * First we need to find the current producer index, so we
 294          * know where to start cleaning from.  It doesn't matter if HW
 295          * adds new entries after this loop -- the QP we're worried
 296          * about is already in RESET, so the new entries won't come
 297          * from our QP and therefore don't need to be checked.
 298          */
 299         for (prod_index = cq->cons_index;
 300              cqe_sw(cq, prod_index & cq->ibcq.cqe);
 301              ++prod_index) {
 302                 if (prod_index == cq->cons_index + cq->ibcq.cqe)
 303                         break;
 304         }
 305
 306         HCA_PRINT(TRACE_LEVEL_VERBOSE,HCA_DBG_LOW,("Cleaning QPN %06x from CQN %06x; ci %d, pi %d\n",
 307                   qpn, cqn, cq->cons_index, prod_index));
 308
 309         /*
 310          * Now sweep backwards through the CQ, removing CQ entries
 311          * that match our QP by copying older entries on top of them.
 312          */
 313         while ((int) --prod_index - (int) cq->cons_index >= 0) {
 314                 cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
 315                 if (cqe->my_qpn == cl_hton32(qpn)) {
 316                         if (srq)
 317                                 mthca_free_srq_wqe(srq, cl_ntoh32(cqe->wqe));
 318                         ++nfreed;
 319                 }
 320                 else
 321                 if (nfreed) {
 322                         memcpy(get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe),
 323                                 cqe, MTHCA_CQ_ENTRY_SIZE);
 324                 }
 325         }
 326
 327         if (nfreed) {
 328                 wmb();
 329                 cq->cons_index += nfreed;
 330                 update_cons_index(dev, cq, nfreed);
 331         }
 332
 333         spin_unlock_irq(&lh);
 334         if (atomic_dec_and_test(&cq->refcount))
 335                 wake_up(&cq->wait);
 336 }
 337
 338 static void handle_error_cqe(struct mthca_dev *dev, struct mthca_cq *cq,
 339                             struct mthca_qp *qp, int wqe_index, int is_send,
 340                             struct mthca_err_cqe *cqe,
 341                             struct _ib_wc *entry, int *free_cqe)
 342 {
 343         int dbd;
 344         __be32 new_wqe;
 345
 346         UNREFERENCED_PARAMETER(cq);
 347
 348         if (cqe->syndrome != SYNDROME_WR_FLUSH_ERR) {
 349                 HCA_PRINT(TRACE_LEVEL_INFORMATION ,HCA_DBG_CQ ,("Completion with errro "
 350                           "(QPN %06x, WQE @ %08x, CQN %06x, index %d)\n",
 351                           cl_ntoh32(cqe->my_qpn), cl_ntoh32(cqe->wqe),
 352                           cq->cqn, cq->cons_index));
 353                 dump_cqe(TRACE_LEVEL_INFORMATION, dev, cqe);
 354         }
 355
 356
 357         /*
 358          * For completions in error, only work request ID, status, vendor error
 359          * (and freed resource count for RD) have to be set.
 360          */
 361         switch (cqe->syndrome) {
 362         case SYNDROME_LOCAL_LENGTH_ERR:
 363                 entry->status = IB_WCS_LOCAL_LEN_ERR;
 364                 break;
 365         case SYNDROME_LOCAL_QP_OP_ERR:
 366                 entry->status = IB_WCS_LOCAL_OP_ERR;
 367                 break;
 368         case SYNDROME_LOCAL_PROT_ERR:
 369                 entry->status = IB_WCS_LOCAL_PROTECTION_ERR;
 370                 break;
 371         case SYNDROME_WR_FLUSH_ERR:
 372                 entry->status = IB_WCS_WR_FLUSHED_ERR;
 373                 break;
 374         case SYNDROME_MW_BIND_ERR:
 375                 entry->status = IB_WCS_MEM_WINDOW_BIND_ERR;
 376                 break;
 377         case SYNDROME_BAD_RESP_ERR:
 378                 entry->status = IB_WCS_BAD_RESP_ERR;
 379                 break;
 380         case SYNDROME_LOCAL_ACCESS_ERR:
 381                 entry->status = IB_WCS_LOCAL_ACCESS_ERR;
 382                 break;
 383         case SYNDROME_REMOTE_INVAL_REQ_ERR:
 384                 entry->status = IB_WCS_REM_INVALID_REQ_ERR;
 385                 break;
 386         case SYNDROME_REMOTE_ACCESS_ERR:
 387                 entry->status = IB_WCS_REM_ACCESS_ERR;
 388                 break;
 389         case SYNDROME_REMOTE_OP_ERR:
 390                 entry->status = IB_WCS_REM_OP_ERR;
 391                 break;
 392         case SYNDROME_RETRY_EXC_ERR:
 393                 entry->status = IB_WCS_TIMEOUT_RETRY_ERR;
 394                 break;
 395         case SYNDROME_RNR_RETRY_EXC_ERR:
 396                 entry->status = IB_WCS_RNR_RETRY_ERR;
 397                 break;
 398         case SYNDROME_REMOTE_INVAL_RD_REQ_ERR:
 399                 entry->status = IB_WCS_REM_INVALID_REQ_ERR;
 400                 break;
 401         case SYNDROME_REMOTE_ABORTED_ERR:
 402         case SYNDROME_LOCAL_EEC_OP_ERR:
 403         case SYNDROME_LOCAL_RDD_VIOL_ERR:
 404         case SYNDROME_INVAL_EECN_ERR:
 405         case SYNDROME_INVAL_EEC_STATE_ERR:
 406         default:
 407                 entry->status = IB_WCS_GENERAL_ERR;
 408                 break;
 409         }
 410
 411         entry->vendor_specific = cqe->vendor_err;
 412
 413         /*
 414          * Mem-free HCAs always generate one CQE per WQE, even in the
 415          * error case, so we don't have to check the doorbell count, etc.
 416          */
 417         if (mthca_is_memfree(dev))
 418                 return;
 419
 420         mthca_free_err_wqe(dev, qp, is_send, wqe_index, &dbd, &new_wqe);
 421
 422         /*
 423          * If we're at the end of the WQE chain, or we've used up our
 424          * doorbell count, free the CQE.  Otherwise just update it for
 425          * the next poll operation.
 426          */
 427         if (!(new_wqe & cl_hton32(0x3f)) || (!cqe->db_cnt && dbd))
 428                 return;
 429
 430         cqe->db_cnt   = cl_hton16(cl_ntoh16(cqe->db_cnt) - (u16)dbd);
 431         cqe->wqe      = new_wqe;
 432         cqe->syndrome = SYNDROME_WR_FLUSH_ERR;
 433
 434         *free_cqe = 0;
 435 }
 436
 437 static inline int mthca_poll_one(struct mthca_dev *dev,
 438                                  struct mthca_cq *cq,
 439                                  struct mthca_qp **cur_qp,
 440                                  int *freed,
 441                                  struct _ib_wc *entry)
 442 {
 443         struct mthca_wq *wq;
 444         struct mthca_cqe *cqe;
 445         unsigned  wqe_index;
 446         int is_error;
 447         int is_send;
 448         int free_cqe = 1;
 449         int err = 0;
 450
 451         HCA_ENTER(HCA_DBG_CQ);
 452         cqe = next_cqe_sw(cq);
 453         if (!cqe)
 454                 return -EAGAIN;
 455
 456         /*
 457          * Make sure we read CQ entry contents after we've checked the
 458          * ownership bit.
 459          */
 460         rmb();
 461
 462         { // debug print
 463                 HCA_PRINT(TRACE_LEVEL_VERBOSE,HCA_DBG_CQ,("CQ: 0x%06x/%d: CQE -> QPN 0x%06x, WQE @ 0x%08x\n",
 464                           cq->cqn, cq->cons_index, cl_ntoh32(cqe->my_qpn),
 465                           cl_ntoh32(cqe->wqe)));
 466                 dump_cqe(TRACE_LEVEL_VERBOSE, dev, cqe);
 467         }
 468
 469         is_error = (cqe->opcode & MTHCA_ERROR_CQE_OPCODE_MASK) ==
 470                 MTHCA_ERROR_CQE_OPCODE_MASK;
 471         is_send  = is_error ? cqe->opcode & 0x01 : cqe->is_send & 0x80;
 472
 473         if (!*cur_qp || cl_ntoh32(cqe->my_qpn) != (*cur_qp)->qpn) {
 474                 /*
 475                  * We do not have to take the QP table lock here,
 476                  * because CQs will be locked while QPs are removed
 477                  * from the table.
 478                  */
 479                 *cur_qp = mthca_array_get(&dev->qp_table.qp,
 480                                           cl_ntoh32(cqe->my_qpn) &
 481                                           (dev->limits.num_qps - 1));
 482                 if (!*cur_qp) {
 483                         HCA_PRINT(TRACE_LEVEL_WARNING,HCA_DBG_CQ, ("CQ entry for unknown QP %06x\n",
 484                                    cl_ntoh32(cqe->my_qpn) & 0xffffff));
 485                         err = -EINVAL;
 486                         goto out;
 487                 }
 488         }
 489
 490         if (is_send) {
 491                 wq = &(*cur_qp)->sq;
 492                 wqe_index = ((cl_ntoh32(cqe->wqe) - (*cur_qp)->send_wqe_offset)
 493                              >> wq->wqe_shift);
 494                 entry->wr_id = (*cur_qp)->wrid[wqe_index +
 495                                                (*cur_qp)->rq.max];
 496         } else if ((*cur_qp)->ibqp.srq) {
 497                 struct mthca_srq *srq = to_msrq((*cur_qp)->ibqp.srq);
 498                 u32 wqe = cl_ntoh32(cqe->wqe);
 499                 wq = NULL;
 500                 wqe_index = wqe >> srq->wqe_shift;
 501                 entry->wr_id = srq->wrid[wqe_index];
 502                 mthca_free_srq_wqe(srq, wqe);
 503         } else {
 504                 wq = &(*cur_qp)->rq;
 505                 wqe_index = cl_ntoh32(cqe->wqe) >> wq->wqe_shift;
 506                 entry->wr_id = (*cur_qp)->wrid[wqe_index];
 507         }
 508
 509         if (wq) {
 510                 if (wq->last_comp < wqe_index)
 511                         wq->tail += wqe_index - wq->last_comp;
 512                 else
 513                         wq->tail += wqe_index + wq->max - wq->last_comp;
 514
 515                 wq->last_comp = wqe_index;
 516         }
 517
 518         if (is_send) {
 519                 entry->recv.ud.recv_opt = 0;
 520                 switch (cqe->opcode) {
 521                 case MTHCA_OPCODE_RDMA_WRITE:
 522                         entry->wc_type    = IB_WC_RDMA_WRITE;
 523                         break;
 524                 case MTHCA_OPCODE_RDMA_WRITE_IMM:
 525                         entry->wc_type    = IB_WC_RDMA_WRITE;
 526                         entry->recv.ud.recv_opt |= IB_RECV_OPT_IMMEDIATE;
 527                         break;
 528                 case MTHCA_OPCODE_SEND:
 529                         entry->wc_type    = IB_WC_SEND;
 530                         break;
 531                 case MTHCA_OPCODE_SEND_IMM:
 532                         entry->wc_type    = IB_WC_SEND;
 533                         entry->recv.ud.recv_opt |= IB_RECV_OPT_IMMEDIATE;
 534                         break;
 535                 case MTHCA_OPCODE_RDMA_READ:
 536                         entry->wc_type    = IB_WC_RDMA_READ;
 537                         entry->length  = cl_ntoh32(cqe->byte_cnt);
 538                         break;
 539                 case MTHCA_OPCODE_ATOMIC_CS:
 540                         entry->wc_type    = IB_WC_COMPARE_SWAP;
 541                         entry->length  = cl_ntoh32(cqe->byte_cnt);
 542                         break;
 543                 case MTHCA_OPCODE_ATOMIC_FA:
 544                         entry->wc_type    = IB_WC_FETCH_ADD;
 545                         entry->length  = cl_ntoh32(cqe->byte_cnt);
 546                         break;
 547                 case MTHCA_OPCODE_BIND_MW:
 548                         entry->wc_type    = IB_WC_MW_BIND;
 549                         break;
 550                 default:
 551                         entry->wc_type    = IB_WC_SEND;
 552                         break;
 553                 }
 554         } else {
 555                 entry->length = cl_ntoh32(cqe->byte_cnt);
 556                 switch (cqe->opcode & 0x1f) {
 557                 case IB_OPCODE_SEND_LAST_WITH_IMMEDIATE:
 558                 case IB_OPCODE_SEND_ONLY_WITH_IMMEDIATE:
 559                         entry->recv.ud.recv_opt = IB_RECV_OPT_IMMEDIATE;
 560                         entry->recv.ud.immediate_data = cqe->imm_etype_pkey_eec;
 561                         entry->wc_type = IB_WC_RECV;
 562                         break;
 563                 case IB_OPCODE_RDMA_WRITE_LAST_WITH_IMMEDIATE:
 564                 case IB_OPCODE_RDMA_WRITE_ONLY_WITH_IMMEDIATE:
 565                         entry->recv.ud.recv_opt = IB_RECV_OPT_IMMEDIATE;
 566                         entry->recv.ud.immediate_data = cqe->imm_etype_pkey_eec;
 567                         entry->wc_type = IB_WC_RECV_RDMA_WRITE;
 568                         break;
 569                 default:
 570                         entry->recv.ud.recv_opt = 0;
 571                         entry->wc_type = IB_WC_RECV;
 572                         break;
 573                 }
 574                 entry->recv.ud.remote_lid          = cqe->rlid;
 575                 entry->recv.ud.remote_qp           = cqe->rqpn & 0xffffff00;
 576                 entry->recv.ud.pkey_index  = (u16)(cl_ntoh32(cqe->imm_etype_pkey_eec) >> 16);
 577                 entry->recv.ud.remote_sl           = (uint8_t)(cl_ntoh16(cqe->sl_g_mlpath) >> 12);
 578                 entry->recv.ud.path_bits = (uint8_t)(cl_ntoh16(cqe->sl_g_mlpath) & 0x7f);
 579                 entry->recv.ud.recv_opt   |= cl_ntoh16(cqe->sl_g_mlpath) & 0x80 ?
 580                                         IB_RECV_OPT_GRH_VALID : 0;
 581         }
 582         if (!is_send && cqe->rlid == 0){
 583                 HCA_PRINT(TRACE_LEVEL_INFORMATION,HCA_DBG_CQ,("found rlid == 0 \n "));
 584                 entry->recv.ud.recv_opt   |= IB_RECV_OPT_FORWARD;
 585
 586         }
 587         if (is_error) {
 588                 handle_error_cqe(dev, cq, *cur_qp, wqe_index, is_send,
 589                         (struct mthca_err_cqe *) cqe, entry, &free_cqe);
 590         }
 591         else
 592                 entry->status = IB_WCS_SUCCESS;
 593
 594  out:
 595         if (likely(free_cqe)) {
 596                 set_cqe_hw(cqe);
 597                 ++(*freed);
 598                 ++cq->cons_index;
 599         }
 600         HCA_EXIT(HCA_DBG_CQ);
 601         return err;
 602 }
 603
 604 int mthca_poll_cq(struct ib_cq *ibcq, int num_entries,
 605                   struct _ib_wc *entry)
 606 {
 607         struct mthca_dev *dev = to_mdev(ibcq->device);
 608         struct mthca_cq *cq = to_mcq(ibcq);
 609         struct mthca_qp *qp = NULL;
 610         int err = 0;
 611         int freed = 0;
 612         int npolled;
 613         SPIN_LOCK_PREP(lh);
 614
 615         spin_lock_irqsave(&cq->lock, &lh);
 616
 617         for (npolled = 0; npolled < num_entries; ++npolled) {
 618                 err = mthca_poll_one(dev, cq, &qp,
 619                                      &freed, entry + npolled);
 620                 if (err)
 621                         break;
 622         }
 623
 624         if (freed) {
 625                 wmb();
 626                 update_cons_index(dev, cq, freed);
 627         }
 628
 629         spin_unlock_irqrestore(&lh);
 630
 631         return (err == 0 || err == -EAGAIN) ? npolled : err;
 632 }
 633
 634 int mthca_poll_cq_list(
 635         IN              struct ib_cq *ibcq,
 636         IN      OUT                     ib_wc_t** const                         pp_free_wclist,
 637                 OUT                     ib_wc_t** const                         pp_done_wclist )
 638 {
 639         struct mthca_dev *dev = to_mdev(ibcq->device);
 640         struct mthca_cq *cq = to_mcq(ibcq);
 641         struct mthca_qp *qp = NULL;
 642         int err = 0;
 643         int freed = 0;
 644         ib_wc_t         *wc_p, **next_pp;
 645         SPIN_LOCK_PREP(lh);
 646
 647         HCA_ENTER(HCA_DBG_CQ);
 648
 649         spin_lock_irqsave(&cq->lock, &lh);
 650
 651         // loop through CQ
 652         next_pp = pp_done_wclist;
 653         wc_p = *pp_free_wclist;
 654         while( wc_p ) {
 655                 // poll one CQE
 656                 err = mthca_poll_one(dev, cq, &qp, &freed, wc_p);
 657                 if (err)
 658                         break;
 659
 660                 // prepare for the next loop
 661                 *next_pp = wc_p;
 662                 next_pp = &wc_p->p_next;
 663                 wc_p = wc_p->p_next;
 664         }
 665
 666         // prepare the results
 667         *pp_free_wclist = wc_p;         /* Set the head of the free list. */
 668         *next_pp = NULL;                                                /* Clear the tail of the done list. */
 669
 670         // update consumer index
 671         if (freed) {
 672                 wmb();
 673                 update_cons_index(dev, cq, freed);
 674         }
 675
 676         spin_unlock_irqrestore(&lh);
 677         HCA_EXIT(HCA_DBG_CQ);
 678         return (err == 0 || err == -EAGAIN)? 0 : err;
 679 }
 680
 681
 682 int mthca_tavor_arm_cq(struct ib_cq *cq, enum ib_cq_notify notify)
 683 {
 684         __be32 doorbell[2];
 685
 686         doorbell[0] = cl_hton32((notify == IB_CQ_SOLICITED ?
 687                                    MTHCA_TAVOR_CQ_DB_REQ_NOT_SOL :
 688                                    MTHCA_TAVOR_CQ_DB_REQ_NOT)      |
 689                                   to_mcq(cq)->cqn);
 690         doorbell[1] = (__be32) 0xffffffff;
 691
 692         mthca_write64(doorbell,
 693                       to_mdev(cq->device)->kar + MTHCA_CQ_DOORBELL,
 694                       MTHCA_GET_DOORBELL_LOCK(&to_mdev(cq->device)->doorbell_lock));
 695
 696         return 0;
 697 }
 698
 699 int mthca_arbel_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify notify)
 700 {
 701         struct mthca_cq *cq = to_mcq(ibcq);
 702         __be32 doorbell[2];
 703         u32 sn;
 704         __be32 ci;
 705
 706         sn = cq->arm_sn & 3;
 707         ci = cl_hton32(cq->cons_index);
 708
 709         doorbell[0] = ci;
 710         doorbell[1] = cl_hton32((cq->cqn << 8) | (2 << 5) | (sn << 3) |
 711                                   (notify == IB_CQ_SOLICITED ? 1 : 2));
 712
 713         mthca_write_db_rec(doorbell, cq->arm_db);
 714
 715         /*
 716          * Make sure that the doorbell record in host memory is
 717          * written before ringing the doorbell via PCI MMIO.
 718          */
 719         wmb();
 720
 721         doorbell[0] = cl_hton32((sn << 28)                       |
 722                                   (notify == IB_CQ_SOLICITED ?
 723                                    MTHCA_ARBEL_CQ_DB_REQ_NOT_SOL :
 724                                    MTHCA_ARBEL_CQ_DB_REQ_NOT)      |
 725                                   cq->cqn);
 726         doorbell[1] = ci;
 727
 728         mthca_write64(doorbell,
 729                       to_mdev(ibcq->device)->kar + MTHCA_CQ_DOORBELL,
 730                       MTHCA_GET_DOORBELL_LOCK(&to_mdev(ibcq->device)->doorbell_lock));
 731
 732         return 0;
 733 }
 734
 735 static void mthca_free_cq_buf(struct mthca_dev *dev, struct mthca_cq *cq)
 736 {
 737         mthca_buf_free(dev, (cq->ibcq.cqe + 1) * MTHCA_CQ_ENTRY_SIZE,
 738                        &cq->queue, cq->is_direct, &cq->mr);
 739 }
 740
 741 int mthca_init_cq(struct mthca_dev *dev, int nent,
 742                   struct mthca_ucontext *ctx, u32 pdn,
 743                   struct mthca_cq *cq)
 744 {
 745         int size = NEXT_PAGE_ALIGN(nent * MTHCA_CQ_ENTRY_SIZE );
 746         struct mthca_mailbox *mailbox;
 747         struct mthca_cq_context *cq_context;
 748         int err = -ENOMEM;
 749         u8 status;
 750         int i;
 751         SPIN_LOCK_PREP(lh);
 752
 753         cq->ibcq.cqe  = nent - 1;
 754         cq->is_kernel = !ctx;
 755
 756         cq->cqn = mthca_alloc(&dev->cq_table.alloc);
 757         if (cq->cqn == -1)
 758                 return -ENOMEM;
 759
 760         if (mthca_is_memfree(dev)) {
 761                 err = mthca_table_get(dev, dev->cq_table.table, cq->cqn);
 762                 if (err)
 763                         goto err_out;
 764
 765                 if (cq->is_kernel) {
 766                         cq->arm_sn = 1;
 767
 768                         err = -ENOMEM;
 769
 770                         cq->set_ci_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_SET_CI,
 771                                                              cq->cqn, &cq->set_ci_db);
 772                         if (cq->set_ci_db_index < 0)
 773                                 goto err_out_icm;
 774
 775                         cq->arm_db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_CQ_ARM,
 776                                                           cq->cqn, &cq->arm_db);
 777                         if (cq->arm_db_index < 0)
 778                                 goto err_out_ci;
 779                 }
 780         }
 781
 782         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 783         if (IS_ERR(mailbox))
 784                 goto err_out_arm;
 785
 786         cq_context = mailbox->buf;
 787
 788         if (cq->is_kernel) {
 789                 err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_CQ_SIZE,
 790                                       &cq->queue, &cq->is_direct,
 791                                       &dev->driver_pd, 1, &cq->mr);
 792                 if (err)
 793                         goto err_out_mailbox;
 794
 795                 for (i = 0; i < nent; ++i)
 796                         set_cqe_hw(get_cqe(cq, i));
 797         }
 798
 799         spin_lock_init(&cq->lock);
 800         atomic_set(&cq->refcount, 1);
 801         init_waitqueue_head(&cq->wait);
 802         KeInitializeMutex(&cq->mutex, 0);
 803
 804         RtlZeroMemory(cq_context, sizeof *cq_context);
 805         cq_context->flags           = cl_hton32(MTHCA_CQ_STATUS_OK      |
 806                                                   MTHCA_CQ_STATE_DISARMED |
 807                                                   MTHCA_CQ_FLAG_TR);
 808         cq_context->logsize_usrpage = cl_hton32((ffs(nent) - 1) << 24);
 809         if (ctx)
 810                 cq_context->logsize_usrpage |= cl_hton32(ctx->uar.index);
 811         else
 812                 cq_context->logsize_usrpage |= cl_hton32(dev->driver_uar.index);
 813         cq_context->error_eqn       = cl_hton32(dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn);
 814         cq_context->comp_eqn        = cl_hton32(dev->eq_table.eq[MTHCA_EQ_COMP].eqn);
 815         cq_context->pd              = cl_hton32(pdn);
 816         cq_context->lkey            = cl_hton32(cq->mr.ibmr.lkey);
 817         cq_context->cqn             = cl_hton32(cq->cqn);
 818
 819         if (mthca_is_memfree(dev)) {
 820                 cq_context->ci_db    = cl_hton32(cq->set_ci_db_index);
 821                 cq_context->state_db = cl_hton32(cq->arm_db_index);
 822         }
 823
 824         err = mthca_SW2HW_CQ(dev, mailbox, cq->cqn, &status);
 825         if (err) {
 826                 HCA_PRINT(TRACE_LEVEL_WARNING  ,HCA_DBG_LOW  ,("SW2HW_CQ failed (%d)\n", err));
 827                 goto err_out_free_mr;
 828         }
 829
 830         if (status) {
 831                 HCA_PRINT(TRACE_LEVEL_WARNING,HCA_DBG_LOW,("SW2HW_CQ returned status 0x%02x\n",
 832                            status));
 833                 err = -EINVAL;
 834                 goto err_out_free_mr;
 835         }
 836
 837         spin_lock_irq(&dev->cq_table.lock, &lh);
 838         if (mthca_array_set(&dev->cq_table.cq,
 839                             cq->cqn & (dev->limits.num_cqs - 1),
 840                             cq)) {
 841                 spin_unlock_irq(&lh);
 842                 goto err_out_free_mr;
 843         }
 844         spin_unlock_irq(&lh);
 845
 846         cq->cons_index = 0;
 847
 848         mthca_free_mailbox(dev, mailbox);
 849
 850         return 0;
 851
 852 err_out_free_mr:
 853         if (cq->is_kernel)
 854                 mthca_free_cq_buf(dev, cq);
 855
 856 err_out_mailbox:
 857         mthca_free_mailbox(dev, mailbox);
 858
 859 err_out_arm:
 860         if (cq->is_kernel && mthca_is_memfree(dev))
 861                 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM, cq->arm_db_index);
 862
 863 err_out_ci:
 864         if (cq->is_kernel && mthca_is_memfree(dev))
 865                 mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
 866
 867 err_out_icm:
 868         mthca_table_put(dev, dev->cq_table.table, cq->cqn);
 869
 870 err_out:
 871         mthca_free(&dev->cq_table.alloc, cq->cqn);
 872
 873         return err;
 874 }
 875
 876 void mthca_free_cq(struct mthca_dev *dev,
 877                    struct mthca_cq *cq)
 878 {
 879         struct mthca_mailbox *mailbox;
 880         int err;
 881         u8 status;
 882         SPIN_LOCK_PREP(lh);
 883
 884         mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
 885         if (IS_ERR(mailbox)) {
 886                 HCA_PRINT(TRACE_LEVEL_WARNING  ,HCA_DBG_LOW  ,("No memory for mailbox to free CQ.\n"));
 887                 return;
 888         }
 889
 890         err = mthca_HW2SW_CQ(dev, mailbox, cq->cqn, &status);
 891         if (err){
 892                 HCA_PRINT(TRACE_LEVEL_WARNING  ,HCA_DBG_LOW  ,("HW2SW_CQ failed (%d)\n", err));
 893         }
 894         else if (status){
 895                 HCA_PRINT(TRACE_LEVEL_WARNING  ,HCA_DBG_LOW  ,("HW2SW_CQ returned status 0x%02x\n", status));
 896         }
 897
 898         { // debug print
 899                 __be32 *ctx = mailbox->buf;
 900                 int j;
 901
 902                 HCA_PRINT(TRACE_LEVEL_VERBOSE ,HCA_DBG_LOW ,("context for CQN %x (cons index %x, next sw %d)\n",
 903                        cq->cqn, cq->cons_index,
 904                        cq->is_kernel ? !!next_cqe_sw(cq) : 0));
 905                 for (j = 0; j < 16; ++j)
 906                         HCA_PRINT(TRACE_LEVEL_VERBOSE   ,HCA_DBG_LOW   ,("[%2x] %08x\n", j * 4, cl_ntoh32(ctx[j])));
 907         }
 908
 909         spin_lock_irq(&dev->cq_table.lock, &lh);
 910         mthca_array_clear(&dev->cq_table.cq,
 911                           cq->cqn & (dev->limits.num_cqs - 1));
 912         spin_unlock_irq(&lh);
 913
 914         /* wait for all RUNNING DPCs on that EQ to complete */
 915         {
 916                 ASSERT(KeGetCurrentIrql() <= DISPATCH_LEVEL);
 917                 // wait for DPCs, using this EQ, to complete
 918                 spin_lock_sync( &dev->eq_table.eq[MTHCA_EQ_COMP].lock);
 919                 //TODO: do we need that ?
 920                 spin_lock_sync( &dev->eq_table.eq[MTHCA_EQ_ASYNC].lock );
 921         }
 922
 923         atomic_dec(&cq->refcount);
 924         wait_event(&cq->wait, !atomic_read(&cq->refcount));
 925
 926         if (cq->is_kernel) {
 927                 mthca_free_cq_buf(dev, cq);
 928                 if (mthca_is_memfree(dev)) {
 929                         mthca_free_db(dev, MTHCA_DB_TYPE_CQ_ARM,    cq->arm_db_index);
 930                         mthca_free_db(dev, MTHCA_DB_TYPE_CQ_SET_CI, cq->set_ci_db_index);
 931                 }
 932         }
 933
 934         mthca_table_put(dev, dev->cq_table.table, cq->cqn);
 935         mthca_free(&dev->cq_table.alloc, cq->cqn);
 936         mthca_free_mailbox(dev, mailbox);
 937 }
 938
 939 int mthca_init_cq_table(struct mthca_dev *dev)
 940 {
 941         int err;
 942
 943         spin_lock_init(&dev->cq_table.lock);
 944
 945         err = mthca_alloc_init(&dev->cq_table.alloc,
 946                                dev->limits.num_cqs,
 947                                (1 << 24) - 1,
 948                                dev->limits.reserved_cqs);
 949         if (err)
 950                 return err;
 951
 952         err = mthca_array_init(&dev->cq_table.cq,
 953                                dev->limits.num_cqs);
 954         if (err)
 955                 mthca_alloc_cleanup(&dev->cq_table.alloc);
 956
 957         return err;
 958 }
 959
 960 void mthca_cleanup_cq_table(struct mthca_dev *dev)
 961 {
 962         mthca_array_cleanup(&dev->cq_table.cq, dev->limits.num_cqs);
 963         mthca_alloc_cleanup(&dev->cq_table.alloc);
 964 }
 965
 966