hw/mt23108/kernel/hca_data.h

   1 /*\r
   2  * Copyright (c) 2005 SilverStorm Technologies.  All rights reserved.\r
   3  * Copyright (c) 2004-2005 Mellanox Technologies, Inc. All rights reserved. \r
   4  *\r
   5  * This software is available to you under the OpenIB.org BSD license\r
   6  * below:\r
   7  *\r
   8  *     Redistribution and use in source and binary forms, with or\r
   9  *     without modification, are permitted provided that the following\r
  10  *     conditions are met:\r
  11  *\r
  12  *      - Redistributions of source code must retain the above\r
  13  *        copyright notice, this list of conditions and the following\r
  14  *        disclaimer.\r
  15  *\r
  16  *      - Redistributions in binary form must reproduce the above\r
  17  *        copyright notice, this list of conditions and the following\r
  18  *        disclaimer in the documentation and/or other materials\r
  19  *        provided with the distribution.\r
  20  *\r
  21  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,\r
  22  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF\r
  23  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND\r
  24  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS\r
  25  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN\r
  26  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN\r
  27  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE\r
  28  * SOFTWARE.\r
  29  *\r
  30  * $Id$\r
  31  */\r
  32 \r
  33 #ifndef __HCA_DATA_H__\r
  34 #define __HCA_DATA_H__\r
  35 \r
  36 \r
  37 #include <iba/ib_ci.h>\r
  38 #include <complib/comp_lib.h>\r
  39 \r
  40 #include <vapi.h>\r
  41 #include <evapi.h>\r
  42 #include <hh.h>\r
  43 #include <thh.h>\r
  44 #include <thh_hob.h>\r
  45 #include <tavor_dev_defs.h>\r
  46 #include <thh_init.h>\r
  47 #include <hhul.h>\r
  48 #include <thhul_hob.h>\r
  49 #include <thhul_pdm.h>\r
  50 #include <thhul_cqm.h>\r
  51 #include <thhul_qpm.h>\r
  52 \r
  53 extern u_int32_t                g_mlnx_dbg_lvl;\r
  54 extern uint32_t                 g_sqp_max_avs;\r
  55 extern char                             mlnx_uvp_lib_name[];\r
  56 \r
  57 #define MLNX_DBG_INFO    (1<<1)\r
  58 #define MLNX_DBG_TRACE   (1<<2)\r
  59 #define MLNX_DBG_VERBOSE (1<<3)\r
  60 // for data path debugging\r
  61 #define MLNX_DBG_DIRECT  (1<<4)\r
  62 #define MLNX_DBG_QPN     (1<<5)\r
  63 #define MLNX_DBG_MEM     (1<<6)\r
  64 \r
  65 #define MLNX_MAX_HCA   4\r
  66 #define MLNX_NUM_HOBKL MLNX_MAX_HCA\r
  67 #define MLNX_NUM_HOBUL MLNX_MAX_HCA\r
  68 #define MLNX_NUM_CB_THR     1\r
  69 #define MLNX_SIZE_CB_POOL 256\r
  70 #define MLNX_UAL_ALLOC_HCA_UL_RES 1\r
  71 #define MLNX_UAL_FREE_HCA_UL_RES 2\r
  72 \r
  73 \r
  74 // Defines for QP ops\r
  75 #define MLNX_MAX_NUM_SGE 8\r
  76 #define MLNX_MAX_WRS_PER_CHAIN 4\r
  77 \r
  78 #define MLNX_NUM_RESERVED_QPS 16\r
  79 \r
  80 /*\r
  81  * Completion model.\r
  82  *      0: No DPC processor assignment\r
  83  *      1: DPCs per-CQ, processor affinity set at CQ initialization time.\r
  84  *      2: DPCs per-CQ, processor affinity set at runtime.\r
  85  *      3: DPCs per-CQ, no processor affinity set.\r
  86  */\r
  87 #define MLNX_COMP_MODEL         3\r
  88 \r
  89 #define PD_HCA_FROM_HNDL(hndl) (((pd_info_t *)hndl)->hca_idx)\r
  90 #define PD_NUM_FROM_HNDL(hndl) (((pd_info_t *)hndl)->pd_num)\r
  91 #define CQ_HCA_FROM_HNDL(hndl) (((cq_info_t *)hndl)->hca_idx)\r
  92 #define CQ_NUM_FROM_HNDL(hndl) (((cq_info_t *)hndl)->cq_num)\r
  93 #define QP_HCA_FROM_HNDL(hndl) (((qp_info_t *)hndl)->hca_idx)\r
  94 #define QP_NUM_FROM_HNDL(hndl) (((qp_info_t *)hndl)->qp_num)\r
  95 \r
  96 #define PD_HNDL_FROM_PD(pd_num) (&hobul_p->pd_info_tbl[pd_num])\r
  97 #define CQ_HNDL_FROM_CQ(cq_num) (&hobul_p->cq_info_tbl[cq_num])\r
  98 #define QP_HNDL_FROM_QP(qp_num) (&hobul_p->qp_info_tbl[qp_num])\r
  99 \r
 100 #ifdef _DEBUG_\r
 101 #define VALIDATE_INDEX(index, limit, error, label) \\r
 102         {                  \\r
 103                 if (index >= limit) \\r
 104                 {                   \\r
 105                         status = error;   \\r
 106                         CL_TRACE(CL_DBG_ERROR, g_mlnx_dbg_lvl, ("file %s line %d\n", __FILE__, __LINE__)); \\r
 107                         goto label;       \\r
 108                 }                   \\r
 109         }\r
 110 #else\r
 111 #define VALIDATE_INDEX(index, limit, error, label)\r
 112 #endif\r
 113 \r
 114 \r
 115 \r
 116 // Typedefs\r
 117 \r
 118 typedef enum {\r
 119         E_EV_CA=1,\r
 120         E_EV_QP,\r
 121         E_EV_CQ,\r
 122         E_EV_LAST\r
 123 } ENUM_EVENT_CLASS;\r
 124 \r
 125 typedef enum {\r
 126         E_MARK_CA=1, // Channel Adaptor\r
 127         E_MARK_PD, // Protection Domain\r
 128         E_MARK_CQ, // Completion Queue\r
 129         E_MARK_QP, // Queue Pair\r
 130         E_MARK_AV, // Address Vector (UD)\r
 131         E_MARK_MG, // Multicast Group\r
 132         E_MARK_MR, // Memory Region\r
 133         E_MARK_MW, // Memory Windows\r
 134         E_MARK_INVALID,\r
 135 } ENUM_MARK;\r
 136 \r
 137 typedef enum {\r
 138         E_MR_PHYS=1,\r
 139         E_MR_SHARED,\r
 140         E_MR_ANY,\r
 141         E_MR_INVALID\r
 142 } ENUM_MR_TYPE;\r
 143 \r
 144 /*\r
 145  * Attribute cache for port info saved to expedite local MAD processing.\r
 146  * Note that the cache accounts for the worst case GID and PKEY table size\r
 147  * but is allocated from paged pool, so it's nothing to worry about.\r
 148  */\r
 149 \r
 150 typedef struct _guid_block\r
 151 {\r
 152         boolean_t                               valid;\r
 153         ib_guid_info_t                  tbl;\r
 154 \r
 155 }       mlnx_guid_block_t;\r
 156 \r
 157 typedef struct _port_info_cache\r
 158 {\r
 159         boolean_t                               valid;\r
 160         ib_port_info_t                  info;\r
 161 \r
 162 }       mlnx_port_info_cache_t;\r
 163 \r
 164 typedef struct _pkey_block\r
 165 {\r
 166         boolean_t                               valid;\r
 167         ib_pkey_table_info_t    tbl;\r
 168 \r
 169 }       mlnx_pkey_block_t;\r
 170 \r
 171 typedef struct _sl_vl_cache\r
 172 {\r
 173         boolean_t                               valid;\r
 174         ib_slvl_table_t                 tbl;\r
 175 \r
 176 }       mlnx_sl_vl_cache_t;\r
 177 \r
 178 typedef struct _vl_arb_block\r
 179 {\r
 180         boolean_t                               valid;\r
 181         ib_vl_arb_table_t               tbl;\r
 182 \r
 183 }       mlnx_vl_arb_block_t;\r
 184 \r
 185 typedef struct _attr_cache\r
 186 {\r
 187         mlnx_guid_block_t               guid_block[32];\r
 188         mlnx_port_info_cache_t  port_info;\r
 189         mlnx_pkey_block_t               pkey_tbl[2048];\r
 190         mlnx_sl_vl_cache_t              sl_vl;\r
 191         mlnx_vl_arb_block_t             vl_arb[4];\r
 192 \r
 193 }       mlnx_cache_t;\r
 194 \r
 195 typedef struct _ib_ca {\r
 196         ENUM_MARK           mark;\r
 197         HH_hca_hndl_t       hh_hndl;\r
 198         ci_completion_cb_t  comp_cb_p;\r
 199         ci_async_event_cb_t async_cb_p;\r
 200         const void          *ca_context;\r
 201         void                *cl_device_h;\r
 202         u_int32_t           index;\r
 203         cl_async_proc_t     *async_proc_mgr_p;\r
 204         mlnx_cache_t            *cache; // Cached port attributes.\r
 205         const void * __ptr64    p_dev_obj; // store underlying device object\r
 206 } mlnx_hob_t;\r
 207 \r
 208 typedef struct _ib_um_ca\r
 209 {\r
 210         MDL                                     *p_mdl;\r
 211         void                            *p_mapped_addr;\r
 212         HH_hca_hndl_t           hh_hndl;\r
 213         mlnx_hob_t                      *hob_p;\r
 214         /* The next two fields must be grouped together as the are mapped to UM. */\r
 215         HH_hca_dev_t            dev_info;\r
 216         uint8_t                         ul_hca_res[1];  // Beginning of UL resource buffer.\r
 217 }       mlnx_um_ca_t;\r
 218 \r
 219 typedef struct {\r
 220         cl_async_proc_item_t async_item;\r
 221         HH_hca_hndl_t        hh_hndl;\r
 222         HH_cq_hndl_t         hh_cq; // for completion\r
 223         HH_event_record_t    hh_er; // for async events\r
 224         void                 *private_data;\r
 225 } mlnx_cb_data_t;\r
 226 \r
 227 typedef struct {\r
 228         cl_list_item_t  list_item;\r
 229         HH_hca_hndl_t hh_hndl;\r
 230         struct _hca_if {\r
 231                 HH_hca_hndl_t hh_hndl;\r
 232                 void *          kernel_crspace_addr;\r
 233                 ULONG           kernel_crspace_size;\r
 234         } s;\r
 235 //      char                    *hca_name_p;\r
 236         net64_t                 guid;\r
 237         const void* __ptr64     p_dev_obj;              // hca device object\r
 238 //      ci_interface_t ifx;\r
 239 } mlnx_hca_t;\r
 240 \r
 241 typedef struct _ib_pd {        /* struct of PD related resources */\r
 242         ENUM_MARK         mark;\r
 243         cl_mutex_t        mutex;\r
 244         u_int32_t         kernel_mode;\r
 245         atomic32_t        count;\r
 246         u_int32_t         hca_idx;\r
 247         // mlnx_hob_t        *hob_p;\r
 248         HH_hca_hndl_t     hh_hndl;        /* For HH direct access */\r
 249         HH_pd_hndl_t      pd_num;         /* For HH-UL direct access */\r
 250         HHUL_pd_hndl_t    hhul_pd_hndl;\r
 251         void              *pd_ul_resources_p;\r
 252 } pd_info_t;\r
 253 \r
 254 typedef struct _ib_cq {        /* struct of CQ related resources */\r
 255         ENUM_MARK         mark;\r
 256         cl_mutex_t        mutex;\r
 257         u_int32_t         hca_idx;\r
 258         u_int32_t         kernel_mode;\r
 259         // mlnx_hob_t        *hob_p;\r
 260         HH_hca_hndl_t     hh_hndl;        /* For HH direct access */\r
 261         HH_cq_hndl_t      cq_num;         /* For HH-UL direct access */\r
 262 //      HH_pd_hndl_t      pd_num;         /* For HH-UL direct access */\r
 263         HHUL_cq_hndl_t    hhul_cq_hndl;\r
 264         void              *cq_ul_resources_p;\r
 265         const void        *cq_context;\r
 266         KDPC                            dpc;\r
 267         atomic32_t                      spl_qp_cnt;\r
 268 \r
 269 } cq_info_t;\r
 270 \r
 271 typedef struct _ib_qp {\r
 272         ENUM_MARK         mark;\r
 273         cl_mutex_t        mutex;\r
 274         u_int32_t         hca_idx;\r
 275         u_int32_t         kernel_mode;\r
 276         // mlnx_hob_t        *hob_p;\r
 277         HH_hca_hndl_t     hh_hndl;      // For HH direct access */\r
 278         HHUL_qp_hndl_t    hhul_qp_hndl;\r
 279         IB_wqpn_t         qp_num;       // For direct HH-UL access */\r
 280         HH_pd_hndl_t      pd_num;       // For HH-UL direct access */\r
 281         IB_port_t         port;         // Valid for special QPs only */\r
 282         ib_qp_type_t      qp_type;      // Required for qp_query\r
 283         u_int32_t         sq_signaled;  // Required for qp_query\r
 284         ib_cq_handle_t          h_sq_cq;\r
 285         ib_cq_handle_t          h_rq_cq;\r
 286         u_int32_t         sq_size;\r
 287         u_int32_t         rq_size;\r
 288         VAPI_sr_desc_t    *send_desc_p;\r
 289         VAPI_rr_desc_t    *recv_desc_p;\r
 290         VAPI_sg_lst_entry_t *send_sge_p;\r
 291         VAPI_sg_lst_entry_t *recv_sge_p;\r
 292         void              *qp_ul_resources_p;\r
 293         const void        *qp_context;\r
 294 } qp_info_t;\r
 295 \r
 296 typedef struct HOBUL_t {\r
 297         HH_hca_hndl_t     hh_hndl;                /* For HH direct access */\r
 298         HHUL_hca_hndl_t   hhul_hndl;              /* user level HCA resources handle for HH */\r
 299         u_int32_t         cq_idx_mask;            /*                                                */\r
 300         u_int32_t         qp_idx_mask;            /*                                                */\r
 301         u_int32_t         vendor_id;              /* \                                              */\r
 302         u_int32_t         device_id;              /*  >  3 items needed for initializing user level */\r
 303         void              *hca_ul_resources_p;    /* /                                              */\r
 304         MT_size_t         cq_ul_resources_sz;     /* Needed for allocating user resources for CQs  */\r
 305         MT_size_t         qp_ul_resources_sz;     /* Needed for allocating user resources for QPs  */\r
 306         MT_size_t         pd_ul_resources_sz;     /* Needed for allocating user resources for PDs  */\r
 307         u_int32_t         max_cq;                 /* Max num. of CQs - size of following table */\r
 308         cq_info_t         *cq_info_tbl;\r
 309         u_int32_t         max_qp;                 /* Max num. of QPs - size of following table */\r
 310         qp_info_t         *qp_info_tbl;\r
 311         u_int32_t         max_pd;                 /* Max num. of PDs - size of following table */\r
 312         pd_info_t         *pd_info_tbl;\r
 313         u_int32_t         log2_mpt_size;\r
 314         atomic32_t        count;\r
 315 } mlnx_hobul_t, *mlnx_hobul_hndl_t;\r
 316 \r
 317 typedef struct _ib_mr {\r
 318         ENUM_MARK                               mark;\r
 319         ENUM_MR_TYPE                    mr_type;\r
 320         u_int64_t                               mr_start;       // TBD: IA64\r
 321         u_int64_t                               mr_size;                // TBD: IA64\r
 322 //      u_int64_t                               mr_first_page_addr; // TBD : IA64\r
 323 //      u_int32_t                               mr_num_pages;\r
 324         ib_pd_handle_t                  mr_pd_handle;\r
 325         MOSAL_iobuf_t                   mr_iobuf;\r
 326         VAPI_mrw_acl_t                  mr_acl;\r
 327         VAPI_lkey_t                             mr_lkey;\r
 328         MOSAL_protection_ctx_t  mr_prot_ctx;\r
 329         MOSAL_mem_perm_t                mr_mosal_perm;\r
 330 } mlnx_mro_t;\r
 331 \r
 332 typedef struct _ib_mw {\r
 333         ENUM_MARK         mark;\r
 334         u_int32_t         hca_idx;\r
 335         u_int32_t         pd_idx;\r
 336         u_int32_t         mw_rkey;\r
 337 } mlnx_mwo_t;\r
 338 \r
 339 typedef struct _ib_mcast {\r
 340         ENUM_MARK         mark;\r
 341         IB_gid_t          mcast_gid;\r
 342         u_int32_t         hca_idx;\r
 343         u_int32_t         qp_num;\r
 344         u_int32_t         kernel_mode;\r
 345 } mlnx_mcast_t;\r
 346 \r
 347 typedef struct _ib_av {\r
 348         ENUM_MARK         mark;\r
 349         u_int32_t         hca_idx;\r
 350         u_int32_t         pd_idx;\r
 351         u_int32_t         user_mode;\r
 352         HHUL_ud_av_hndl_t h_av;\r
 353 } mlnx_avo_t;\r
 354 \r
 355 typedef mlnx_hob_t *mlnx_hca_h;\r
 356 \r
 357 // Global Variables\r
 358 //extern mlnx_hca_t       mlnx_hca_array[];\r
 359 //extern uint32_t         mlnx_num_hca;\r
 360 \r
 361 extern mlnx_hob_t   mlnx_hob_array[];\r
 362 extern mlnx_hobul_t *mlnx_hobul_array[];\r
 363 \r
 364 // Functions\r
 365 void\r
 366 setup_ci_interface(\r
 367         IN              const   ib_net64_t                                      ca_guid,\r
 368                 OUT                     ci_interface_t                          *p_interface );\r
 369 \r
 370 void\r
 371 mlnx_hca_insert(\r
 372         IN                              mlnx_hca_t                                      *p_hca );\r
 373 \r
 374 void\r
 375 mlnx_hca_remove(\r
 376         IN                              mlnx_hca_t                                      *p_hca );\r
 377 \r
 378 mlnx_hca_t*\r
 379 mlnx_hca_from_guid(\r
 380         IN                              ib_net64_t                                      guid );\r
 381 \r
 382 mlnx_hca_t*\r
 383 mlnx_hca_from_hh_hndl(\r
 384         IN                              HH_hca_hndl_t                   hh_hndl );\r
 385 \r
 386 /*\r
 387 void\r
 388 mlnx_names_from_guid(\r
 389         IN                              ib_net64_t                                      guid,\r
 390                 OUT                     char                                            **hca_name_p,\r
 391                 OUT                     char                                            **dev_name_p);\r
 392 */\r
 393 \r
 394 cl_status_t\r
 395 mlnx_hobs_init( void );\r
 396 \r
 397 ib_api_status_t\r
 398 mlnx_hobs_insert(\r
 399         IN                              mlnx_hca_t                                      *p_hca,\r
 400                 OUT                     mlnx_hob_t                                      **hob_p);\r
 401 \r
 402 void\r
 403 mlnx_hobs_get_handle(\r
 404         IN                              mlnx_hob_t                                      *hob_p,\r
 405                 OUT                     HH_hca_hndl_t                           *hndl_p);\r
 406 \r
 407 ib_api_status_t\r
 408 mlnx_hobs_set_cb(\r
 409         IN                              mlnx_hob_t                                      *hob_p, \r
 410         IN                              ci_completion_cb_t                      comp_cb_p,\r
 411         IN                              ci_async_event_cb_t                     async_cb_p,\r
 412         IN              const   void* const                                     ib_context);\r
 413 \r
 414 ib_api_status_t\r
 415 mlnx_hobs_get_context(\r
 416         IN                              mlnx_hob_t                                      *hob_p,\r
 417                 OUT                     void                                            **context_p);\r
 418 \r
 419 ib_api_status_t\r
 420 mlnx_hobs_create_device(\r
 421         IN                              mlnx_hob_t                                      *hob_p,\r
 422                 OUT                     char*                                           dev_name);\r
 423 \r
 424 void\r
 425 mlnx_hobs_remove(\r
 426         IN                              mlnx_hob_t                                      *hob_p);\r
 427 \r
 428 ib_api_status_t\r
 429 mlnx_hobs_lookup(\r
 430         IN                              HH_hca_hndl_t                           hndl,\r
 431                 OUT                     mlnx_hob_t                                      **hca_p);\r
 432 \r
 433 mlnx_hobul_t *\r
 434 mlnx_hobs_get_hobul(\r
 435         IN                              mlnx_hob_t                                      *hob_p);\r
 436 \r
 437 ib_api_status_t\r
 438 mlnx_hobul_new(\r
 439         IN                              mlnx_hob_t                                      *hob_p,\r
 440         IN                              HH_hca_hndl_t                           hh_hndl,\r
 441         IN                              void                                            *resources_p);\r
 442 \r
 443 void\r
 444 mlnx_hobul_get(\r
 445         IN                              mlnx_hob_t                                      *hob_p,\r
 446                 OUT                     void                                            **resources_p );\r
 447 \r
 448 void\r
 449 mlnx_hobul_delete(\r
 450         IN                              mlnx_hob_t                                      *hob_p);\r
 451 \r
 452 // Conversion Functions\r
 453 \r
 454 VAPI_mrw_acl_t\r
 455 map_ibal_acl(\r
 456         IN                              ib_access_t                                     ibal_acl);\r
 457 \r
 458 ib_access_t\r
 459 map_vapi_acl(\r
 460         IN                              VAPI_mrw_acl_t                          vapi_acl);\r
 461 \r
 462 ib_api_status_t\r
 463 mlnx_lock_region(\r
 464         IN                              mlnx_mro_t                                      *mro_p,\r
 465         IN                              boolean_t                                       um_call );\r
 466 \r
 467 ib_api_status_t\r
 468 mlnx_conv_ibal_mr_create(\r
 469         IN                              u_int32_t                                       pd_idx,\r
 470         IN      OUT                     mlnx_mro_t                                      *mro_p,\r
 471         IN                              VAPI_mr_change_t                        change_flags,\r
 472         IN                              ib_mr_create_t const            *p_mr_create,\r
 473         IN                              boolean_t                                       um_call,\r
 474                 OUT                     HH_mr_t                                         *mr_props_p );\r
 475 \r
 476 ib_api_status_t\r
 477 mlnx_conv_ibal_pmr_create(\r
 478         IN                              u_int32_t                                       pd_idx,\r
 479         IN                              mlnx_mro_t                                      *mro_p,\r
 480         IN                              ib_phys_create_t const          *p_pmr_create,\r
 481                 OUT                     HH_mr_t                                         *mr_props_p );\r
 482 \r
 483 void\r
 484 mlnx_conv_ibal_av(\r
 485         IN                              HH_hca_hndl_t                           hh_hndl,\r
 486         IN              const   ib_av_attr_t                            *ibal_av_p,\r
 487                 OUT                     VAPI_ud_av_t                            *vapi_av_p);\r
 488 \r
 489 void\r
 490 mlnx_conv_vapi_av(\r
 491         IN                              HH_hca_hndl_t                           hh_hndl,\r
 492         IN              const   VAPI_ud_av_t                            *vapi_av_p,\r
 493                 OUT                     ib_av_attr_t                            *ibal_av_p);\r
 494 \r
 495 int\r
 496 mlnx_map_vapi_cqe_status(\r
 497         IN                              VAPI_wc_status_t                        vapi_status);\r
 498 \r
 499 int\r
 500 mlnx_map_vapi_cqe_type(\r
 501         IN                              VAPI_cqe_opcode_t                       opcode);\r
 502 \r
 503 int\r
 504 mlnx_map_vapi_rna_type(\r
 505         IN                              VAPI_remote_node_addr_type_t    rna);\r
 506 \r
 507 void\r
 508 mlnx_conv_vapi_mr_attr(\r
 509         IN                              ib_pd_handle_t                          pd_h,\r
 510         IN                              HH_mr_info_t                            *mr_info_p,\r
 511                 OUT                     ib_mr_attr_t                            *mr_query_p);\r
 512 \r
 513 void\r
 514 mlnx_conv_bind_req(\r
 515         IN                              HHUL_qp_hndl_t                          hhul_qp_hndl,\r
 516         IN                              ib_bind_wr_t* const                     p_mw_bind,\r
 517                 OUT                     HHUL_mw_bind_t                          *bind_prop_p);\r
 518 \r
 519 int\r
 520 mlnx_map_ibal_qp_type(\r
 521         IN                              ib_qp_type_t                            ibal_qpt,\r
 522                 OUT                     VAPI_special_qp_t                       *vapi_qp_type_p);\r
 523 \r
 524 void\r
 525 mlnx_conv_qp_create_attr(\r
 526         IN              const   ib_qp_create_t                          *create_attr_p,\r
 527         IN                              HHUL_qp_init_attr_t                     *init_attr_p,\r
 528                 OUT                     VAPI_special_qp_t                       *vapi_qp_type_p);\r
 529 \r
 530 void\r
 531 mlnx_conv_vapi_qp_attr(\r
 532         IN                              HH_hca_hndl_t                           hh_hndl,\r
 533         IN                              VAPI_qp_attr_t                          *hh_qp_attr_p,\r
 534                 OUT                     ib_qp_attr_t                            *qp_attr_p);\r
 535 \r
 536 ib_api_status_t\r
 537 mlnx_conv_qp_modify_attr(\r
 538         IN                              HH_hca_hndl_t                           hh_hndl,\r
 539         IN                              ib_qp_type_t                            qp_type,\r
 540         IN              const   ib_qp_mod_t                                     *modify_attr_p,\r
 541                 OUT                     VAPI_qp_attr_t                          *qp_attr_p, \r
 542                 OUT                     VAPI_qp_attr_mask_t                     *attr_mask_p);\r
 543 \r
 544 ib_api_status_t\r
 545 mlnx_conv_send_desc(\r
 546         IN                              IB_ts_t                                         transport,\r
 547         IN              const   ib_send_wr_t                            *ibal_send_wqe_p,\r
 548                 OUT                     VAPI_sr_desc_t                          *vapi_send_desc_p);\r
 549 \r
 550 ib_api_status_t\r
 551 mlnx_conv_recv_desc(\r
 552         IN              const   ib_recv_wr_t                            *ibal_recv_wqe_p,\r
 553                 OUT                     VAPI_rr_desc_t                          *vapi_recv_desc_p);\r
 554 \r
 555 void\r
 556 mlnx_conv_vapi_hca_cap(\r
 557         IN                              HH_hca_dev_t                            *hca_info_p,\r
 558         IN                              VAPI_hca_cap_t                          *vapi_hca_cap_p,\r
 559         IN                              VAPI_hca_port_t                         *vapi_hca_ports,\r
 560                 OUT                     ib_ca_attr_t                            *ca_attr_p);\r
 561 \r
 562 ib_api_status_t\r
 563 mlnx_get_hca_pkey_tbl(\r
 564         IN                              HH_hca_hndl_t                           hh_hndl,\r
 565         IN                              u_int8_t                                        port_num,\r
 566         IN                              u_int16_t                                       num_entries,\r
 567                 OUT                     void*                                           table);\r
 568 \r
 569 ib_api_status_t\r
 570 mlnx_get_hca_gid_tbl(\r
 571         IN                              HH_hca_hndl_t                           hh_hndl,\r
 572         IN                              u_int8_t                                        port_num,\r
 573         IN                              u_int16_t                                       num_entries,\r
 574                 OUT                     void*                                           table);\r
 575 \r
 576 ib_api_status_t\r
 577 mlnx_local_mad (\r
 578         IN              const   ib_ca_handle_t                          h_ca,\r
 579         IN              const   uint8_t                                         port_num,\r
 580         IN              const   ib_av_attr_t                                    *p_av_src_attr, \r
 581         IN              const   ib_mad_t                                        *p_mad_in,\r
 582                 OUT                     ib_mad_t                                        *p_mad_out );\r
 583 \r
 584 void\r
 585 mlnx_memory_if(\r
 586         IN      OUT                     ci_interface_t                          *p_interface );\r
 587 \r
 588 void\r
 589 mlnx_ecc_if(\r
 590         IN      OUT                     ci_interface_t                          *p_interface );\r
 591 \r
 592 void\r
 593 mlnx_direct_if(\r
 594         IN      OUT                     ci_interface_t                          *p_interface );\r
 595 \r
 596 void\r
 597 mlnx_mcast_if(\r
 598         IN      OUT                     ci_interface_t                          *p_interface );\r
 599 \r
 600 ib_api_status_t\r
 601 fw_access_ctrl(\r
 602         IN              const   void* __ptr64                           context,\r
 603         IN              const   void* __ptr64* const            handle_array    OPTIONAL,\r
 604         IN                              uint32_t                                        num_handles,\r
 605         IN                              ib_ci_op_t* const                       p_ci_op,\r
 606         IN      OUT                     ci_umv_buf_t                            *p_umv_buf              OPTIONAL);\r
 607 \r
 608 #endif\r