0a42ee5570b08bd85abd37d2acd5a51604f758a9
[mirror/winof/.git] / hw / mlx4 / kernel / inc / l2w_pci.h
1 #pragma once
2
3 // ===========================================
4 // LITERALS
5 // ===========================================
6
7 #define DEVID_HERMON_SDR                0x6340  /* 25408 */
8 #define DEVID_HERMON_DDR                0x634a  /* 25418 */
9 #define DEVID_HERMON_ETH                0x6368  /* 25448 */
10 #define DEVID_HERMON_ETH_YATIR          0x6372  /* 25458 */
11 #define DEVID_HERMON_DDR_G2             0x6732  /* 26418 */
12 #define DEVID_HERMON_QDR_G2             0x673c  /* 26428 */
13 #define DEVID_HERMON_ETH_G2             0x6750  /* 26448 */
14 #define DEVID_HERMON_ETH_YATIR_G2               0x675A  /* 26458 */
15 /* livefish */
16 #define DEVID_HERMON_BD         0x0191  /* 401 */
17
18 /* Types of supported HCA */
19 typedef enum __hca_type {
20         HERMON,                 /* fully functional HCA */
21         LIVEFISH                /* a burning device */
22 } hca_type_t;
23
24 /* vendors */
25 #define PCI_VENDOR_ID_MELLANOX                          0x15b3
26 #define PCI_VENDOR_ID_TOPSPIN                           0x1867
27
28 #define HCA(v, d, t) \
29         { PCI_VENDOR_ID_##v,    DEVID_HERMON_##d, t }
30
31 struct pci_device_id {
32         USHORT          vendor;
33         USHORT          device;
34         hca_type_t      driver_data;
35 };
36
37
38 // ===========================================
39 // TYPES
40 // ===========================================
41
42
43 // ===========================================
44 // MACROS/FUNCTIONS
45 // ===========================================
46
47 NTSTATUS pci_hca_reset( struct pci_dev *pdev);
48
49 /* use shim to implement that */
50 #define mlx4_reset(dev)         pci_hca_reset(dev->pdev)
51
52 // get bar boundaries
53 #define pci_resource_start(dev,bar_num) ((dev)->bar[bar_num >> 1].phys)
54 #define pci_resource_len(dev,bar_num)   ((dev)->bar[bar_num >> 1].size)
55
56 // i/o to registers
57
58 static inline u64 readq(const volatile void __iomem *addr)
59 {
60         //TODO: write atomic implementation of _IO_READ_QWORD and change mthca_doorbell.h
61         u64 val;
62         READ_REGISTER_BUFFER_ULONG((PULONG)(addr), (PULONG)&val, 2 );
63         return val;
64 }
65
66 static inline u32 readl(const volatile void __iomem *addr)
67 {
68         return READ_REGISTER_ULONG((PULONG)(addr));
69 }
70
71 static inline u16 reads(const volatile void __iomem *addr)
72 {
73         return READ_REGISTER_USHORT((PUSHORT)(addr));
74 }
75
76 static inline u8 readb(const volatile void __iomem *addr)
77 {
78         return READ_REGISTER_UCHAR((PUCHAR)(addr));
79 }
80
81 #define __raw_readq             readq
82 #define __raw_readl             readl
83 #define __raw_reads             reads
84 #define __raw_readb             readb
85
86 static inline void writeq(unsigned __int64 val, volatile void __iomem *addr)
87 {
88         //TODO: write atomic implementation of _IO_WRITE_QWORD and change mthca_doorbell.h
89         WRITE_REGISTER_BUFFER_ULONG( (PULONG)(addr), (PULONG)&val, 2 );
90 }
91
92 static inline void writel(unsigned int val, volatile void __iomem *addr)
93 {
94         WRITE_REGISTER_ULONG((PULONG)(addr),val);
95 }
96
97 static inline void writes(unsigned short val, volatile void __iomem *addr)
98 {
99         WRITE_REGISTER_USHORT((PUSHORT)(addr),val);
100 }
101
102 static inline void writeb(unsigned char val, volatile void __iomem *addr)
103 {
104         WRITE_REGISTER_UCHAR((PUCHAR)(addr),val);
105 }
106
107 #define __raw_writeq            writeq
108 #define __raw_writel            writel
109 #define __raw_writes            writes
110 #define __raw_writeb            writeb
111
112