Add the 82576 to the e1000 driver.
- Examining the Linux 2.6.30-rc4 igb driver, which supports this card and;
- Information available in the Intel® 82576 Gigabit Ethernet
Controller Datasheet v2.1, which is available from Intel's web site.
I only have a dual-ported card with Copper PHY, so any code paths relating
to Fibre haven't been tested. Also, I have only tested using auto-negotiation
of speed and duplex, and no flow control. Other code paths relating to
those settings also have not been exercised.
Signed-off-by: Simon Horman <horms@verge.net.au>
Sponsored-by: Thomas Miletich <thomas.miletich@gmail.com>
Modified-by: Thomas Miletich <thomas.miletich@gmail.com>
Modified-by: Marty Connor <mdc@etherboot.org>
Signed-off-by: Marty Connor <mdc@etherboot.org>
break;
case e1000_82571:
case e1000_82572:
+ case e1000_82576:
case e1000_80003es2lan:
case e1000_ich8lan:
ctrl_ext = E1000_READ_REG(&adapter->hw, CTRL_EXT);
{
struct e1000_hw *hw = &adapter->hw;
uint32_t tctl;
+ uint32_t txdctl;
DBG ( "e1000_configure_tx\n" );
adapter->tx_tail = 0;
adapter->tx_fill_ctr = 0;
+ if (hw->mac_type == e1000_82576) {
+ txdctl = E1000_READ_REG ( hw, TXDCTL );
+ txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
+ E1000_WRITE_REG ( hw, TXDCTL, txdctl );
+ }
+
/* Setup Transmit Descriptor Settings for eop descriptor */
tctl = E1000_TCTL_PSP | E1000_TCTL_EN |
(E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) |
e1000_configure_rx ( struct e1000_adapter *adapter )
{
struct e1000_hw *hw = &adapter->hw;
- uint32_t rctl;
+ uint32_t rctl, rxdctl, mrqc, rxcsum;
DBG ( "e1000_configure_rx\n" );
/* disable receives while setting up the descriptors */
rctl = E1000_READ_REG ( hw, RCTL );
E1000_WRITE_REG ( hw, RCTL, rctl & ~E1000_RCTL_EN );
+ E1000_WRITE_FLUSH ( hw );
+ mdelay(10);
adapter->rx_curr = 0;
E1000_WRITE_REG ( hw, RDLEN, adapter->rx_ring_size );
E1000_WRITE_REG ( hw, RDH, 0 );
- E1000_WRITE_REG ( hw, RDT, NUM_RX_DESC - 1 );
-
- /* Enable Receives */
- rctl = ( E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
- E1000_RCTL_MPE
- );
+ if (hw->mac_type == e1000_82576)
+ E1000_WRITE_REG ( hw, RDT, 0 );
+ else
+ E1000_WRITE_REG ( hw, RDT, NUM_RX_DESC - 1 );
+
+ /* This doesn't seem to be necessary for correct operation,
+ * but it seems as well to be implicit
+ */
+ if (hw->mac_type == e1000_82576) {
+ rxdctl = E1000_READ_REG ( hw, RXDCTL );
+ rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
+ rxdctl &= 0xFFF00000;
+ rxdctl |= IGB_RX_PTHRESH;
+ rxdctl |= IGB_RX_HTHRESH << 8;
+ rxdctl |= IGB_RX_WTHRESH << 16;
+ E1000_WRITE_REG ( hw, RXDCTL, rxdctl );
+ E1000_WRITE_FLUSH ( hw );
+
+ rxcsum = E1000_READ_REG(hw, RXCSUM);
+ rxcsum &= ~( E1000_RXCSUM_TUOFL | E1000_RXCSUM_IPPCSE );
+ E1000_WRITE_REG ( hw, RXCSUM, 0 );
+
+ /* The initial value for MRQC disables multiple receive
+ * queues, however this setting is not recommended.
+ * - Intel® 82576 Gigabit Ethernet Controller Datasheet r2.41
+ * Section 8.10.9 Multiple Queues Command Register - MRQC
+ */
+ mrqc = E1000_MRQC_ENABLE_VMDQ;
+ E1000_WRITE_REG ( hw, MRQC, mrqc );
+ }
+ /* Enable Receives */
+ rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_SZ_2048 |
+ E1000_RCTL_MPE;
E1000_WRITE_REG ( hw, RCTL, rctl );
E1000_WRITE_FLUSH ( hw );
+ /* On the 82576, RDT([0]) must not be "bumped" before
+ * the enable bit of RXDCTL([0]) is set.
+ * - Intel® 82576 Gigabit Ethernet Controller Datasheet r2.41
+ * Section 4.5.9 receive Initialization
+ *
+ * By observation I have found to occur when the enable bit of
+ * RCTL is set. The datasheet recommends polling for this bit,
+ * however as I see no evidence of this in the Linux igb driver
+ * I have omitted that step.
+ * - Simon Horman, May 2009
+ */
+ if (hw->mac_type == e1000_82576)
+ E1000_WRITE_REG ( hw, RDT, NUM_RX_DESC - 1 );
+
DBG ( "RDBAL: %#08x\n", E1000_READ_REG ( hw, RDBAL ) );
DBG ( "RDLEN: %d\n", E1000_READ_REG ( hw, RDLEN ) );
DBG ( "RCTL: %#08x\n", E1000_READ_REG ( hw, RCTL ) );
case e1000_82573:
pba = E1000_PBA_20K;
break;
+ case e1000_82576:
+ pba = E1000_PBA_64K;
+ break;
case e1000_ich8lan:
pba = E1000_PBA_8K;
case e1000_undefined:
/* Set the FC high water mark to 90% of the FIFO size.
* Required to clear last 3 LSB */
fc_high_water_mark = ((pba * 9216)/10) & 0xFFF8;
+
/* We can't use 90% on small FIFOs because the remainder
* would be less than 1 full frame. In this case, we size
* it to allow at least a full frame above the high water
if (pba < E1000_PBA_16K)
fc_high_water_mark = (pba * 1024) - 1600;
- adapter->hw.fc_high_water = fc_high_water_mark;
- adapter->hw.fc_low_water = fc_high_water_mark - 8;
- if (adapter->hw.mac_type == e1000_80003es2lan)
+ /* This actually applies to < e1000_82575, one revision less than
+ * e1000_82576, but e1000_82575 isn't currently defined in the code */
+ if (adapter->hw.mac_type < e1000_82576) {
+ /* 8-byte granularity */
+ adapter->hw.fc_high_water = fc_high_water_mark & 0xFFF8;
+ adapter->hw.fc_low_water = adapter->hw.fc_high_water - 8;
+ } else {
+ /* 16-byte granularity */
+ adapter->hw.fc_high_water = fc_high_water_mark & 0xFFF0;
+ adapter->hw.fc_low_water = adapter->hw.fc_high_water - 16;
+ }
+
+ if (adapter->hw.mac_type == e1000_80003es2lan ||
+ adapter->hw.mac_type == e1000_82576)
adapter->hw.fc_pause_time = 0xFFFF;
else
adapter->hw.fc_pause_time = E1000_FC_PAUSE_TIME;
PCI_ROM(0x8086, 0x10bc, "e1000-0x10bc", "e1000-0x10bc", 0),
PCI_ROM(0x8086, 0x10c4, "e1000-0x10c4", "e1000-0x10c4", 0),
PCI_ROM(0x8086, 0x10c5, "e1000-0x10c5", "e1000-0x10c5", 0),
+ PCI_ROM(0x8086, 0x10c9, "e1000-0x10c9", "e1000-0x10c9", 0),
PCI_ROM(0x8086, 0x10d9, "e1000-0x10d9", "e1000-0x10d9", 0),
PCI_ROM(0x8086, 0x10da, "e1000-0x10da", "e1000-0x10da", 0),
};
case E1000_DEV_ID_ICH8_IGP_M:
hw->mac_type = e1000_ich8lan;
break;
+ case E1000_DEV_ID_82576:
+ hw->mac_type = e1000_82576;
+ break;
default:
/* Should never have loaded on this device */
return -E1000_ERR_MAC_TYPE;
switch (hw->mac_type) {
case e1000_ich8lan:
+ case e1000_82576:
hw->swfwhw_semaphore_present = TRUE;
hw->asf_firmware_present = TRUE;
break;
break;
case e1000_ich8lan:
case e1000_82573:
+ case e1000_82576:
/* The STATUS_TBIMODE bit is reserved or reused for the this
* device.
*/
static void
e1000_initialize_hardware_bits(struct e1000_hw *hw)
{
- if ((hw->mac_type >= e1000_82571) && (!hw->initialize_hw_bits_disable)) {
+ if ((hw->mac_type >= e1000_82571 && hw->mac_type < e1000_82576) &&
+ (!hw->initialize_hw_bits_disable)) {
/* Settings common to all PCI-express silicon */
uint32_t reg_ctrl, reg_ctrl_ext;
uint32_t reg_tarc0, reg_tarc1;
/* Disabling VLAN filtering. */
DEBUGOUT("Initializing the IEEE VLAN\n");
- /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
- if (hw->mac_type != e1000_ich8lan) {
+ switch (hw->mac_type) {
+ case e1000_ich8lan:
+ /* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
+ break;
+ case e1000_82576:
+ /* There is no need to clear vfta on 82576 if VLANs are not used.
+ * - Intel® 82576 Gigabit Ethernet Controller Datasheet r2.41
+ * Section 8.10.19 Table Array - VFTA
+ *
+ * Setting VET may also be unnecessary, however the documentation
+ * isn't specific on this point. The value used here is as advised in
+ * - Intel® 82576 Gigabit Ethernet Controller Datasheet r2.41
+ * Section 8.2.7 VLAN Ether Type - VET
+ */
+ E1000_WRITE_REG(hw, VET, ETHERNET_IEEE_VLAN_TYPE);
+ break;
+ default:
if (hw->mac_type < e1000_82545_rev_3)
E1000_WRITE_REG(hw, VET, 0);
e1000_clear_vfta(hw);
+ break;
}
/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
return ret_val;
}
- /* Wait 15ms for MAC to configure PHY from eeprom settings */
- msleep(15);
- if (hw->mac_type != e1000_ich8lan) {
+ /*
+ * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
+ * timeout issues when LFS is enabled.
+ */
+ msleep(100);
+
+ if (hw->mac_type != e1000_ich8lan && hw->mac_type != e1000_82576) {
/* Configure activity LED after PHY reset */
led_ctrl = E1000_READ_REG(hw, LEDCTL);
led_ctrl &= IGP_ACTIVITY_LED_MASK;
DEBUGFUNC("e1000_read_phy_reg");
- if ((hw->mac_type == e1000_80003es2lan) &&
+ if ((hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_82576) &&
(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
swfw = E1000_SWFW_PHY1_SM;
} else {
DEBUGFUNC("e1000_write_phy_reg");
- if ((hw->mac_type == e1000_80003es2lan) &&
+ if ((hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_82576) &&
(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
swfw = E1000_SWFW_PHY1_SM;
} else {
uint16_t swfw;
DEBUGFUNC("e1000_read_kmrn_reg");
- if ((hw->mac_type == e1000_80003es2lan) &&
+ if ((hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_82576) &&
(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
swfw = E1000_SWFW_PHY1_SM;
} else {
uint16_t swfw;
DEBUGFUNC("e1000_write_kmrn_reg");
- if ((hw->mac_type == e1000_80003es2lan) &&
+ if ((hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_82576) &&
(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
swfw = E1000_SWFW_PHY1_SM;
} else {
DEBUGOUT("Resetting Phy...\n");
if (hw->mac_type > e1000_82543) {
- if ((hw->mac_type == e1000_80003es2lan) &&
+ if ((hw->mac_type == e1000_80003es2lan ||
+ hw->mac_type == e1000_82576) &&
(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
swfw = E1000_SWFW_PHY1_SM;
} else {
if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
break;
+ case e1000_82576:
+ match = TRUE;
+ break;
default:
DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
return -E1000_ERR_CONFIG;
hw->flash_bank_size /= 2 * sizeof(uint16_t);
+ break;
+ }
+ case e1000_82576:
+ {
+ uint16_t size;
+
+ eeprom->type = e1000_eeprom_spi;
+ eeprom->opcode_bits = 8;
+ eeprom->delay_usec = 1;
+ if (eecd & E1000_EECD_ADDR_BITS) {
+ eeprom->page_size = 32;
+ eeprom->address_bits = 16;
+ } else {
+ eeprom->page_size = 8;
+ eeprom->address_bits = 8;
+ }
+ eeprom->use_eerd = TRUE;
+ eeprom->use_eewr = FALSE;
+
+ size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
+ E1000_EECD_SIZE_EX_SHIFT);
+ /*
+ * Added to a constant, "size" becomes the left-shift value
+ * for setting word_size.
+ */
+ size += EEPROM_WORD_SIZE_SHIFT;
+
+ /* EEPROM access above 16k is unsupported */
+ if (size > 14)
+ size = 14;
+ eeprom->word_size = 1 << size;
+
break;
}
default:
* directly. In this case, we need to acquire the EEPROM so that
* FW or other port software does not interrupt.
*/
- if (e1000_is_onboard_nvm_eeprom(hw) == TRUE &&
- hw->eeprom.use_eerd == FALSE) {
+ if (hw->eeprom.use_eerd == FALSE && e1000_is_onboard_nvm_eeprom(hw)) {
/* Prepare the EEPROM for bit-bang reading */
if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
return -E1000_ERR_EEPROM;
DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
+ assert(hw->mac_type != e1000_82576);
+
if (hw->mac_type == e1000_ich8lan)
return FALSE;
case e1000_82546:
case e1000_82546_rev_3:
case e1000_82571:
+ case e1000_82576:
case e1000_80003es2lan:
if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
hw->perm_mac_addr[5] ^= 0x01;
case e1000_80003es2lan:
if (hw->leave_av_bit_off == TRUE)
break;
+ case e1000_82576:
+ /* If MAC address zero, no need to set the AV bit */
+ if (rar_low || rar_high)
+ rar_high |= E1000_RAH_AV;
+ // Only neded when Multiple Receive Queues are enabmed in MRQC
+ rar_high |= E1000_RAH_POOL_1;
+ break;
default:
/* Indicate to hardware the Address is Valid. */
rar_high |= E1000_RAH_AV;
case e1000_82572:
case e1000_82573:
case e1000_80003es2lan:
+ case e1000_82576:
hw->bus_type = e1000_bus_type_pci_express;
hw->bus_speed = e1000_bus_speed_2500;
ret_val = e1000_read_pcie_cap_reg(hw,
case e1000_82573:
case e1000_80003es2lan:
case e1000_ich8lan:
+ case e1000_82576:
while (timeout) {
if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
break;
mdelay(10);
break;
case e1000_80003es2lan:
+ case e1000_82576:
/* Separate *_CFG_DONE_* bit for each port */
if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
case e1000_82572:
case e1000_82573:
case e1000_80003es2lan:
+ case e1000_82576:
fwsm = E1000_READ_REG(hw, FWSM);
if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
return TRUE;
e1000_82573,
e1000_80003es2lan,
e1000_ich8lan,
+ e1000_82576,
e1000_num_macs
} e1000_mac_type;
#define E1000_DEV_ID_ICH8_IFE_G 0x10C5
#define E1000_DEV_ID_ICH8_IGP_M 0x104D
+#define E1000_DEV_ID_82576 0x10C9
#define NODE_ADDRESS_SIZE 6
#define ETH_LENGTH_OF_ADDRESS 6
E1000_IMS_TXDW | \
E1000_IMS_RXDMT0 | \
E1000_IMS_RXSEQ | \
- E1000_IMS_LSC)
+ E1000_IMS_LSC | \
+ E1000_IMS_DOUTSYNC)
/* Additional interrupts need to be handled for e1000_ich8lan:
DSW = The FW changed the status of the DISSW bit in FWSM
/* Receive Address */
#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
+#define E1000_RAH_POOL_1 0x00040000
+
/* Interrupt Cause Read */
#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
+/* LAN connected device generates an interrupt */
+#define E1000_ICR_DOUTSYNC 0x10000000 /* NIC DMA out of sync */
#define E1000_ICR_RXO 0x00000040 /* rx overrun */
#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
+#define E1000_IMS_DOUTSYNC E1000_ICR_DOUTSYNC /* NIC DMA out of sync */
#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
+#define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
+#define IGB_RX_PTHRESH 16
+#define IGB_RX_HTHRESH 8
+#define IGB_RX_WTHRESH 1
/* Transmit Descriptor Control */
#define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */
#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
#define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc.
still to be processed. */
+#define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
/* Transmit Configuration Word */
#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
/* Multiple Receive Queue Control */
#define E1000_MRQC_ENABLE_MASK 0x00000003
+#define E1000_MRQC_ENABLE_VMDQ 0x00000003
#define E1000_MRQC_ENABLE_RSS_2Q 0x00000001
#define E1000_MRQC_ENABLE_RSS_INT 0x00000004
#define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000
#define E1000_PBA_38K 0x0026
#define E1000_PBA_40K 0x0028
#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
+#define E1000_PBA_64K 0x0040 /* 64KB */
#define E1000_PBS_16K E1000_PBA_16K
http://git.etherboot.org / gpxe.git / commitdiff