5 #include <gpxe/blockdev.h>
6 #include <gpxe/uaccess.h>
15 * An ATA Logical Block Address
17 * ATA controllers have three byte-wide registers for specifying the
18 * block address: LBA Low, LBA Mid and LBA High. This allows for a
19 * 24-bit address. Some devices support the "48-bit address feature
20 * set" (LBA48), in which case each of these byte-wide registers is
21 * actually a two-entry FIFO, and the "previous" byte pushed into the
22 * FIFO is used as the corresponding high-order byte. So, to set up
23 * the 48-bit address 0x123456abcdef, you would issue
25 * 0x56 -> LBA Low register
26 * 0xef -> LBA Low register
27 * 0x34 -> LBA Mid register
28 * 0xcd -> LBA Mid register
29 * 0x12 -> LBA High register
30 * 0xab -> LBA High register
32 * This structure encapsulates this information by providing a single
33 * 64-bit integer in native byte order, unioned with bytes named so
34 * that the sequence becomes
36 * low_prev -> LBA Low register
37 * low_cur -> LBA Low register
38 * mid_prev -> LBA Mid register
39 * mid_cur -> LBA Mid register
40 * high_prev -> LBA High register
41 * high_cur -> LBA High register
43 * Just to complicate matters further, in non-LBA48 mode it is
44 * possible to have a 28-bit address, in which case bits 27:24 must be
45 * written into the low four bits of the Device register.
48 /** LBA as a 64-bit integer in native-endian order */
52 #if __BYTE_ORDER == __LITTLE_ENDIAN
60 #elif __BYTE_ORDER == __BIG_ENDIAN
69 #error "I need a byte order"
74 /** An ATA 2-byte FIFO register */
76 /** Value in native-endian order */
80 #if __BYTE_ORDER == __LITTLE_ENDIAN
83 #elif __BYTE_ORDER == __BIG_ENDIAN
87 #error "I need a byte order"
92 /** ATA command block */
94 /** Logical block address */
98 /** Error/feature register */
99 union ata_fifo err_feat;
100 /** Device register */
102 /** Command/status register */
104 /** LBA48 addressing flag */
108 /** Obsolete bits in the ATA device register */
109 #define ATA_DEV_OBSOLETE 0xa0
111 /** LBA flag in the ATA device register */
112 #define ATA_DEV_LBA 0x40
114 /** Slave ("device 1") flag in the ATA device register */
115 #define ATA_DEV_SLAVE 0x10
117 /** Master ("device 0") flag in the ATA device register */
118 #define ATA_DEV_MASTER 0x00
120 /** Mask of non-LBA portion of device register */
121 #define ATA_DEV_MASK 0xf0
123 /** "Read sectors" command */
124 #define ATA_CMD_READ 0x20
126 /** "Read sectors (ext)" command */
127 #define ATA_CMD_READ_EXT 0x24
129 /** "Write sectors" command */
130 #define ATA_CMD_WRITE 0x30
132 /** "Write sectors (ext)" command */
133 #define ATA_CMD_WRITE_EXT 0x34
135 /** "Identify" command */
136 #define ATA_CMD_IDENTIFY 0xec
138 /** An ATA command */
140 /** ATA command block */
142 /** Data-out buffer (may be NULL)
144 * If non-NULL, this buffer must be ata_command::cb::count
148 /** Data-in buffer (may be NULL)
150 * If non-NULL, this buffer must be ata_command::cb::count
157 * Structure returned by ATA IDENTIFY command
159 * This is a huge structure with many fields that we don't care about,
160 * so we implement only a few fields.
162 struct ata_identity {
163 uint16_t ignore_a[60]; /* words 0-59 */
164 uint32_t lba_sectors; /* words 60-61 */
165 uint16_t ignore_b[21]; /* words 62-82 */
166 uint16_t supports_lba48; /* word 83 */
167 uint16_t ignore_c[16]; /* words 84-99 */
168 uint64_t lba48_sectors; /* words 100-103 */
169 uint16_t ignore_d[152]; /* words 104-255 */
172 /** Supports LBA48 flag */
173 #define ATA_SUPPORTS_LBA48 ( 1 << 10 )
175 /** ATA sector size */
176 #define ATA_SECTOR_SIZE 512
180 /** Block device interface */
181 struct block_device blockdev;
184 * Must be ATA_DEV_MASTER or ATA_DEV_SLAVE.
187 /** LBA48 extended addressing */
193 * @v command ATA command
194 * @ret rc Return status code
196 int ( * command ) ( struct ata_device *ata,
197 struct ata_command *command );
200 extern int init_atadev ( struct ata_device *ata );
202 #endif /* _GPXE_ATA_H */