Added support for the 80003ES2LAN Gigabit Ethernet controller (copper).
[etherboot.git] / src / drivers / net / e1000.c
index 7c57265..9d8b43e 100644 (file)
@@ -72,6 +72,9 @@ typedef enum {
  * and the corresponding inplace checks inserted instead.
  * Pieces such as LED handling that we definitely don't need are deleted.
  *
+ * Please keep the function ordering so that it is easy to produce diffs
+ * against the linux driver.
+ *
  * The following defines should not be needed normally,
  * but may be helpful for debugging purposes. */
 
@@ -84,11 +87,14 @@ typedef enum {
 
 #include "e1000_hw.h"
 
+#define RX_BUFS        8
+#define MAX_PACKET     2096
+
 /* NIC specific static variables go here */
 static struct e1000_hw hw;
 static char tx_pool[128 + 16];
 static char rx_pool[128 + 16];
-static char packet[2096];
+static char packets[MAX_PACKET * RX_BUFS];
 
 static struct e1000_tx_desc *tx_base;
 static struct e1000_rx_desc *rx_base;
@@ -114,7 +120,11 @@ static int e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16
 static void e1000_phy_hw_reset(struct e1000_hw *hw);
 static int e1000_phy_reset(struct e1000_hw *hw);
 static int e1000_detect_gig_phy(struct e1000_hw *hw);
-static void e1000_irq(struct nic *nic, irq_action_t action);
+static int e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
+static void e1000_init_rx_addrs(struct e1000_hw *hw);
+static void e1000_clear_vfta(struct e1000_hw *hw);
+static void e1000_io_write(struct e1000_hw *hw __unused, uint32_t port, uint32_t value);
+static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
 
 /* Printing macros... */
 
@@ -168,17 +178,10 @@ static void e1000_irq(struct nic *nic, irq_action_t action);
 
 #define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);}
 
-uint32_t
-e1000_io_read(struct e1000_hw *hw __unused, uint32_t port)
-{
-        return inl(port);
-}
 
-void
-e1000_io_write(struct e1000_hw *hw __unused, uint32_t port, uint32_t value)
-{
-        outl(value, port);
-}
+/******************************************************************************
+ * Inline functions from e1000_main.c of the linux driver
+ ******************************************************************************/
 
 static inline void e1000_pci_set_mwi(struct e1000_hw *hw)
 {
@@ -191,1410 +194,1088 @@ static inline void e1000_pci_clear_mwi(struct e1000_hw *hw)
                              hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
 }
 
-/******************************************************************************
- * Raises the EEPROM's clock input.
- *
- * hw - Struct containing variables accessed by shared code
- * eecd - EECD's current value
- *****************************************************************************/
-static void
-e1000_raise_ee_clk(struct e1000_hw *hw,
-                   uint32_t *eecd)
-{
-       /* Raise the clock input to the EEPROM (by setting the SK bit), and then
-        * wait <delay> microseconds.
-        */
-       *eecd = *eecd | E1000_EECD_SK;
-       E1000_WRITE_REG(hw, EECD, *eecd);
-       E1000_WRITE_FLUSH(hw);
-       udelay(hw->eeprom.delay_usec);
-}
 
 /******************************************************************************
- * Lowers the EEPROM's clock input.
- *
- * hw - Struct containing variables accessed by shared code 
- * eecd - EECD's current value
- *****************************************************************************/
-static void
-e1000_lower_ee_clk(struct e1000_hw *hw,
-                   uint32_t *eecd)
-{
-       /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 
-        * wait 50 microseconds. 
-        */
-       *eecd = *eecd & ~E1000_EECD_SK;
-       E1000_WRITE_REG(hw, EECD, *eecd);
-       E1000_WRITE_FLUSH(hw);
-       udelay(hw->eeprom.delay_usec);
-}
+ * Functions from e1000_hw.c of the linux driver
+ ******************************************************************************/
 
 /******************************************************************************
- * Shift data bits out to the EEPROM.
+ * Set the phy type member in the hw struct.
  *
  * hw - Struct containing variables accessed by shared code
- * data - data to send to the EEPROM
- * count - number of bits to shift out
  *****************************************************************************/
-static void
-e1000_shift_out_ee_bits(struct e1000_hw *hw,
-                        uint16_t data,
-                        uint16_t count)
+static int32_t
+e1000_set_phy_type(struct e1000_hw *hw)
 {
-       struct e1000_eeprom_info *eeprom = &hw->eeprom;
-       uint32_t eecd;
-       uint32_t mask;
-       
-       /* We need to shift "count" bits out to the EEPROM. So, value in the
-        * "data" parameter will be shifted out to the EEPROM one bit at a time.
-        * In order to do this, "data" must be broken down into bits. 
-        */
-       mask = 0x01 << (count - 1);
-       eecd = E1000_READ_REG(hw, EECD);
-       if (eeprom->type == e1000_eeprom_microwire) {
-               eecd &= ~E1000_EECD_DO;
-       } else if (eeprom->type == e1000_eeprom_spi) {
-               eecd |= E1000_EECD_DO;
+       DEBUGFUNC("e1000_set_phy_type");
+
+       switch(hw->phy_id) {
+       case M88E1000_E_PHY_ID:
+       case M88E1000_I_PHY_ID:
+       case M88E1011_I_PHY_ID:
+               hw->phy_type = e1000_phy_m88;
+               break;
+       case IGP01E1000_I_PHY_ID:
+               hw->phy_type = e1000_phy_igp;
+               break;
+       case GG82563_E_PHY_ID:
+               if (hw->mac_type == e1000_80003es2lan) {
+                       hw->phy_type = e1000_phy_gg82563;
+                       break;
+               }
+       default:
+               /* Should never have loaded on this device */
+               hw->phy_type = e1000_phy_undefined;
+               return -E1000_ERR_PHY_TYPE;
        }
-       do {
-               /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
-                * and then raising and then lowering the clock (the SK bit controls
-                * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
-                * by setting "DI" to "0" and then raising and then lowering the clock.
-                */
-               eecd &= ~E1000_EECD_DI;
-               
-               if(data & mask)
-                       eecd |= E1000_EECD_DI;
-               
-               E1000_WRITE_REG(hw, EECD, eecd);
-               E1000_WRITE_FLUSH(hw);
-               
-               udelay(eeprom->delay_usec);
-               
-               e1000_raise_ee_clk(hw, &eecd);
-               e1000_lower_ee_clk(hw, &eecd);
-               
-               mask = mask >> 1;
-               
-       } while(mask);
 
-       /* We leave the "DI" bit set to "0" when we leave this routine. */
-       eecd &= ~E1000_EECD_DI;
-       E1000_WRITE_REG(hw, EECD, eecd);
+       return E1000_SUCCESS;
 }
 
 /******************************************************************************
- * Shift data bits in from the EEPROM
+ * IGP phy init script - initializes the GbE PHY
  *
  * hw - Struct containing variables accessed by shared code
  *****************************************************************************/
-static uint16_t
-e1000_shift_in_ee_bits(struct e1000_hw *hw,
-                       uint16_t count)
+static void
+e1000_phy_init_script(struct e1000_hw *hw)
 {
-       uint32_t eecd;
-       uint32_t i;
-       uint16_t data;
-       
-       /* In order to read a register from the EEPROM, we need to shift 'count' 
-        * bits in from the EEPROM. Bits are "shifted in" by raising the clock
-        * input to the EEPROM (setting the SK bit), and then reading the value of
-        * the "DO" bit.  During this "shifting in" process the "DI" bit should
-        * always be clear.
-        */
-       
-       eecd = E1000_READ_REG(hw, EECD);
-       
-       eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
-       data = 0;
-       
-       for(i = 0; i < count; i++) {
-               data = data << 1;
-               e1000_raise_ee_clk(hw, &eecd);
-               
-               eecd = E1000_READ_REG(hw, EECD);
-               
-               eecd &= ~(E1000_EECD_DI);
-               if(eecd & E1000_EECD_DO)
-                       data |= 1;
-               
-               e1000_lower_ee_clk(hw, &eecd);
-       }
-       
-       return data;
-}
+       DEBUGFUNC("e1000_phy_init_script");
 
-/******************************************************************************
- * Prepares EEPROM for access
- *
- * hw - Struct containing variables accessed by shared code
- *
- * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 
- * function should be called before issuing a command to the EEPROM.
- *****************************************************************************/
-static int32_t
-e1000_acquire_eeprom(struct e1000_hw *hw)
-{
-       struct e1000_eeprom_info *eeprom = &hw->eeprom;
-       uint32_t eecd, i=0;
+#if 0
+       /* See e1000_sw_init() of the Linux driver */
+       if(hw->phy_init_script) {
+#else
+       if((hw->mac_type == e1000_82541) ||
+          (hw->mac_type == e1000_82547) ||
+          (hw->mac_type == e1000_82541_rev_2) ||
+          (hw->mac_type == e1000_82547_rev_2)) {
+#endif
+               mdelay(20);
 
-       eecd = E1000_READ_REG(hw, EECD);
+               e1000_write_phy_reg(hw,0x0000,0x0140);
 
-       /* Request EEPROM Access */
-       if(hw->mac_type > e1000_82544) {
-               eecd |= E1000_EECD_REQ;
-               E1000_WRITE_REG(hw, EECD, eecd);
-               eecd = E1000_READ_REG(hw, EECD);
-               while((!(eecd & E1000_EECD_GNT)) &&
-                     (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
-                       i++;
-                       udelay(5);
-                       eecd = E1000_READ_REG(hw, EECD);
-               }
-               if(!(eecd & E1000_EECD_GNT)) {
-                       eecd &= ~E1000_EECD_REQ;
-                       E1000_WRITE_REG(hw, EECD, eecd);
-                       DEBUGOUT("Could not acquire EEPROM grant\n");
-                       return -E1000_ERR_EEPROM;
-               }
-       }
+               mdelay(5);
 
-       /* Setup EEPROM for Read/Write */
+               if(hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547) {
+                       e1000_write_phy_reg(hw, 0x1F95, 0x0001);
 
-       if (eeprom->type == e1000_eeprom_microwire) {
-               /* Clear SK and DI */
-               eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
-               E1000_WRITE_REG(hw, EECD, eecd);
+                       e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
 
-               /* Set CS */
-               eecd |= E1000_EECD_CS;
-               E1000_WRITE_REG(hw, EECD, eecd);
-       } else if (eeprom->type == e1000_eeprom_spi) {
-               /* Clear SK and CS */
-               eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
-               E1000_WRITE_REG(hw, EECD, eecd);
-               udelay(1);
-       }
+                       e1000_write_phy_reg(hw, 0x1F79, 0x0018);
 
-       return E1000_SUCCESS;
-}
+                       e1000_write_phy_reg(hw, 0x1F30, 0x1600);
 
-/******************************************************************************
- * Returns EEPROM to a "standby" state
- * 
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static void
-e1000_standby_eeprom(struct e1000_hw *hw)
-{
-       struct e1000_eeprom_info *eeprom = &hw->eeprom;
-       uint32_t eecd;
-       
-       eecd = E1000_READ_REG(hw, EECD);
+                       e1000_write_phy_reg(hw, 0x1F31, 0x0014);
 
-       if(eeprom->type == e1000_eeprom_microwire) {
+                       e1000_write_phy_reg(hw, 0x1F32, 0x161C);
 
-               /* Deselect EEPROM */
-               eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
-               E1000_WRITE_REG(hw, EECD, eecd);
-               E1000_WRITE_FLUSH(hw);
-               udelay(eeprom->delay_usec);
-       
-               /* Clock high */
-               eecd |= E1000_EECD_SK;
-               E1000_WRITE_REG(hw, EECD, eecd);
-               E1000_WRITE_FLUSH(hw);
-               udelay(eeprom->delay_usec);
-       
-               /* Select EEPROM */
-               eecd |= E1000_EECD_CS;
-               E1000_WRITE_REG(hw, EECD, eecd);
-               E1000_WRITE_FLUSH(hw);
-               udelay(eeprom->delay_usec);
+                       e1000_write_phy_reg(hw, 0x1F94, 0x0003);
 
-               /* Clock low */
-               eecd &= ~E1000_EECD_SK;
-               E1000_WRITE_REG(hw, EECD, eecd);
-               E1000_WRITE_FLUSH(hw);
-               udelay(eeprom->delay_usec);
-       } else if(eeprom->type == e1000_eeprom_spi) {
-               /* Toggle CS to flush commands */
-               eecd |= E1000_EECD_CS;
-               E1000_WRITE_REG(hw, EECD, eecd);
-               E1000_WRITE_FLUSH(hw);
-               udelay(eeprom->delay_usec);
-               eecd &= ~E1000_EECD_CS;
-               E1000_WRITE_REG(hw, EECD, eecd);
-               E1000_WRITE_FLUSH(hw);
-               udelay(eeprom->delay_usec);
-       }
-}
+                       e1000_write_phy_reg(hw, 0x1F96, 0x003F);
 
-/******************************************************************************
- * Terminates a command by inverting the EEPROM's chip select pin
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static void
-e1000_release_eeprom(struct e1000_hw *hw)
-{
-       uint32_t eecd;
+                       e1000_write_phy_reg(hw, 0x2010, 0x0008);
+               } else {
+                       e1000_write_phy_reg(hw, 0x1F73, 0x0099);
+               }
 
-       eecd = E1000_READ_REG(hw, EECD);
+               e1000_write_phy_reg(hw, 0x0000, 0x3300);
 
-       if (hw->eeprom.type == e1000_eeprom_spi) {
-               eecd |= E1000_EECD_CS;  /* Pull CS high */
-               eecd &= ~E1000_EECD_SK; /* Lower SCK */
 
-               E1000_WRITE_REG(hw, EECD, eecd);
+               if(hw->mac_type == e1000_82547) {
+                       uint16_t fused, fine, coarse;
 
-               udelay(hw->eeprom.delay_usec);
-       } else if(hw->eeprom.type == e1000_eeprom_microwire) {
-               /* cleanup eeprom */
+                       /* Move to analog registers page */
+                       e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
 
-               /* CS on Microwire is active-high */
-               eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
+                       if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
+                               e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
 
-               E1000_WRITE_REG(hw, EECD, eecd);
+                               fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
+                               coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
 
-               /* Rising edge of clock */
-               eecd |= E1000_EECD_SK;
-               E1000_WRITE_REG(hw, EECD, eecd);
-               E1000_WRITE_FLUSH(hw);
-               udelay(hw->eeprom.delay_usec);
+                               if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
+                                       coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
+                                       fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
+                               } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
+                                       fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
 
-               /* Falling edge of clock */
-               eecd &= ~E1000_EECD_SK;
-               E1000_WRITE_REG(hw, EECD, eecd);
-               E1000_WRITE_FLUSH(hw);
-               udelay(hw->eeprom.delay_usec);
-       }
+                               fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
+                                       (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
+                                       (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
 
-       /* Stop requesting EEPROM access */
-       if(hw->mac_type > e1000_82544) {
-               eecd &= ~E1000_EECD_REQ;
-               E1000_WRITE_REG(hw, EECD, eecd);
+                               e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
+                               e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
+                                               IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
+                       }
+               }
        }
 }
 
 /******************************************************************************
- * Reads a 16 bit word from the EEPROM.
- *
+ * Set the mac type member in the hw struct.
+ * 
  * hw - Struct containing variables accessed by shared code
  *****************************************************************************/
-static int32_t
-e1000_spi_eeprom_ready(struct e1000_hw *hw)
+static int
+e1000_set_mac_type(struct e1000_hw *hw)
 {
-       uint16_t retry_count = 0;
-       uint8_t spi_stat_reg;
+       DEBUGFUNC("e1000_set_mac_type");
 
-       /* Read "Status Register" repeatedly until the LSB is cleared.  The
-        * EEPROM will signal that the command has been completed by clearing
-        * bit 0 of the internal status register.  If it's not cleared within
-        * 5 milliseconds, then error out.
-        */
-       retry_count = 0;
-       do {
-               e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
-               hw->eeprom.opcode_bits);
-               spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
-               if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
+       switch (hw->device_id) {
+       case E1000_DEV_ID_82542:
+               switch (hw->revision_id) {
+               case E1000_82542_2_0_REV_ID:
+                       hw->mac_type = e1000_82542_rev2_0;
                        break;
+               case E1000_82542_2_1_REV_ID:
+                       hw->mac_type = e1000_82542_rev2_1;
+                       break;
+               default:
+                       /* Invalid 82542 revision ID */
+                       return -E1000_ERR_MAC_TYPE;
+               }
+               break;
+       case E1000_DEV_ID_82543GC_FIBER:
+       case E1000_DEV_ID_82543GC_COPPER:
+               hw->mac_type = e1000_82543;
+               break;
+       case E1000_DEV_ID_82544EI_COPPER:
+       case E1000_DEV_ID_82544EI_FIBER:
+       case E1000_DEV_ID_82544GC_COPPER:
+       case E1000_DEV_ID_82544GC_LOM:
+               hw->mac_type = e1000_82544;
+               break;
+       case E1000_DEV_ID_82540EM:
+       case E1000_DEV_ID_82540EM_LOM:
+       case E1000_DEV_ID_82540EP:
+       case E1000_DEV_ID_82540EP_LOM:
+       case E1000_DEV_ID_82540EP_LP:
+               hw->mac_type = e1000_82540;
+               break;
+       case E1000_DEV_ID_82545EM_COPPER:
+       case E1000_DEV_ID_82545EM_FIBER:
+               hw->mac_type = e1000_82545;
+               break;
+       case E1000_DEV_ID_82545GM_COPPER:
+       case E1000_DEV_ID_82545GM_FIBER:
+       case E1000_DEV_ID_82545GM_SERDES:
+               hw->mac_type = e1000_82545_rev_3;
+               break;
+       case E1000_DEV_ID_82546EB_COPPER:
+       case E1000_DEV_ID_82546EB_FIBER:
+       case E1000_DEV_ID_82546EB_QUAD_COPPER:
+               hw->mac_type = e1000_82546;
+               break;
+       case E1000_DEV_ID_82546GB_COPPER:
+       case E1000_DEV_ID_82546GB_FIBER:
+       case E1000_DEV_ID_82546GB_SERDES:
+               hw->mac_type = e1000_82546_rev_3;
+               break;
+       case E1000_DEV_ID_82541EI:
+       case E1000_DEV_ID_82541EI_MOBILE:
+               hw->mac_type = e1000_82541;
+               break;
+       case E1000_DEV_ID_82541ER:
+       case E1000_DEV_ID_82541GI:
+       case E1000_DEV_ID_82541GI_MOBILE:
+               hw->mac_type = e1000_82541_rev_2;
+               break;
+       case E1000_DEV_ID_82547EI:
+               hw->mac_type = e1000_82547;
+               break;
+       case E1000_DEV_ID_82547GI:
+               hw->mac_type = e1000_82547_rev_2;
+               break;
+       case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
+               hw->mac_type = e1000_80003es2lan;
+               break;
+       default:
+               /* Should never have loaded on this device */
+               return -E1000_ERR_MAC_TYPE;
+       }
 
-               udelay(5);
-               retry_count += 5;
+       return E1000_SUCCESS;
+}
 
-       } while(retry_count < EEPROM_MAX_RETRY_SPI);
+/*****************************************************************************
+ * Set media type and TBI compatibility.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * **************************************************************************/
+static void
+e1000_set_media_type(struct e1000_hw *hw)
+{
+       uint32_t status;
 
-       /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
-        * only 0-5mSec on 5V devices)
-        */
-       if(retry_count >= EEPROM_MAX_RETRY_SPI) {
-               DEBUGOUT("SPI EEPROM Status error\n");
-               return -E1000_ERR_EEPROM;
+       DEBUGFUNC("e1000_set_media_type");
+       
+       if(hw->mac_type != e1000_82543) {
+               /* tbi_compatibility is only valid on 82543 */
+               hw->tbi_compatibility_en = FALSE;
        }
 
-       return E1000_SUCCESS;
+       switch (hw->device_id) {
+               case E1000_DEV_ID_82545GM_SERDES:
+               case E1000_DEV_ID_82546GB_SERDES:
+                       hw->media_type = e1000_media_type_internal_serdes;
+                       break;
+               default:
+                       if(hw->mac_type >= e1000_82543) {
+                               status = E1000_READ_REG(hw, STATUS);
+                               if(status & E1000_STATUS_TBIMODE) {
+                                       hw->media_type = e1000_media_type_fiber;
+                                       /* tbi_compatibility not valid on fiber */
+                                       hw->tbi_compatibility_en = FALSE;
+                               } else {
+                                       hw->media_type = e1000_media_type_copper;
+                               }
+                       } else {
+                               /* This is an 82542 (fiber only) */
+                               hw->media_type = e1000_media_type_fiber;
+                       }
+       }
 }
 
 /******************************************************************************
- * Reads a 16 bit word from the EEPROM.
+ * Reset the transmit and receive units; mask and clear all interrupts.
  *
  * hw - Struct containing variables accessed by shared code
- * offset - offset of  word in the EEPROM to read
- * data - word read from the EEPROM
- * words - number of words to read
  *****************************************************************************/
-static int
-e1000_read_eeprom(struct e1000_hw *hw,
-                  uint16_t offset,
-                 uint16_t words,
-                  uint16_t *data)
+static void
+e1000_reset_hw(struct e1000_hw *hw)
 {
-       struct e1000_eeprom_info *eeprom = &hw->eeprom;
-       uint32_t i = 0;
+       uint32_t ctrl;
+       uint32_t ctrl_ext;
+       uint32_t icr;
+       uint32_t manc;
        
-       DEBUGFUNC("e1000_read_eeprom");
+       DEBUGFUNC("e1000_reset_hw");
+       
+       /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
+       if(hw->mac_type == e1000_82542_rev2_0) {
+               DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
+               e1000_pci_clear_mwi(hw);
+       }
 
-       /* A check for invalid values:  offset too large, too many words, and not
-        * enough words.
+       /* Clear interrupt mask to stop board from generating interrupts */
+       DEBUGOUT("Masking off all interrupts\n");
+       E1000_WRITE_REG(hw, IMC, 0xffffffff);
+       
+       /* Disable the Transmit and Receive units.  Then delay to allow
+        * any pending transactions to complete before we hit the MAC with
+        * the global reset.
         */
-       if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
-          (words == 0)) {
-               DEBUGOUT("\"words\" parameter out of bounds\n");
-               return -E1000_ERR_EEPROM;
-       }
+       E1000_WRITE_REG(hw, RCTL, 0);
+       E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
+       E1000_WRITE_FLUSH(hw);
 
-       /*  Prepare the EEPROM for reading  */
-       if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
-               return -E1000_ERR_EEPROM;
-
-       if(eeprom->type == e1000_eeprom_spi) {
-               uint16_t word_in;
-               uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
-
-               if(e1000_spi_eeprom_ready(hw)) {
-                       e1000_release_eeprom(hw);
-                       return -E1000_ERR_EEPROM;
-               }
-
-               e1000_standby_eeprom(hw);
-
-               /* Some SPI eeproms use the 8th address bit embedded in the opcode */
-               if((eeprom->address_bits == 8) && (offset >= 128))
-                       read_opcode |= EEPROM_A8_OPCODE_SPI;
+       /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
+       hw->tbi_compatibility_on = FALSE;
 
-               /* Send the READ command (opcode + addr)  */
-               e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
-               e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
+       /* Delay to allow any outstanding PCI transactions to complete before
+        * resetting the device
+        */ 
+       mdelay(10);
 
-               /* Read the data.  The address of the eeprom internally increments with
-                * each byte (spi) being read, saving on the overhead of eeprom setup
-                * and tear-down.  The address counter will roll over if reading beyond
-                * the size of the eeprom, thus allowing the entire memory to be read
-                * starting from any offset. */
-               for (i = 0; i < words; i++) {
-                       word_in = e1000_shift_in_ee_bits(hw, 16);
-                       data[i] = (word_in >> 8) | (word_in << 8);
-               }
-       } else if(eeprom->type == e1000_eeprom_microwire) {
-               for (i = 0; i < words; i++) {
-                       /*  Send the READ command (opcode + addr)  */
-                       e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
-                                               eeprom->opcode_bits);
-                       e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
-                                               eeprom->address_bits);
+       ctrl = E1000_READ_REG(hw, CTRL);
 
-                       /* Read the data.  For microwire, each word requires the overhead
-                        * of eeprom setup and tear-down. */
-                       data[i] = e1000_shift_in_ee_bits(hw, 16);
-                       e1000_standby_eeprom(hw);
-               }
+       /* Must reset the PHY before resetting the MAC */
+       if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
+               E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
+               mdelay(5);
        }
 
-       /* End this read operation */
-       e1000_release_eeprom(hw);
+       /* Issue a global reset to the MAC.  This will reset the chip's
+        * transmit, receive, DMA, and link units.  It will not effect
+        * the current PCI configuration.  The global reset bit is self-
+        * clearing, and should clear within a microsecond.
+        */
+       DEBUGOUT("Issuing a global reset to MAC\n");
 
-       return E1000_SUCCESS;
-}
+       switch(hw->mac_type) {
+               case e1000_82544:
+               case e1000_82540:
+               case e1000_82545:
+               case e1000_82546:
+               case e1000_82541:
+               case e1000_82541_rev_2:
+                       /* These controllers can't ack the 64-bit write when issuing the
+                        * reset, so use IO-mapping as a workaround to issue the reset */
+                       E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
+                       break;
+               case e1000_82545_rev_3:
+               case e1000_82546_rev_3:
+                       /* Reset is performed on a shadow of the control register */
+                       E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
+                       break;
+               default:
+                       E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
+                       break;
+       }
 
-/******************************************************************************
- * Verifies that the EEPROM has a valid checksum
- * 
- * hw - Struct containing variables accessed by shared code
- *
- * Reads the first 64 16 bit words of the EEPROM and sums the values read.
- * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
- * valid.
- *****************************************************************************/
-static int
-e1000_validate_eeprom_checksum(struct e1000_hw *hw)
-{
-       uint16_t checksum = 0;
-       uint16_t i, eeprom_data;
+       /* After MAC reset, force reload of EEPROM to restore power-on settings to
+        * device.  Later controllers reload the EEPROM automatically, so just wait
+        * for reload to complete.
+        */
+       switch(hw->mac_type) {
+               case e1000_82542_rev2_0:
+               case e1000_82542_rev2_1:
+               case e1000_82543:
+               case e1000_82544:
+                       /* Wait for reset to complete */
+                       udelay(10);
+                       ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
+                       ctrl_ext |= E1000_CTRL_EXT_EE_RST;
+                       E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
+                       E1000_WRITE_FLUSH(hw);
+                       /* Wait for EEPROM reload */
+                       mdelay(2);
+                       break;
+               case e1000_82541:
+               case e1000_82541_rev_2:
+               case e1000_82547:
+               case e1000_82547_rev_2:
+                       /* Wait for EEPROM reload */
+                       mdelay(20);
+                       break;
+               default:
+                       /* Wait for EEPROM reload (it happens automatically) */
+                       mdelay(5);
+                       break;
+       }
 
-       DEBUGFUNC("e1000_validate_eeprom_checksum");
+       /* Disable HW ARPs on ASF enabled adapters */
+       if(hw->mac_type >= e1000_82540) {
+               manc = E1000_READ_REG(hw, MANC);
+               manc &= ~(E1000_MANC_ARP_EN);
+               E1000_WRITE_REG(hw, MANC, manc);
+       }
 
-       for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
-               if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
-                       DEBUGOUT("EEPROM Read Error\n");
-                       return -E1000_ERR_EEPROM;
-               }
-               checksum += eeprom_data;
+       if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
+               e1000_phy_init_script(hw);
        }
+
+       /* Clear interrupt mask to stop board from generating interrupts */
+       DEBUGOUT("Masking off all interrupts\n");
+       E1000_WRITE_REG(hw, IMC, 0xffffffff);
        
-       if(checksum == (uint16_t) EEPROM_SUM)
-               return E1000_SUCCESS;
-       else {
-               DEBUGOUT("EEPROM Checksum Invalid\n");    
-               return -E1000_ERR_EEPROM;
+       /* Clear any pending interrupt events. */
+       icr = E1000_READ_REG(hw, ICR);
+
+       /* If MWI was previously enabled, reenable it. */
+       if(hw->mac_type == e1000_82542_rev2_0) {
+#ifdef LINUX_DRIVER
+               if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
+#endif
+                       e1000_pci_set_mwi(hw);
        }
 }
 
 /******************************************************************************
- * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
- * second function of dual function devices
+ * Performs basic configuration of the adapter.
  *
  * hw - Struct containing variables accessed by shared code
+ * 
+ * Assumes that the controller has previously been reset and is in a 
+ * post-reset uninitialized state. Initializes the receive address registers,
+ * multicast table, and VLAN filter table. Calls routines to setup link
+ * configuration and flow control settings. Clears all on-chip counters. Leaves
+ * the transmit and receive units disabled and uninitialized.
  *****************************************************************************/
-static int 
-e1000_read_mac_addr(struct e1000_hw *hw)
+static int
+e1000_init_hw(struct e1000_hw *hw)
 {
-       uint16_t offset;
-       uint16_t eeprom_data;
-       int i;
+       uint32_t ctrl, status;
+       uint32_t i;
+       int32_t ret_val;
+       uint16_t pcix_cmd_word;
+       uint16_t pcix_stat_hi_word;
+       uint16_t cmd_mmrbc;
+       uint16_t stat_mmrbc;
+       e1000_bus_type bus_type = e1000_bus_type_unknown;
 
-       DEBUGFUNC("e1000_read_mac_addr");
+       DEBUGFUNC("e1000_init_hw");
 
-       for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
-               offset = i >> 1;
-               if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
-                       DEBUGOUT("EEPROM Read Error\n");
-                       return -E1000_ERR_EEPROM;
-               }
-               hw->mac_addr[i] = eeprom_data & 0xff;
-               hw->mac_addr[i+1] = (eeprom_data >> 8) & 0xff;
-       }
-       if(((hw->mac_type == e1000_82546) || (hw->mac_type == e1000_82546_rev_3)) &&
-               (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1))
-               /* Invert the last bit if this is the second device */
-               hw->mac_addr[5] ^= 1;
-       return E1000_SUCCESS;
-}
+       /* Set the media type and TBI compatibility */
+       e1000_set_media_type(hw);
 
-/******************************************************************************
- * Initializes receive address filters.
- *
- * hw - Struct containing variables accessed by shared code 
- *
- * Places the MAC address in receive address register 0 and clears the rest
- * of the receive addresss registers. Clears the multicast table. Assumes
- * the receiver is in reset when the routine is called.
- *****************************************************************************/
-static void
-e1000_init_rx_addrs(struct e1000_hw *hw)
-{
-       uint32_t i;
-       uint32_t addr_low;
-       uint32_t addr_high;
-       
-       DEBUGFUNC("e1000_init_rx_addrs");
+       /* Disabling VLAN filtering. */
+       DEBUGOUT("Initializing the IEEE VLAN\n");
+       E1000_WRITE_REG(hw, VET, 0);
        
-       /* Setup the receive address. */
-       DEBUGOUT("Programming MAC Address into RAR[0]\n");
-       addr_low = (hw->mac_addr[0] |
-               (hw->mac_addr[1] << 8) |
-               (hw->mac_addr[2] << 16) | (hw->mac_addr[3] << 24));
+       e1000_clear_vfta(hw);
        
-       addr_high = (hw->mac_addr[4] |
-               (hw->mac_addr[5] << 8) | E1000_RAH_AV);
+       /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
+       if(hw->mac_type == e1000_82542_rev2_0) {
+               DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
+               e1000_pci_clear_mwi(hw);
+               E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
+               E1000_WRITE_FLUSH(hw);
+               mdelay(5);
+       }
        
-       E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
-       E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
+       /* Setup the receive address. This involves initializing all of the Receive
+        * Address Registers (RARs 0 - 15).
+        */
+       e1000_init_rx_addrs(hw);
        
-       /* Zero out the other 15 receive addresses. */
-       DEBUGOUT("Clearing RAR[1-15]\n");
-       for(i = 1; i < E1000_RAR_ENTRIES; i++) {
-               E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
-               E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
+       /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
+       if(hw->mac_type == e1000_82542_rev2_0) {
+               E1000_WRITE_REG(hw, RCTL, 0);
+               E1000_WRITE_FLUSH(hw);
+               mdelay(1);
+#ifdef LINUX_DRIVER
+               if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
+#endif
+                       e1000_pci_set_mwi(hw);
        }
-}
-
-/******************************************************************************
- * Clears the VLAN filer table
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static void
-e1000_clear_vfta(struct e1000_hw *hw)
-{
-       uint32_t offset;
-    
-       for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
-               E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
-}
+       
+       /* Zero out the Multicast HASH table */
+       DEBUGOUT("Zeroing the MTA\n");
+       for(i = 0; i < E1000_MC_TBL_SIZE; i++)
+               E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
+       
+#if 0
+       /* Set the PCI priority bit correctly in the CTRL register.  This
+        * determines if the adapter gives priority to receives, or if it
+        * gives equal priority to transmits and receives.
+        */
+       if(hw->dma_fairness) {
+               ctrl = E1000_READ_REG(hw, CTRL);
+               E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
+       }
+#endif
 
-/******************************************************************************
-* Writes a value to one of the devices registers using port I/O (as opposed to
-* memory mapped I/O). Only 82544 and newer devices support port I/O. *
-* hw - Struct containing variables accessed by shared code
-* offset - offset to write to * value - value to write
-*****************************************************************************/
-void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value){
-       uint32_t io_addr = hw->io_base;
-       uint32_t io_data = hw->io_base + 4;
-       e1000_io_write(hw, io_addr, offset);
-       e1000_io_write(hw, io_data, value);
-}
+       switch(hw->mac_type) {
+               case e1000_82545_rev_3:
+               case e1000_82546_rev_3:
+                       break;
+               case e1000_80003es2lan:
+               {
+                       int32_t timeout = 200;
+                       while(timeout) {
+                               if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD) 
+                                       break;
+                               else mdelay(10);
+                               timeout--;
+                       }
+                       if(!timeout) {
+                               /* We don't want to continue accessing MAC registers. */
+                               return -E1000_ERR_RESET;
+                       }
+                       break;
+               }
+               default:
+                       if (hw->mac_type >= e1000_82543) {
+                               /* See e1000_get_bus_info() of the Linux driver */
+                               status = E1000_READ_REG(hw, STATUS);
+                               bus_type = (status & E1000_STATUS_PCIX_MODE) ?
+                                       e1000_bus_type_pcix : e1000_bus_type_pci;
+                       }
 
-/******************************************************************************
- * Set the phy type member in the hw struct.
- *
- * hw - Struct containing variables accessed by shared code
- *****************************************************************************/
-static int32_t
-e1000_set_phy_type(struct e1000_hw *hw)
-{
-       DEBUGFUNC("e1000_set_phy_type");
+                       /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
+                       if(bus_type == e1000_bus_type_pcix) {
+                               pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
+                               pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
+                               cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
+                                       PCIX_COMMAND_MMRBC_SHIFT;
+                               stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
+                                       PCIX_STATUS_HI_MMRBC_SHIFT;
+                               if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
+                                       stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
+                               if(cmd_mmrbc > stat_mmrbc) {
+                                       pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
+                                       pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
+                                       pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, pcix_cmd_word);
+                               }
+                       }
+                       break;
+       }
 
-       switch(hw->phy_id) {
-       case M88E1000_E_PHY_ID:
-       case M88E1000_I_PHY_ID:
-       case M88E1011_I_PHY_ID:
-               hw->phy_type = e1000_phy_m88;
-               break;
-       case IGP01E1000_I_PHY_ID:
-               hw->phy_type = e1000_phy_igp;
-               break;
-       default:
-               /* Should never have loaded on this device */
-               hw->phy_type = e1000_phy_undefined;
-               return -E1000_ERR_PHY_TYPE;
+       /* Call a subroutine to configure the link and setup flow control. */
+       ret_val = e1000_setup_link(hw);
+       
+       /* Set the transmit descriptor write-back policy */
+       if(hw->mac_type > e1000_82544) {
+               ctrl = E1000_READ_REG(hw, TXDCTL);
+               ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
+               E1000_WRITE_REG(hw, TXDCTL, ctrl);
        }
 
-       return E1000_SUCCESS;
+#if 0
+       /* Clear all of the statistics registers (clear on read).  It is
+        * important that we do this after we have tried to establish link
+        * because the symbol error count will increment wildly if there
+        * is no link.
+        */
+       e1000_clear_hw_cntrs(hw);
+#endif
+
+       return ret_val;
 }
 
 /******************************************************************************
- * IGP phy init script - initializes the GbE PHY
+ * Adjust SERDES output amplitude based on EEPROM setting.
  *
- * hw - Struct containing variables accessed by shared code
+ * hw - Struct containing variables accessed by shared code.
  *****************************************************************************/
-static void
-e1000_phy_init_script(struct e1000_hw *hw)
+static int32_t
+e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
 {
-       DEBUGFUNC("e1000_phy_init_script");
-
-#if 0
-       /* See e1000_sw_init() of the Linux driver */
-       if(hw->phy_init_script) {
-#else
-       if((hw->mac_type == e1000_82541) ||
-          (hw->mac_type == e1000_82547) ||
-          (hw->mac_type == e1000_82541_rev_2) ||
-          (hw->mac_type == e1000_82547_rev_2)) {
-#endif
-               mdelay(20);
-
-               e1000_write_phy_reg(hw,0x0000,0x0140);
-
-               mdelay(5);
-
-               if(hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547) {
-                       e1000_write_phy_reg(hw, 0x1F95, 0x0001);
-
-                       e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
-
-                       e1000_write_phy_reg(hw, 0x1F79, 0x0018);
-
-                       e1000_write_phy_reg(hw, 0x1F30, 0x1600);
-
-                       e1000_write_phy_reg(hw, 0x1F31, 0x0014);
-
-                       e1000_write_phy_reg(hw, 0x1F32, 0x161C);
-
-                       e1000_write_phy_reg(hw, 0x1F94, 0x0003);
-
-                       e1000_write_phy_reg(hw, 0x1F96, 0x003F);
-
-                       e1000_write_phy_reg(hw, 0x2010, 0x0008);
-               } else {
-                       e1000_write_phy_reg(hw, 0x1F73, 0x0099);
-               }
-
-               e1000_write_phy_reg(hw, 0x0000, 0x3300);
-
-
-               if(hw->mac_type == e1000_82547) {
-                       uint16_t fused, fine, coarse;
-
-                       /* Move to analog registers page */
-                       e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
+       uint16_t eeprom_data;
+       int32_t  ret_val;
 
-                       if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
-                               e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
+       DEBUGFUNC("e1000_adjust_serdes_amplitude");
 
-                               fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
-                               coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
+       if(hw->media_type != e1000_media_type_internal_serdes)
+               return E1000_SUCCESS;
 
-                               if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
-                                       coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
-                                       fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
-                               } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
-                                       fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
+       switch(hw->mac_type) {
+               case e1000_82545_rev_3:
+               case e1000_82546_rev_3:
+                       break;
+               default:
+                       return E1000_SUCCESS;
+       }
 
-                               fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
-                                       (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
-                                       (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
+       if ((ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
+                                       &eeprom_data))) {
+               return ret_val;
+       }
 
-                               e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
-                               e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
-                                               IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
-                       }
-               }
+       if(eeprom_data != EEPROM_RESERVED_WORD) {
+               /* Adjust SERDES output amplitude only. */
+               eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
+               if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL,
+                                                 eeprom_data)))
+                       return ret_val;
        }
-}
 
+       return E1000_SUCCESS;
+}
+                                                                  
 /******************************************************************************
- * Set the mac type member in the hw struct.
+ * Configures flow control and link settings.
  * 
  * hw - Struct containing variables accessed by shared code
+ * 
+ * Determines which flow control settings to use. Calls the apropriate media-
+ * specific link configuration function. Configures the flow control settings.
+ * Assuming the adapter has a valid link partner, a valid link should be
+ * established. Assumes the hardware has previously been reset and the 
+ * transmitter and receiver are not enabled.
  *****************************************************************************/
 static int
-e1000_set_mac_type(struct e1000_hw *hw)
+e1000_setup_link(struct e1000_hw *hw)
 {
-       DEBUGFUNC("e1000_set_mac_type");
+       uint32_t ctrl_ext;
+       int32_t ret_val;
+       uint16_t eeprom_data;
 
-       switch (hw->device_id) {
-       case E1000_DEV_ID_82542:
-               switch (hw->revision_id) {
-               case E1000_82542_2_0_REV_ID:
-                       hw->mac_type = e1000_82542_rev2_0;
-                       break;
-               case E1000_82542_2_1_REV_ID:
-                       hw->mac_type = e1000_82542_rev2_1;
-                       break;
-               default:
-                       /* Invalid 82542 revision ID */
-                       return -E1000_ERR_MAC_TYPE;
-               }
-               break;
-       case E1000_DEV_ID_82543GC_FIBER:
-       case E1000_DEV_ID_82543GC_COPPER:
-               hw->mac_type = e1000_82543;
-               break;
-       case E1000_DEV_ID_82544EI_COPPER:
-       case E1000_DEV_ID_82544EI_FIBER:
-       case E1000_DEV_ID_82544GC_COPPER:
-       case E1000_DEV_ID_82544GC_LOM:
-               hw->mac_type = e1000_82544;
-               break;
-       case E1000_DEV_ID_82540EM:
-       case E1000_DEV_ID_82540EM_LOM:
-       case E1000_DEV_ID_82540EP:
-       case E1000_DEV_ID_82540EP_LOM:
-       case E1000_DEV_ID_82540EP_LP:
-               hw->mac_type = e1000_82540;
-               break;
-       case E1000_DEV_ID_82545EM_COPPER:
-       case E1000_DEV_ID_82545EM_FIBER:
-               hw->mac_type = e1000_82545;
-               break;
-       case E1000_DEV_ID_82545GM_COPPER:
-       case E1000_DEV_ID_82545GM_FIBER:
-       case E1000_DEV_ID_82545GM_SERDES:
-               hw->mac_type = e1000_82545_rev_3;
-               break;
-       case E1000_DEV_ID_82546EB_COPPER:
-       case E1000_DEV_ID_82546EB_FIBER:
-       case E1000_DEV_ID_82546EB_QUAD_COPPER:
-               hw->mac_type = e1000_82546;
-               break;
-       case E1000_DEV_ID_82546GB_COPPER:
-       case E1000_DEV_ID_82546GB_FIBER:
-       case E1000_DEV_ID_82546GB_SERDES:
-               hw->mac_type = e1000_82546_rev_3;
-               break;
-       case E1000_DEV_ID_82541EI:
-       case E1000_DEV_ID_82541EI_MOBILE:
-               hw->mac_type = e1000_82541;
-               break;
-       case E1000_DEV_ID_82541ER:
-       case E1000_DEV_ID_82541GI:
-       case E1000_DEV_ID_82541GI_MOBILE:
-               hw->mac_type = e1000_82541_rev_2;
-               break;
-       case E1000_DEV_ID_82547EI:
-               hw->mac_type = e1000_82547;
-               break;
-       case E1000_DEV_ID_82547GI:
-               hw->mac_type = e1000_82547_rev_2;
-               break;
-       default:
-               /* Should never have loaded on this device */
-               return -E1000_ERR_MAC_TYPE;
+       DEBUGFUNC("e1000_setup_link");
+       
+       /* Read and store word 0x0F of the EEPROM. This word contains bits
+        * that determine the hardware's default PAUSE (flow control) mode,
+        * a bit that determines whether the HW defaults to enabling or
+        * disabling auto-negotiation, and the direction of the
+        * SW defined pins. If there is no SW over-ride of the flow
+        * control setting, then the variable hw->fc will
+        * be initialized based on a value in the EEPROM.
+        */
+       if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
+               DEBUGOUT("EEPROM Read Error\n");
+               return -E1000_ERR_EEPROM;
        }
+       
+       if(hw->fc == e1000_fc_default) {
+               if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
+                       hw->fc = e1000_fc_none;
+               else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 
+                       EEPROM_WORD0F_ASM_DIR)
+                       hw->fc = e1000_fc_tx_pause;
+               else
+                       hw->fc = e1000_fc_full;
+       }
+       
+       /* We want to save off the original Flow Control configuration just
+        * in case we get disconnected and then reconnected into a different
+        * hub or switch with different Flow Control capabilities.
+        */
+       if(hw->mac_type == e1000_82542_rev2_0)
+               hw->fc &= (~e1000_fc_tx_pause);
 
-       return E1000_SUCCESS;
-}
-
-/*****************************************************************************
- * Set media type and TBI compatibility.
- *
- * hw - Struct containing variables accessed by shared code
- * **************************************************************************/
-static void
-e1000_set_media_type(struct e1000_hw *hw)
-{
-       uint32_t status;
+#if 0
+       /* See e1000_sw_init() of the Linux driver */
+       if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
+#else
+       if((hw->mac_type < e1000_82543) && (hw->mac_type >= e1000_82543))
+#endif
+               hw->fc &= (~e1000_fc_rx_pause);
+       
+#if 0
+       hw->original_fc = hw->fc;
+#endif
 
-       DEBUGFUNC("e1000_set_media_type");
+       DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
        
-       if(hw->mac_type != e1000_82543) {
-               /* tbi_compatibility is only valid on 82543 */
-               hw->tbi_compatibility_en = FALSE;
+       /* Take the 4 bits from EEPROM word 0x0F that determine the initial
+        * polarity value for the SW controlled pins, and setup the
+        * Extended Device Control reg with that info.
+        * This is needed because one of the SW controlled pins is used for
+        * signal detection.  So this should be done before e1000_setup_pcs_link()
+        * or e1000_phy_setup() is called.
+        */
+       if(hw->mac_type == e1000_82543) {
+               ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 
+                       SWDPIO__EXT_SHIFT);
+               E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
        }
-
-       switch (hw->device_id) {
-               case E1000_DEV_ID_82545GM_SERDES:
-               case E1000_DEV_ID_82546GB_SERDES:
-                       hw->media_type = e1000_media_type_internal_serdes;
-                       break;
-               default:
-                       if(hw->mac_type >= e1000_82543) {
-                               status = E1000_READ_REG(hw, STATUS);
-                               if(status & E1000_STATUS_TBIMODE) {
-                                       hw->media_type = e1000_media_type_fiber;
-                                       /* tbi_compatibility not valid on fiber */
-                                       hw->tbi_compatibility_en = FALSE;
-                               } else {
-                                       hw->media_type = e1000_media_type_copper;
-                               }
-                       } else {
-                               /* This is an 82542 (fiber only) */
-                               hw->media_type = e1000_media_type_fiber;
-                       }
+       
+       /* Call the necessary subroutine to configure the link. */
+       ret_val = (hw->media_type == e1000_media_type_copper) ?
+               e1000_setup_copper_link(hw) :
+               e1000_setup_fiber_serdes_link(hw);
+       if (ret_val < 0) {
+               return ret_val;
+       }
+       
+       /* Initialize the flow control address, type, and PAUSE timer
+        * registers to their default values.  This is done even if flow
+        * control is disabled, because it does not hurt anything to
+        * initialize these registers.
+        */
+       DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
+       
+       E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
+       E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
+       E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
+#if 0
+       E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
+#else
+       E1000_WRITE_REG(hw, FCTTV, FC_DEFAULT_TX_TIMER);
+#endif
+       
+       /* Set the flow control receive threshold registers.  Normally,
+        * these registers will be set to a default threshold that may be
+        * adjusted later by the driver's runtime code.  However, if the
+        * ability to transmit pause frames in not enabled, then these
+        * registers will be set to 0. 
+        */
+       if(!(hw->fc & e1000_fc_tx_pause)) {
+               E1000_WRITE_REG(hw, FCRTL, 0);
+               E1000_WRITE_REG(hw, FCRTH, 0);
+       } else {
+               /* We need to set up the Receive Threshold high and low water marks
+                * as well as (optionally) enabling the transmission of XON frames.
+                */
+#if 0
+               if(hw->fc_send_xon) {
+                       E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
+                       E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
+               } else {
+                       E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
+                       E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
+               }
+#else
+               E1000_WRITE_REG(hw, FCRTL, (FC_DEFAULT_LO_THRESH | E1000_FCRTL_XONE));
+               E1000_WRITE_REG(hw, FCRTH, FC_DEFAULT_HI_THRESH);
+#endif
        }
+       return ret_val;
 }
 
 /******************************************************************************
- * Reset the transmit and receive units; mask and clear all interrupts.
+ * Sets up link for a fiber based or serdes based adapter
  *
  * hw - Struct containing variables accessed by shared code
+ *
+ * Manipulates Physical Coding Sublayer functions in order to configure
+ * link. Assumes the hardware has been previously reset and the transmitter
+ * and receiver are not enabled.
  *****************************************************************************/
-static void
-e1000_reset_hw(struct e1000_hw *hw)
+static int
+e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
 {
        uint32_t ctrl;
-       uint32_t ctrl_ext;
-       uint32_t icr;
-       uint32_t manc;
-       
-       DEBUGFUNC("e1000_reset_hw");
-       
-       /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
-       if(hw->mac_type == e1000_82542_rev2_0) {
-               DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
-               e1000_pci_clear_mwi(hw);
-       }
-
-       /* Clear interrupt mask to stop board from generating interrupts */
-       DEBUGOUT("Masking off all interrupts\n");
-       E1000_WRITE_REG(hw, IMC, 0xffffffff);
-       
-       /* Disable the Transmit and Receive units.  Then delay to allow
-        * any pending transactions to complete before we hit the MAC with
-        * the global reset.
-        */
-       E1000_WRITE_REG(hw, RCTL, 0);
-       E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
-       E1000_WRITE_FLUSH(hw);
-
-       /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
-       hw->tbi_compatibility_on = FALSE;
+       uint32_t status;
+       uint32_t txcw = 0;
+       uint32_t i;
+       uint32_t signal = 0;
+       int32_t ret_val;
 
-       /* Delay to allow any outstanding PCI transactions to complete before
-        * resetting the device
-        */ 
-       mdelay(10);
+       DEBUGFUNC("e1000_setup_fiber_serdes_link");
 
+       /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 
+        * set when the optics detect a signal. On older adapters, it will be 
+        * cleared when there is a signal.  This applies to fiber media only.
+        * If we're on serdes media, adjust the output amplitude to value set in
+        * the EEPROM.
+        */
        ctrl = E1000_READ_REG(hw, CTRL);
+       if(hw->media_type == e1000_media_type_fiber)
+               signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
 
-       /* Must reset the PHY before resetting the MAC */
-       if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
-               E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
-               mdelay(5);
-       }
+       if((ret_val = e1000_adjust_serdes_amplitude(hw)))
+               return ret_val;
 
-       /* Issue a global reset to the MAC.  This will reset the chip's
-        * transmit, receive, DMA, and link units.  It will not effect
-        * the current PCI configuration.  The global reset bit is self-
-        * clearing, and should clear within a microsecond.
-        */
-       DEBUGOUT("Issuing a global reset to MAC\n");
+       /* Take the link out of reset */
+       ctrl &= ~(E1000_CTRL_LRST);
 
-       switch(hw->mac_type) {
-               case e1000_82544:
-               case e1000_82540:
-               case e1000_82545:
-               case e1000_82546:
-               case e1000_82541:
-               case e1000_82541_rev_2:
-                       /* These controllers can't ack the 64-bit write when issuing the
-                        * reset, so use IO-mapping as a workaround to issue the reset */
-                       E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
-                       break;
-               case e1000_82545_rev_3:
-               case e1000_82546_rev_3:
-                       /* Reset is performed on a shadow of the control register */
-                       E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
-                       break;
-               default:
-                       E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
-                       break;
-       }
+#if 0
+       /* Adjust VCO speed to improve BER performance */
+       if((ret_val = e1000_set_vco_speed(hw)))
+               return ret_val;
+#endif
 
-       /* After MAC reset, force reload of EEPROM to restore power-on settings to
-        * device.  Later controllers reload the EEPROM automatically, so just wait
-        * for reload to complete.
+       e1000_config_collision_dist(hw);
+       
+       /* Check for a software override of the flow control settings, and setup
+        * the device accordingly.  If auto-negotiation is enabled, then software
+        * will have to set the "PAUSE" bits to the correct value in the Tranmsit
+        * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
+        * auto-negotiation is disabled, then software will have to manually 
+        * configure the two flow control enable bits in the CTRL register.
+        *
+        * The possible values of the "fc" parameter are:
+        *      0:  Flow control is completely disabled
+        *      1:  Rx flow control is enabled (we can receive pause frames, but 
+        *          not send pause frames).
+        *      2:  Tx flow control is enabled (we can send pause frames but we do
+        *          not support receiving pause frames).
+        *      3:  Both Rx and TX flow control (symmetric) are enabled.
         */
-       switch(hw->mac_type) {
-               case e1000_82542_rev2_0:
-               case e1000_82542_rev2_1:
-               case e1000_82543:
-               case e1000_82544:
-                       /* Wait for reset to complete */
-                       udelay(10);
-                       ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
-                       ctrl_ext |= E1000_CTRL_EXT_EE_RST;
-                       E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
-                       E1000_WRITE_FLUSH(hw);
-                       /* Wait for EEPROM reload */
-                       mdelay(2);
-                       break;
-               case e1000_82541:
-               case e1000_82541_rev_2:
-               case e1000_82547:
-               case e1000_82547_rev_2:
-                       /* Wait for EEPROM reload */
-                       mdelay(20);
-                       break;
-               default:
-                       /* Wait for EEPROM reload (it happens automatically) */
-                       mdelay(5);
-                       break;
-       }
-
-       /* Disable HW ARPs on ASF enabled adapters */
-       if(hw->mac_type >= e1000_82540) {
-               manc = E1000_READ_REG(hw, MANC);
-               manc &= ~(E1000_MANC_ARP_EN);
-               E1000_WRITE_REG(hw, MANC, manc);
+       switch (hw->fc) {
+       case e1000_fc_none:
+               /* Flow control is completely disabled by a software over-ride. */
+               txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
+               break;
+       case e1000_fc_rx_pause:
+               /* RX Flow control is enabled and TX Flow control is disabled by a 
+                * software over-ride. Since there really isn't a way to advertise 
+                * that we are capable of RX Pause ONLY, we will advertise that we
+                * support both symmetric and asymmetric RX PAUSE. Later, we will
+                *  disable the adapter's ability to send PAUSE frames.
+                */
+               txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
+               break;
+       case e1000_fc_tx_pause:
+               /* TX Flow control is enabled, and RX Flow control is disabled, by a 
+                * software over-ride.
+                */
+               txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
+               break;
+       case e1000_fc_full:
+               /* Flow control (both RX and TX) is enabled by a software over-ride. */
+               txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
+               break;
+       default:
+               DEBUGOUT("Flow control param set incorrectly\n");
+               return -E1000_ERR_CONFIG;
+               break;
        }
-
-       if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
-               e1000_phy_init_script(hw);
+       
+       /* Since auto-negotiation is enabled, take the link out of reset (the link
+        * will be in reset, because we previously reset the chip). This will
+        * restart auto-negotiation.  If auto-neogtiation is successful then the
+        * link-up status bit will be set and the flow control enable bits (RFCE
+        * and TFCE) will be set according to their negotiated value.
+        */
+       DEBUGOUT("Auto-negotiation enabled\n");
+       
+       E1000_WRITE_REG(hw, TXCW, txcw);
+       E1000_WRITE_REG(hw, CTRL, ctrl);
+       E1000_WRITE_FLUSH(hw);
+       
+       hw->txcw = txcw;
+       mdelay(1);
+       
+       /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
+        * indication in the Device Status Register.  Time-out if a link isn't 
+        * seen in 500 milliseconds seconds (Auto-negotiation should complete in 
+        * less than 500 milliseconds even if the other end is doing it in SW).
+        * For internal serdes, we just assume a signal is present, then poll.
+        */
+       if(hw->media_type == e1000_media_type_internal_serdes ||
+          (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
+               DEBUGOUT("Looking for Link\n");
+               for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
+                       mdelay(10);
+                       status = E1000_READ_REG(hw, STATUS);
+                       if(status & E1000_STATUS_LU) break;
+               }
+               if(i == (LINK_UP_TIMEOUT / 10)) {
+                       DEBUGOUT("Never got a valid link from auto-neg!!!\n");
+                       hw->autoneg_failed = 1;
+                       /* AutoNeg failed to achieve a link, so we'll call 
+                        * e1000_check_for_link. This routine will force the link up if
+                        * we detect a signal. This will allow us to communicate with
+                        * non-autonegotiating link partners.
+                        */
+                       if((ret_val = e1000_check_for_link(hw))) {
+                               DEBUGOUT("Error while checking for link\n");
+                               return ret_val;
+                       }
+                       hw->autoneg_failed = 0;
+               } else {
+                       hw->autoneg_failed = 0;
+                       DEBUGOUT("Valid Link Found\n");
+               }
+       } else {
+               DEBUGOUT("No Signal Detected\n");
        }
+       return E1000_SUCCESS;
+}
 
-       /* Clear interrupt mask to stop board from generating interrupts */
-       DEBUGOUT("Masking off all interrupts\n");
-       E1000_WRITE_REG(hw, IMC, 0xffffffff);
+int32_t
+e1000_read_kmrn_reg(struct e1000_hw *hw,
+                       uint32_t reg_addr,
+                       uint16_t *data)
+{
+       uint32_t reg_val;
+       DEBUGFUNC("e1000_read_kmrn_reg");
        
-       /* Clear any pending interrupt events. */
-       icr = E1000_READ_REG(hw, ICR);
+       /* Write register address */
+       reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
+                       E1000_KUMCTRLSTA_OFFSET) |
+                       E1000_KUMCTRLSTA_REN;
+       E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
+       udelay(2);
 
-       /* If MWI was previously enabled, reenable it. */
-       if(hw->mac_type == e1000_82542_rev2_0) {
-#ifdef LINUX_DRIVER
-               if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
-#endif
-                       e1000_pci_set_mwi(hw);
-       }
+       /* Read the data returned */
+       reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
+       *data = (uint16_t)reg_val;
+
+       return E1000_SUCCESS;
 }
 
-/******************************************************************************
- * Performs basic configuration of the adapter.
- *
- * hw - Struct containing variables accessed by shared code
- * 
- * Assumes that the controller has previously been reset and is in a 
- * post-reset uninitialized state. Initializes the receive address registers,
- * multicast table, and VLAN filter table. Calls routines to setup link
- * configuration and flow control settings. Clears all on-chip counters. Leaves
- * the transmit and receive units disabled and uninitialized.
- *****************************************************************************/
-static int
-e1000_init_hw(struct e1000_hw *hw)
+int32_t
+e1000_write_kmrn_reg(struct e1000_hw *hw,
+                       uint32_t reg_addr,
+                       uint16_t data)
+{
+       uint32_t reg_val;
+       DEBUGFUNC("e1000_write_kmrn_reg");
+
+       reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
+                       E1000_KUMCTRLSTA_OFFSET) | data;
+       E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
+       udelay(2);
+
+       return E1000_SUCCESS;
+}
+
+/********************************************************************
+* Copper link setup for e1000_phy_gg82563 series.
+*
+* hw - Struct containing variables accessed by shared code
+*********************************************************************/
+
+static int32_t
+e1000_copper_link_ggp_setup(struct e1000_hw *hw)
 {
-       uint32_t ctrl, status;
-       uint32_t i;
        int32_t ret_val;
-       uint16_t pcix_cmd_word;
-       uint16_t pcix_stat_hi_word;
-       uint16_t cmd_mmrbc;
-       uint16_t stat_mmrbc;
-       e1000_bus_type bus_type = e1000_bus_type_unknown;
+       uint16_t phy_data;
+       uint32_t reg_data;
 
-       DEBUGFUNC("e1000_init_hw");
+       DEBUGFUNC("e1000_copper_link_ggp_setup\n");
 
-       /* Set the media type and TBI compatibility */
-       e1000_set_media_type(hw);
+       /* Enable CRS on TX for half-duplex operation. */
+       ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
+                                    &phy_data);
+       if(ret_val)
+               return ret_val;
 
-       /* Disabling VLAN filtering. */
-       DEBUGOUT("Initializing the IEEE VLAN\n");
-       E1000_WRITE_REG(hw, VET, 0);
-       
-       e1000_clear_vfta(hw);
-       
-       /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
-       if(hw->mac_type == e1000_82542_rev2_0) {
-               DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
-               e1000_pci_clear_mwi(hw);
-               E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
-               E1000_WRITE_FLUSH(hw);
-               mdelay(5);
-       }
-       
-       /* Setup the receive address. This involves initializing all of the Receive
-        * Address Registers (RARs 0 - 15).
+       phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
+       /* Use 25MHz for both link down and 1000BASE-T for Tx clock */
+       phy_data |= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
+
+       ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
+                                      phy_data);
+       if(ret_val)
+               return ret_val;
+       /* Options:
+        *   MDI/MDI-X = 0 (default)
+        *   0 - Auto for all speeds
+        *   1 - MDI mode
+        *   2 - MDI-X mode
+        *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
         */
-       e1000_init_rx_addrs(hw);
-       
-       /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
-       if(hw->mac_type == e1000_82542_rev2_0) {
-               E1000_WRITE_REG(hw, RCTL, 0);
-               E1000_WRITE_FLUSH(hw);
-               mdelay(1);
-#ifdef LINUX_DRIVER
-               if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
-#endif
-                       e1000_pci_set_mwi(hw);
-       }
-       
-       /* Zero out the Multicast HASH table */
-       DEBUGOUT("Zeroing the MTA\n");
-       for(i = 0; i < E1000_MC_TBL_SIZE; i++)
-               E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
-       
-#if 0
-       /* Set the PCI priority bit correctly in the CTRL register.  This
-        * determines if the adapter gives priority to receives, or if it
-        * gives equal priority to transmits and receives.
+       ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
+       if(ret_val)
+               return ret_val;
+
+       phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
+
+       phy_data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
+
+       /* Options:
+        *   disable_polarity_correction = 0 (default)
+        *       Automatic Correction for Reversed Cable Polarity
+        *   0 - Disabled
+        *   1 - Enabled
         */
-       if(hw->dma_fairness) {
-               ctrl = E1000_READ_REG(hw, CTRL);
-               E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
+       phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
+       ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
+
+       if(ret_val)
+               return ret_val;
+
+       /* SW Reset the PHY so all changes take effect */
+       ret_val = e1000_phy_reset(hw);
+       if (ret_val) {
+           DEBUGOUT("Error Resetting the PHY\n");
+           return ret_val;
        }
-#endif
 
-       switch(hw->mac_type) {
-               case e1000_82545_rev_3:
-               case e1000_82546_rev_3:
-                       break;
-               default:
-                       if (hw->mac_type >= e1000_82543) {
-                               /* See e1000_get_bus_info() of the Linux driver */
-                               status = E1000_READ_REG(hw, STATUS);
-                               bus_type = (status & E1000_STATUS_PCIX_MODE) ?
-                                       e1000_bus_type_pcix : e1000_bus_type_pci;
-                       }
-
-                       /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
-                       if(bus_type == e1000_bus_type_pcix) {
-                               pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
-                               pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
-                               cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
-                                       PCIX_COMMAND_MMRBC_SHIFT;
-                               stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
-                                       PCIX_STATUS_HI_MMRBC_SHIFT;
-                               if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
-                                       stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
-                               if(cmd_mmrbc > stat_mmrbc) {
-                                       pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
-                                       pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
-                                       pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, pcix_cmd_word);
-                               }
-                       }
-                       break;
-       }
-
-       /* Call a subroutine to configure the link and setup flow control. */
-       ret_val = e1000_setup_link(hw);
-       
-       /* Set the transmit descriptor write-back policy */
-       if(hw->mac_type > e1000_82544) {
-               ctrl = E1000_READ_REG(hw, TXDCTL);
-               ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
-               E1000_WRITE_REG(hw, TXDCTL, ctrl);
-       }
+       if (hw->mac_type == e1000_80003es2lan) {
+               /* Bypass RX and TX FIFO's */
+               ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
+                                               E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS |
+                                               E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
+               if (ret_val)
+                               return ret_val;
 
-#if 0
-       /* Clear all of the statistics registers (clear on read).  It is
-        * important that we do this after we have tried to establish link
-        * because the symbol error count will increment wildly if there
-        * is no link.
-        */
-       e1000_clear_hw_cntrs(hw);
-#endif
+               ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
+               if (ret_val)
+                       ret_val;
 
-       return ret_val;
-}
+               phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
+               ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
 
-/******************************************************************************
- * Adjust SERDES output amplitude based on EEPROM setting.
- *
- * hw - Struct containing variables accessed by shared code.
- *****************************************************************************/
-static int32_t
-e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
-{
-       uint16_t eeprom_data;
-       int32_t  ret_val;
+               if (ret_val)
+                       return ret_val;
 
-       DEBUGFUNC("e1000_adjust_serdes_amplitude");
+               reg_data = E1000_READ_REG(hw, CTRL_EXT);
+               reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
+               E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
+       
+               ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
+                                                       &phy_data);
+               if (ret_val)
+                       return ret_val;
 
-       if(hw->media_type != e1000_media_type_internal_serdes)
-               return E1000_SUCCESS;
+               /* Enable Electrical Idle on the PHY */
+               phy_data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
+               ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
+                                                       phy_data);
+       
+               if (ret_val)
+                       return ret_val;
 
-       switch(hw->mac_type) {
-               case e1000_82545_rev_3:
-               case e1000_82546_rev_3:
-                       break;
-               default:
-                       return E1000_SUCCESS;
-       }
+               ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
+                                                       &phy_data);
+               if (ret_val)
+                       return ret_val;
 
-       if ((ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
-                                       &eeprom_data))) {
-               return ret_val;
-       }
+               /* Disable Pass False Carrier on the PHY */
+               phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
 
-       if(eeprom_data != EEPROM_RESERVED_WORD) {
-               /* Adjust SERDES output amplitude only. */
-               eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
-               if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL,
-                                                 eeprom_data)))
+               ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
+                                                       phy_data);
+               if (ret_val)
                        return ret_val;
        }
 
        return E1000_SUCCESS;
 }
-                                                                  
+
 /******************************************************************************
- * Configures flow control and link settings.
- * 
- * hw - Struct containing variables accessed by shared code
- * 
- * Determines which flow control settings to use. Calls the apropriate media-
- * specific link configuration function. Configures the flow control settings.
- * Assuming the adapter has a valid link partner, a valid link should be
- * established. Assumes the hardware has previously been reset and the 
- * transmitter and receiver are not enabled.
- *****************************************************************************/
+* Detects which PHY is present and the speed and duplex
+*
+* hw - Struct containing variables accessed by shared code
+******************************************************************************/
 static int
-e1000_setup_link(struct e1000_hw *hw)
+e1000_setup_copper_link(struct e1000_hw *hw)
 {
-       uint32_t ctrl_ext;
+       uint32_t ctrl;
        int32_t ret_val;
-       uint16_t eeprom_data;
-
-       DEBUGFUNC("e1000_setup_link");
-       
-       /* Read and store word 0x0F of the EEPROM. This word contains bits
-        * that determine the hardware's default PAUSE (flow control) mode,
-        * a bit that determines whether the HW defaults to enabling or
-        * disabling auto-negotiation, and the direction of the
-        * SW defined pins. If there is no SW over-ride of the flow
-        * control setting, then the variable hw->fc will
-        * be initialized based on a value in the EEPROM.
-        */
-       if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
-               DEBUGOUT("EEPROM Read Error\n");
-               return -E1000_ERR_EEPROM;
-       }
+       uint16_t i;
+       uint16_t phy_data;
        
-       if(hw->fc == e1000_fc_default) {
-               if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
-                       hw->fc = e1000_fc_none;
-               else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 
-                       EEPROM_WORD0F_ASM_DIR)
-                       hw->fc = e1000_fc_tx_pause;
-               else
-                       hw->fc = e1000_fc_full;
-       }
+       DEBUGFUNC("e1000_setup_copper_link");
        
-       /* We want to save off the original Flow Control configuration just
-        * in case we get disconnected and then reconnected into a different
-        * hub or switch with different Flow Control capabilities.
-        */
-       if(hw->mac_type == e1000_82542_rev2_0)
-               hw->fc &= (~e1000_fc_tx_pause);
+       ctrl = E1000_READ_REG(hw, CTRL);
 
-#if 0
-       /* See e1000_sw_init() of the Linux driver */
-       if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
-#else
-       if((hw->mac_type < e1000_82543) && (hw->mac_type >= e1000_82543))
-#endif
-               hw->fc &= (~e1000_fc_rx_pause);
-       
-#if 0
-       hw->original_fc = hw->fc;
-#endif
+       if(hw->mac_type == e1000_80003es2lan) {
+               uint16_t reg_data;
+               /* Set the mac to wait the maximum time between each
+                * iteration and increase the max iterations when
+                * polling the phy; this fixes erroneous timeouts at 10Mbps. */
+               ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
+               if (ret_val)
+                       return ret_val;
+               ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
+               if (ret_val)
+                       return ret_val;
+               reg_data |= 0x3F;
+               ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
+               if (ret_val)
+                       return ret_val;
+               ret_val = e1000_read_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
+                                                                       &reg_data);
+               if (ret_val)
+                       return ret_val;
+               reg_data |= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
+               ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
+                                                                       reg_data);
+               if (ret_val)
+                       return ret_val;
+       }
 
-       DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
-       
-       /* Take the 4 bits from EEPROM word 0x0F that determine the initial
-        * polarity value for the SW controlled pins, and setup the
-        * Extended Device Control reg with that info.
-        * This is needed because one of the SW controlled pins is used for
-        * signal detection.  So this should be done before e1000_setup_pcs_link()
-        * or e1000_phy_setup() is called.
+       /* With 82543, we need to force speed and duplex on the MAC equal to what
+        * the PHY speed and duplex configuration is. In addition, we need to
+        * perform a hardware reset on the PHY to take it out of reset.
         */
-       if(hw->mac_type == e1000_82543) {
-               ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 
-                       SWDPIO__EXT_SHIFT);
-               E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
+       if(hw->mac_type > e1000_82543) {
+               ctrl |= E1000_CTRL_SLU;
+               ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
+               E1000_WRITE_REG(hw, CTRL, ctrl);
+       } else {
+               ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
+               E1000_WRITE_REG(hw, CTRL, ctrl);
+               e1000_phy_hw_reset(hw);
        }
        
-       /* Call the necessary subroutine to configure the link. */
-       ret_val = (hw->media_type == e1000_media_type_copper) ?
-               e1000_setup_copper_link(hw) :
-               e1000_setup_fiber_serdes_link(hw);
-       if (ret_val < 0) {
+       /* Make sure we have a valid PHY */
+       if((ret_val = e1000_detect_gig_phy(hw))) {
+               DEBUGOUT("Error, did not detect valid phy.\n");
                return ret_val;
        }
-       
-       /* Initialize the flow control address, type, and PAUSE timer
-        * registers to their default values.  This is done even if flow
-        * control is disabled, because it does not hurt anything to
-        * initialize these registers.
-        */
-       DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
-       
-       E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
-       E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
-       E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
+       DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
+
+       if (hw->phy_type == e1000_phy_gg82563) {
+               ret_val = e1000_copper_link_ggp_setup(hw);
+               if(ret_val)
+                       return ret_val;
+       }
+
+       if(hw->mac_type <= e1000_82543 ||
+          hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
 #if 0
-       E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
+          hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
+               hw->phy_reset_disable = FALSE;
+
+       if(!hw->phy_reset_disable) {
 #else
-       E1000_WRITE_REG(hw, FCTTV, FC_DEFAULT_TX_TIMER);
+          hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2 || 
+                                               hw->mac_type == e1000_80003es2lan) {
 #endif
-       
-       /* Set the flow control receive threshold registers.  Normally,
-        * these registers will be set to a default threshold that may be
-        * adjusted later by the driver's runtime code.  However, if the
-        * ability to transmit pause frames in not enabled, then these
-        * registers will be set to 0. 
-        */
-       if(!(hw->fc & e1000_fc_tx_pause)) {
-               E1000_WRITE_REG(hw, FCRTL, 0);
-               E1000_WRITE_REG(hw, FCRTH, 0);
-       } else {
-               /* We need to set up the Receive Threshold high and low water marks
-                * as well as (optionally) enabling the transmission of XON frames.
-                */
+       if (hw->phy_type == e1000_phy_igp || hw->phy_type == e1000_phy_gg82563) {
+
+               if((ret_val = e1000_phy_reset(hw))) {
+                       DEBUGOUT("Error Resetting the PHY\n");
+                       return ret_val;
+               }
+
+               /* Wait 10ms for MAC to configure PHY from eeprom settings */
+               mdelay(15);
+
 #if 0
-               if(hw->fc_send_xon) {
-                       E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
-                       E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
-               } else {
-                       E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
-                       E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
-               }
-#else
-               E1000_WRITE_REG(hw, FCRTL, (FC_DEFAULT_LO_THRESH | E1000_FCRTL_XONE));
-               E1000_WRITE_REG(hw, FCRTH, FC_DEFAULT_HI_THRESH);
-#endif
-       }
-       return ret_val;
-}
-
-/******************************************************************************
- * Sets up link for a fiber based or serdes based adapter
- *
- * hw - Struct containing variables accessed by shared code
- *
- * Manipulates Physical Coding Sublayer functions in order to configure
- * link. Assumes the hardware has been previously reset and the transmitter
- * and receiver are not enabled.
- *****************************************************************************/
-static int
-e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
-{
-       uint32_t ctrl;
-       uint32_t status;
-       uint32_t txcw = 0;
-       uint32_t i;
-       uint32_t signal = 0;
-       int32_t ret_val;
-
-       DEBUGFUNC("e1000_setup_fiber_serdes_link");
-
-       /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 
-        * set when the optics detect a signal. On older adapters, it will be 
-        * cleared when there is a signal.  This applies to fiber media only.
-        * If we're on serdes media, adjust the output amplitude to value set in
-        * the EEPROM.
-        */
-       ctrl = E1000_READ_REG(hw, CTRL);
-       if(hw->media_type == e1000_media_type_fiber)
-               signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
-
-       if((ret_val = e1000_adjust_serdes_amplitude(hw)))
-               return ret_val;
-
-       /* Take the link out of reset */
-       ctrl &= ~(E1000_CTRL_LRST);
-
-#if 0
-       /* Adjust VCO speed to improve BER performance */
-       if((ret_val = e1000_set_vco_speed(hw)))
-               return ret_val;
-#endif
-
-       e1000_config_collision_dist(hw);
-       
-       /* Check for a software override of the flow control settings, and setup
-        * the device accordingly.  If auto-negotiation is enabled, then software
-        * will have to set the "PAUSE" bits to the correct value in the Tranmsit
-        * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
-        * auto-negotiation is disabled, then software will have to manually 
-        * configure the two flow control enable bits in the CTRL register.
-        *
-        * The possible values of the "fc" parameter are:
-        *      0:  Flow control is completely disabled
-        *      1:  Rx flow control is enabled (we can receive pause frames, but 
-        *          not send pause frames).
-        *      2:  Tx flow control is enabled (we can send pause frames but we do
-        *          not support receiving pause frames).
-        *      3:  Both Rx and TX flow control (symmetric) are enabled.
-        */
-       switch (hw->fc) {
-       case e1000_fc_none:
-               /* Flow control is completely disabled by a software over-ride. */
-               txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
-               break;
-       case e1000_fc_rx_pause:
-               /* RX Flow control is enabled and TX Flow control is disabled by a 
-                * software over-ride. Since there really isn't a way to advertise 
-                * that we are capable of RX Pause ONLY, we will advertise that we
-                * support both symmetric and asymmetric RX PAUSE. Later, we will
-                *  disable the adapter's ability to send PAUSE frames.
-                */
-               txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
-               break;
-       case e1000_fc_tx_pause:
-               /* TX Flow control is enabled, and RX Flow control is disabled, by a 
-                * software over-ride.
-                */
-               txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
-               break;
-       case e1000_fc_full:
-               /* Flow control (both RX and TX) is enabled by a software over-ride. */
-               txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
-               break;
-       default:
-               DEBUGOUT("Flow control param set incorrectly\n");
-               return -E1000_ERR_CONFIG;
-               break;
-       }
-       
-       /* Since auto-negotiation is enabled, take the link out of reset (the link
-        * will be in reset, because we previously reset the chip). This will
-        * restart auto-negotiation.  If auto-neogtiation is successful then the
-        * link-up status bit will be set and the flow control enable bits (RFCE
-        * and TFCE) will be set according to their negotiated value.
-        */
-       DEBUGOUT("Auto-negotiation enabled\n");
-       
-       E1000_WRITE_REG(hw, TXCW, txcw);
-       E1000_WRITE_REG(hw, CTRL, ctrl);
-       E1000_WRITE_FLUSH(hw);
-       
-       hw->txcw = txcw;
-       mdelay(1);
-       
-       /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
-        * indication in the Device Status Register.  Time-out if a link isn't 
-        * seen in 500 milliseconds seconds (Auto-negotiation should complete in 
-        * less than 500 milliseconds even if the other end is doing it in SW).
-        * For internal serdes, we just assume a signal is present, then poll.
-        */
-       if(hw->media_type == e1000_media_type_internal_serdes ||
-          (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
-               DEBUGOUT("Looking for Link\n");
-               for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
-                       mdelay(10);
-                       status = E1000_READ_REG(hw, STATUS);
-                       if(status & E1000_STATUS_LU) break;
-               }
-               if(i == (LINK_UP_TIMEOUT / 10)) {
-                       DEBUGOUT("Never got a valid link from auto-neg!!!\n");
-                       hw->autoneg_failed = 1;
-                       /* AutoNeg failed to achieve a link, so we'll call 
-                        * e1000_check_for_link. This routine will force the link up if
-                        * we detect a signal. This will allow us to communicate with
-                        * non-autonegotiating link partners.
-                        */
-                       if((ret_val = e1000_check_for_link(hw))) {
-                               DEBUGOUT("Error while checking for link\n");
-                               return ret_val;
-                       }
-                       hw->autoneg_failed = 0;
-               } else {
-                       hw->autoneg_failed = 0;
-                       DEBUGOUT("Valid Link Found\n");
-               }
-       } else {
-               DEBUGOUT("No Signal Detected\n");
-       }
-       return E1000_SUCCESS;
-}
-
-/******************************************************************************
-* Detects which PHY is present and the speed and duplex
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-static int
-e1000_setup_copper_link(struct e1000_hw *hw)
-{
-       uint32_t ctrl;
-       int32_t ret_val;
-       uint16_t i;
-       uint16_t phy_data;
-       
-       DEBUGFUNC("e1000_setup_copper_link");
-       
-       ctrl = E1000_READ_REG(hw, CTRL);
-       /* With 82543, we need to force speed and duplex on the MAC equal to what
-        * the PHY speed and duplex configuration is. In addition, we need to
-        * perform a hardware reset on the PHY to take it out of reset.
-        */
-       if(hw->mac_type > e1000_82543) {
-               ctrl |= E1000_CTRL_SLU;
-               ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
-               E1000_WRITE_REG(hw, CTRL, ctrl);
-       } else {
-               ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
-               E1000_WRITE_REG(hw, CTRL, ctrl);
-               e1000_phy_hw_reset(hw);
-       }
-       
-       /* Make sure we have a valid PHY */
-       if((ret_val = e1000_detect_gig_phy(hw))) {
-               DEBUGOUT("Error, did not detect valid phy.\n");
-               return ret_val;
-       }
-       DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
-
-       if(hw->mac_type <= e1000_82543 ||
-          hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
-#if 0
-          hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
-               hw->phy_reset_disable = FALSE;
-
-       if(!hw->phy_reset_disable) {
-#else
-          hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
-#endif
-       if (hw->phy_type == e1000_phy_igp) {
-
-               if((ret_val = e1000_phy_reset(hw))) {
-                       DEBUGOUT("Error Resetting the PHY\n");
-                       return ret_val;
-               }
-
-               /* Wait 10ms for MAC to configure PHY from eeprom settings */
-               mdelay(15);
-
-#if 0
-               /* disable lplu d3 during driver init */
-               if((ret_val = e1000_set_d3_lplu_state(hw, FALSE))) {
-                       DEBUGOUT("Error Disabling LPLU D3\n");
-                       return ret_val;
+               /* disable lplu d3 during driver init */
+               if((ret_val = e1000_set_d3_lplu_state(hw, FALSE))) {
+                       DEBUGOUT("Error Disabling LPLU D3\n");
+                       return ret_val;
                }
 
                /* Configure mdi-mdix settings */
@@ -2616,636 +2297,1192 @@ e1000_get_speed_and_duplex(struct e1000_hw *hw,
                        *speed = SPEED_10;
                        DEBUGOUT("10 Mbs, ");
                }
-               
-               if(status & E1000_STATUS_FD) {
-                       *duplex = FULL_DUPLEX;
-                       DEBUGOUT("Full Duplex\r\n");
+               
+               if(status & E1000_STATUS_FD) {
+                       *duplex = FULL_DUPLEX;
+                       DEBUGOUT("Full Duplex\r\n");
+               } else {
+                       *duplex = HALF_DUPLEX;
+                       DEBUGOUT(" Half Duplex\r\n");
+               }
+       } else {
+               DEBUGOUT("1000 Mbs, Full Duplex\r\n");
+               *speed = SPEED_1000;
+               *duplex = FULL_DUPLEX;
+       }
+}
+
+/******************************************************************************
+* Blocks until autoneg completes or times out (~4.5 seconds)
+*
+* hw - Struct containing variables accessed by shared code
+******************************************************************************/
+static int
+e1000_wait_autoneg(struct e1000_hw *hw)
+{
+       int32_t ret_val;
+       uint16_t i;
+       uint16_t phy_data;
+       
+       DEBUGFUNC("e1000_wait_autoneg");
+       DEBUGOUT("Waiting for Auto-Neg to complete.\n");
+       
+       /* We will wait for autoneg to complete or 4.5 seconds to expire. */
+       for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
+               /* Read the MII Status Register and wait for Auto-Neg
+                * Complete bit to be set.
+                */
+               if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
+                       return ret_val;
+               if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
+                       return ret_val;
+               if(phy_data & MII_SR_AUTONEG_COMPLETE) {
+                       DEBUGOUT("Auto-Neg complete.\n");
+                       return E1000_SUCCESS;
+               }
+               mdelay(100);
+       }
+       DEBUGOUT("Auto-Neg timedout.\n");
+       return -E1000_ERR_TIMEOUT;
+}
+
+/******************************************************************************
+* Raises the Management Data Clock
+*
+* hw - Struct containing variables accessed by shared code
+* ctrl - Device control register's current value
+******************************************************************************/
+static void
+e1000_raise_mdi_clk(struct e1000_hw *hw,
+                    uint32_t *ctrl)
+{
+       /* Raise the clock input to the Management Data Clock (by setting the MDC
+        * bit), and then delay 10 microseconds.
+        */
+       E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
+       E1000_WRITE_FLUSH(hw);
+       udelay(10);
+}
+
+/******************************************************************************
+* Lowers the Management Data Clock
+*
+* hw - Struct containing variables accessed by shared code
+* ctrl - Device control register's current value
+******************************************************************************/
+static void
+e1000_lower_mdi_clk(struct e1000_hw *hw,
+                    uint32_t *ctrl)
+{
+       /* Lower the clock input to the Management Data Clock (by clearing the MDC
+        * bit), and then delay 10 microseconds.
+        */
+       E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
+       E1000_WRITE_FLUSH(hw);
+       udelay(10);
+}
+
+/******************************************************************************
+* Shifts data bits out to the PHY
+*
+* hw - Struct containing variables accessed by shared code
+* data - Data to send out to the PHY
+* count - Number of bits to shift out
+*
+* Bits are shifted out in MSB to LSB order.
+******************************************************************************/
+static void
+e1000_shift_out_mdi_bits(struct e1000_hw *hw,
+                         uint32_t data,
+                         uint16_t count)
+{
+       uint32_t ctrl;
+       uint32_t mask;
+
+       /* We need to shift "count" number of bits out to the PHY. So, the value
+        * in the "data" parameter will be shifted out to the PHY one bit at a 
+        * time. In order to do this, "data" must be broken down into bits.
+        */
+       mask = 0x01;
+       mask <<= (count - 1);
+       
+       ctrl = E1000_READ_REG(hw, CTRL);
+       
+       /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
+       ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
+       
+       while(mask) {
+               /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
+                * then raising and lowering the Management Data Clock. A "0" is
+                * shifted out to the PHY by setting the MDIO bit to "0" and then
+                * raising and lowering the clock.
+                */
+               if(data & mask) ctrl |= E1000_CTRL_MDIO;
+               else ctrl &= ~E1000_CTRL_MDIO;
+               
+               E1000_WRITE_REG(hw, CTRL, ctrl);
+               E1000_WRITE_FLUSH(hw);
+               
+               udelay(10);
+
+               e1000_raise_mdi_clk(hw, &ctrl);
+               e1000_lower_mdi_clk(hw, &ctrl);
+
+               mask = mask >> 1;
+       }
+}
+
+/******************************************************************************
+* Shifts data bits in from the PHY
+*
+* hw - Struct containing variables accessed by shared code
+*
+* Bits are shifted in in MSB to LSB order. 
+******************************************************************************/
+static uint16_t
+e1000_shift_in_mdi_bits(struct e1000_hw *hw)
+{
+       uint32_t ctrl;
+       uint16_t data = 0;
+       uint8_t i;
+
+       /* In order to read a register from the PHY, we need to shift in a total
+        * of 18 bits from the PHY. The first two bit (turnaround) times are used
+        * to avoid contention on the MDIO pin when a read operation is performed.
+        * These two bits are ignored by us and thrown away. Bits are "shifted in"
+        * by raising the input to the Management Data Clock (setting the MDC bit),
+        * and then reading the value of the MDIO bit.
+        */ 
+       ctrl = E1000_READ_REG(hw, CTRL);
+       
+       /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
+       ctrl &= ~E1000_CTRL_MDIO_DIR;
+       ctrl &= ~E1000_CTRL_MDIO;
+       
+       E1000_WRITE_REG(hw, CTRL, ctrl);
+       E1000_WRITE_FLUSH(hw);
+       
+       /* Raise and Lower the clock before reading in the data. This accounts for
+        * the turnaround bits. The first clock occurred when we clocked out the
+        * last bit of the Register Address.
+        */
+       e1000_raise_mdi_clk(hw, &ctrl);
+       e1000_lower_mdi_clk(hw, &ctrl);
+       
+       for(data = 0, i = 0; i < 16; i++) {
+               data = data << 1;
+               e1000_raise_mdi_clk(hw, &ctrl);
+               ctrl = E1000_READ_REG(hw, CTRL);
+               /* Check to see if we shifted in a "1". */
+               if(ctrl & E1000_CTRL_MDIO) data |= 1;
+               e1000_lower_mdi_clk(hw, &ctrl);
+       }
+       
+       e1000_raise_mdi_clk(hw, &ctrl);
+       e1000_lower_mdi_clk(hw, &ctrl);
+       
+       return data;
+}
+
+/*****************************************************************************
+* Reads the value from a PHY register, if the value is on a specific non zero
+* page, sets the page first.
+*
+* hw - Struct containing variables accessed by shared code
+* reg_addr - address of the PHY register to read
+******************************************************************************/
+static int
+e1000_read_phy_reg(struct e1000_hw *hw,
+                   uint32_t reg_addr,
+                   uint16_t *phy_data)
+{
+       uint32_t ret_val;
+
+       DEBUGFUNC("e1000_read_phy_reg");
+
+       if(hw->phy_type == e1000_phy_igp &&
+          (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
+               if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
+                                                    (uint16_t)reg_addr)))
+                       return ret_val;
+       }
+
+       ret_val = e1000_read_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
+                                       phy_data);
+
+       return ret_val;
+}
+
+static int
+e1000_read_phy_reg_ex(struct e1000_hw *hw,
+                      uint32_t reg_addr,
+                      uint16_t *phy_data)
+{
+       uint32_t i;
+       uint32_t mdic = 0;
+       const uint32_t phy_addr = 1;
+
+       DEBUGFUNC("e1000_read_phy_reg_ex");
+       
+       if(reg_addr > MAX_PHY_REG_ADDRESS) {
+               DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
+               return -E1000_ERR_PARAM;
+       }
+       
+       if(hw->mac_type > e1000_82543) {
+               /* Set up Op-code, Phy Address, and register address in the MDI
+                * Control register.  The MAC will take care of interfacing with the
+                * PHY to retrieve the desired data.
+                */
+               mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
+                       (phy_addr << E1000_MDIC_PHY_SHIFT) | 
+                       (E1000_MDIC_OP_READ));
+               
+               E1000_WRITE_REG(hw, MDIC, mdic);
+
+               /* Poll the ready bit to see if the MDI read completed */
+               for(i = 0; i < 64; i++) {
+                       udelay(50);
+                       mdic = E1000_READ_REG(hw, MDIC);
+                       if(mdic & E1000_MDIC_READY) break;
+               }
+               if(!(mdic & E1000_MDIC_READY)) {
+                       DEBUGOUT("MDI Read did not complete\n");
+                       return -E1000_ERR_PHY;
+               }
+               if(mdic & E1000_MDIC_ERROR) {
+                       DEBUGOUT("MDI Error\n");
+                       return -E1000_ERR_PHY;
+               }
+               *phy_data = (uint16_t) mdic;
+       } else {
+               /* We must first send a preamble through the MDIO pin to signal the
+                * beginning of an MII instruction.  This is done by sending 32
+                * consecutive "1" bits.
+                */
+               e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
+               
+               /* Now combine the next few fields that are required for a read
+                * operation.  We use this method instead of calling the
+                * e1000_shift_out_mdi_bits routine five different times. The format of
+                * a MII read instruction consists of a shift out of 14 bits and is
+                * defined as follows:
+                *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
+                * followed by a shift in of 18 bits.  This first two bits shifted in
+                * are TurnAround bits used to avoid contention on the MDIO pin when a
+                * READ operation is performed.  These two bits are thrown away
+                * followed by a shift in of 16 bits which contains the desired data.
+                */
+               mdic = ((reg_addr) | (phy_addr << 5) | 
+                       (PHY_OP_READ << 10) | (PHY_SOF << 12));
+               
+               e1000_shift_out_mdi_bits(hw, mdic, 14);
+               
+               /* Now that we've shifted out the read command to the MII, we need to
+                * "shift in" the 16-bit value (18 total bits) of the requested PHY
+                * register address.
+                */
+               *phy_data = e1000_shift_in_mdi_bits(hw);
+       }
+       return E1000_SUCCESS;
+}
+
+/******************************************************************************
+* Writes a value to a PHY register
+*
+* hw - Struct containing variables accessed by shared code
+* reg_addr - address of the PHY register to write
+* data - data to write to the PHY
+******************************************************************************/
+static int 
+e1000_write_phy_reg(struct e1000_hw *hw,
+                    uint32_t reg_addr,
+                    uint16_t phy_data)
+{
+       uint32_t ret_val;
+
+       DEBUGFUNC("e1000_write_phy_reg");
+
+       if(hw->phy_type == e1000_phy_igp &&
+          (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
+               if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
+                                                    (uint16_t)reg_addr)))
+                       return ret_val;
+       }
+
+       ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
+                                        phy_data);
+
+       return ret_val;
+}
+
+static int
+e1000_write_phy_reg_ex(struct e1000_hw *hw,
+                       uint32_t reg_addr,
+                       uint16_t phy_data)
+{
+       uint32_t i;
+       uint32_t mdic = 0;
+       const uint32_t phy_addr = 1;
+       
+       DEBUGFUNC("e1000_write_phy_reg_ex");
+       
+       if(reg_addr > MAX_PHY_REG_ADDRESS) {
+               DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
+               return -E1000_ERR_PARAM;
+       }
+       
+       if(hw->mac_type > e1000_82543) {
+               /* Set up Op-code, Phy Address, register address, and data intended
+                * for the PHY register in the MDI Control register.  The MAC will take
+                * care of interfacing with the PHY to send the desired data.
+                */
+               mdic = (((uint32_t) phy_data) |
+                       (reg_addr << E1000_MDIC_REG_SHIFT) |
+                       (phy_addr << E1000_MDIC_PHY_SHIFT) | 
+                       (E1000_MDIC_OP_WRITE));
+               
+               E1000_WRITE_REG(hw, MDIC, mdic);
+               
+               /* Poll the ready bit to see if the MDI read completed */
+               for(i = 0; i < 640; i++) {
+                       udelay(5);
+                       mdic = E1000_READ_REG(hw, MDIC);
+                       if(mdic & E1000_MDIC_READY) break;
+               }
+               if(!(mdic & E1000_MDIC_READY)) {
+                       DEBUGOUT("MDI Write did not complete\n");
+                       return -E1000_ERR_PHY;
+               }
+       } else {
+               /* We'll need to use the SW defined pins to shift the write command
+                * out to the PHY. We first send a preamble to the PHY to signal the
+                * beginning of the MII instruction.  This is done by sending 32 
+                * consecutive "1" bits.
+                */
+               e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
+               
+               /* Now combine the remaining required fields that will indicate a 
+                * write operation. We use this method instead of calling the
+                * e1000_shift_out_mdi_bits routine for each field in the command. The
+                * format of a MII write instruction is as follows:
+                * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
+                */
+               mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
+                       (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
+               mdic <<= 16;
+               mdic |= (uint32_t) phy_data;
+               
+               e1000_shift_out_mdi_bits(hw, mdic, 32);
+       }
+
+       return E1000_SUCCESS;
+}
+
+/******************************************************************************
+* Returns the PHY to the power-on reset state
+*
+* hw - Struct containing variables accessed by shared code
+******************************************************************************/
+static void
+e1000_phy_hw_reset(struct e1000_hw *hw)
+{
+       uint32_t ctrl, ctrl_ext;
+
+       DEBUGFUNC("e1000_phy_hw_reset");
+       
+       DEBUGOUT("Resetting Phy...\n");
+       
+       if(hw->mac_type > e1000_82543) {
+               /* Read the device control register and assert the E1000_CTRL_PHY_RST
+                * bit. Then, take it out of reset.
+                */
+               ctrl = E1000_READ_REG(hw, CTRL);
+               E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
+               E1000_WRITE_FLUSH(hw);
+               mdelay(10);
+               E1000_WRITE_REG(hw, CTRL, ctrl);
+               E1000_WRITE_FLUSH(hw);
+       } else {
+               /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
+                * bit to put the PHY into reset. Then, take it out of reset.
+                */
+               ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
+               ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
+               ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
+               E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
+               E1000_WRITE_FLUSH(hw);
+               mdelay(10);
+               ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
+               E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
+               E1000_WRITE_FLUSH(hw);
+       }
+       udelay(150);
+}
+
+/******************************************************************************
+* Resets the PHY
+*
+* hw - Struct containing variables accessed by shared code
+*
+* Sets bit 15 of the MII Control regiser
+******************************************************************************/
+static int 
+e1000_phy_reset(struct e1000_hw *hw)
+{
+       int32_t ret_val;
+       uint16_t phy_data;
+
+       DEBUGFUNC("e1000_phy_reset");
+
+       if(hw->mac_type != e1000_82541_rev_2) {
+               if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
+                       return ret_val;
+               
+               phy_data |= MII_CR_RESET;
+               if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
+                       return ret_val;
+               
+               udelay(1);
+       } else e1000_phy_hw_reset(hw);
+
+       if(hw->phy_type == e1000_phy_igp)
+               e1000_phy_init_script(hw);
+
+       return E1000_SUCCESS;
+}
+
+/******************************************************************************
+* Probes the expected PHY address for known PHY IDs
+*
+* hw - Struct containing variables accessed by shared code
+******************************************************************************/
+static int
+e1000_detect_gig_phy(struct e1000_hw *hw)
+{
+       int32_t phy_init_status, ret_val;
+       uint16_t phy_id_high, phy_id_low;
+       boolean_t match = FALSE;
+
+       DEBUGFUNC("e1000_detect_gig_phy");
+       
+       /* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work-
+        * around that forces PHY page 0 to be set or the reads fail.  The rest of
+        * the code in this routine uses e1000_read_phy_reg to read the PHY ID.
+        * So for ESB-2 we need to have this set so our reads won't fail.  If the
+        * attached PHY is not a e1000_phy_gg82563, the routines below will figure
+        * this out as well. */
+       if (hw->mac_type == e1000_80003es2lan)
+               hw->phy_type = e1000_phy_gg82563;
+       
+       /* Read the PHY ID Registers to identify which PHY is onboard. */
+       if((ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high)))
+               return ret_val;
+
+       hw->phy_id = (uint32_t) (phy_id_high << 16);
+       udelay(20);
+       if((ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low)))
+               return ret_val;
+       
+       hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
+#ifdef LINUX_DRIVER
+       hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
+#endif
+       
+       switch(hw->mac_type) {
+       case e1000_82543:
+               if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
+               break;
+       case e1000_82544:
+               if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
+               break;
+       case e1000_82540:
+       case e1000_82545:
+       case e1000_82545_rev_3:
+       case e1000_82546:
+       case e1000_82546_rev_3:
+               if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
+               break;
+       case e1000_82541:
+       case e1000_82541_rev_2:
+       case e1000_82547:
+       case e1000_82547_rev_2:
+               if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
+               break;
+       case e1000_80003es2lan:
+               if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
+               break;
+       default:
+               DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
+               return -E1000_ERR_CONFIG;
+       }
+       phy_init_status = e1000_set_phy_type(hw);
+
+       if ((match) && (phy_init_status == E1000_SUCCESS)) {
+               DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
+               return E1000_SUCCESS;
+       }
+       DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
+       return -E1000_ERR_PHY;
+}
+
+/******************************************************************************
+ * Sets up eeprom variables in the hw struct.  Must be called after mac_type
+ * is configured.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static void
+e1000_init_eeprom_params(struct e1000_hw *hw)
+{
+       struct e1000_eeprom_info *eeprom = &hw->eeprom;
+       uint32_t eecd = E1000_READ_REG(hw, EECD);
+       uint16_t eeprom_size;
+
+       DEBUGFUNC("e1000_init_eeprom_params");
+
+       switch (hw->mac_type) {
+       case e1000_82542_rev2_0:
+       case e1000_82542_rev2_1:
+       case e1000_82543:
+       case e1000_82544:
+               eeprom->type = e1000_eeprom_microwire;
+               eeprom->word_size = 64;
+               eeprom->opcode_bits = 3;
+               eeprom->address_bits = 6;
+               eeprom->delay_usec = 50;
+               break;
+       case e1000_82540:
+       case e1000_82545:
+       case e1000_82545_rev_3:
+       case e1000_82546:
+       case e1000_82546_rev_3:
+               eeprom->type = e1000_eeprom_microwire;
+               eeprom->opcode_bits = 3;
+               eeprom->delay_usec = 50;
+               if(eecd & E1000_EECD_SIZE) {
+                       eeprom->word_size = 256;
+                       eeprom->address_bits = 8;
+               } else {
+                       eeprom->word_size = 64;
+                       eeprom->address_bits = 6;
+               }
+               break;
+       case e1000_82541:
+       case e1000_82541_rev_2:
+       case e1000_82547:
+       case e1000_82547_rev_2:
+               if (eecd & E1000_EECD_TYPE) {
+                       eeprom->type = e1000_eeprom_spi;
+                       if (eecd & E1000_EECD_ADDR_BITS) {
+                               eeprom->page_size = 32;
+                               eeprom->address_bits = 16;
+                       } else {
+                               eeprom->page_size = 8;
+                               eeprom->address_bits = 8;
+                       }
+               } else {
+                       eeprom->type = e1000_eeprom_microwire;
+                       eeprom->opcode_bits = 3;
+                       eeprom->delay_usec = 50;
+                       if (eecd & E1000_EECD_ADDR_BITS) {
+                               eeprom->word_size = 256;
+                               eeprom->address_bits = 8;
+                       } else {
+                               eeprom->word_size = 64;
+                               eeprom->address_bits = 6;
+                       }
+               }
+               break;
+       default:
+               eeprom->type = e1000_eeprom_spi;
+               if (eecd & E1000_EECD_ADDR_BITS) {
+                       eeprom->page_size = 32;
+                       eeprom->address_bits = 16;
                } else {
-                       *duplex = HALF_DUPLEX;
-                       DEBUGOUT(" Half Duplex\r\n");
+                       eeprom->page_size = 8;
+                       eeprom->address_bits = 8;
                }
-       } else {
-               DEBUGOUT("1000 Mbs, Full Duplex\r\n");
-               *speed = SPEED_1000;
-               *duplex = FULL_DUPLEX;
+               break;
        }
-}
 
-/******************************************************************************
-* Blocks until autoneg completes or times out (~4.5 seconds)
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-static int
-e1000_wait_autoneg(struct e1000_hw *hw)
-{
-       int32_t ret_val;
-       uint16_t i;
-       uint16_t phy_data;
-       
-       DEBUGFUNC("e1000_wait_autoneg");
-       DEBUGOUT("Waiting for Auto-Neg to complete.\n");
-       
-       /* We will wait for autoneg to complete or 4.5 seconds to expire. */
-       for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
-               /* Read the MII Status Register and wait for Auto-Neg
-                * Complete bit to be set.
-                */
-               if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
-                       return ret_val;
-               if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
-                       return ret_val;
-               if(phy_data & MII_SR_AUTONEG_COMPLETE) {
-                       DEBUGOUT("Auto-Neg complete.\n");
-                       return E1000_SUCCESS;
+       if (eeprom->type == e1000_eeprom_spi) {
+               eeprom->opcode_bits = 8;
+               eeprom->delay_usec = 1;
+               eeprom->word_size = 64;
+               if (e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) {
+                       eeprom_size &= EEPROM_SIZE_MASK;
+
+                       switch (eeprom_size) {
+                       case EEPROM_SIZE_16KB:
+                               eeprom->word_size = 8192;
+                               break;
+                       case EEPROM_SIZE_8KB:
+                               eeprom->word_size = 4096;
+                               break;
+                       case EEPROM_SIZE_4KB:
+                               eeprom->word_size = 2048;
+                               break;
+                       case EEPROM_SIZE_2KB:
+                               eeprom->word_size = 1024;
+                               break;
+                       case EEPROM_SIZE_1KB:
+                               eeprom->word_size = 512;
+                               break;
+                       case EEPROM_SIZE_512B:
+                               eeprom->word_size = 256;
+                               break;
+                       case EEPROM_SIZE_128B:
+                       default:
+                               break;
+                       }
                }
-               mdelay(100);
        }
-       DEBUGOUT("Auto-Neg timedout.\n");
-       return -E1000_ERR_TIMEOUT;
 }
 
 /******************************************************************************
-* Raises the Management Data Clock
-*
-* hw - Struct containing variables accessed by shared code
-* ctrl - Device control register's current value
-******************************************************************************/
+ * Raises the EEPROM's clock input.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * eecd - EECD's current value
+ *****************************************************************************/
 static void
-e1000_raise_mdi_clk(struct e1000_hw *hw,
-                    uint32_t *ctrl)
+e1000_raise_ee_clk(struct e1000_hw *hw,
+                   uint32_t *eecd)
 {
-       /* Raise the clock input to the Management Data Clock (by setting the MDC
-        * bit), and then delay 10 microseconds.
+       /* Raise the clock input to the EEPROM (by setting the SK bit), and then
+        * wait <delay> microseconds.
         */
-       E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
+       *eecd = *eecd | E1000_EECD_SK;
+       E1000_WRITE_REG(hw, EECD, *eecd);
        E1000_WRITE_FLUSH(hw);
-       udelay(10);
+       udelay(hw->eeprom.delay_usec);
 }
 
 /******************************************************************************
-* Lowers the Management Data Clock
-*
-* hw - Struct containing variables accessed by shared code
-* ctrl - Device control register's current value
-******************************************************************************/
+ * Lowers the EEPROM's clock input.
+ *
+ * hw - Struct containing variables accessed by shared code 
+ * eecd - EECD's current value
+ *****************************************************************************/
 static void
-e1000_lower_mdi_clk(struct e1000_hw *hw,
-                    uint32_t *ctrl)
+e1000_lower_ee_clk(struct e1000_hw *hw,
+                   uint32_t *eecd)
 {
-       /* Lower the clock input to the Management Data Clock (by clearing the MDC
-        * bit), and then delay 10 microseconds.
+       /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 
+        * wait 50 microseconds. 
         */
-       E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
+       *eecd = *eecd & ~E1000_EECD_SK;
+       E1000_WRITE_REG(hw, EECD, *eecd);
        E1000_WRITE_FLUSH(hw);
-       udelay(10);
+       udelay(hw->eeprom.delay_usec);
 }
 
 /******************************************************************************
-* Shifts data bits out to the PHY
-*
-* hw - Struct containing variables accessed by shared code
-* data - Data to send out to the PHY
-* count - Number of bits to shift out
-*
-* Bits are shifted out in MSB to LSB order.
-******************************************************************************/
+ * Shift data bits out to the EEPROM.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * data - data to send to the EEPROM
+ * count - number of bits to shift out
+ *****************************************************************************/
 static void
-e1000_shift_out_mdi_bits(struct e1000_hw *hw,
-                         uint32_t data,
-                         uint16_t count)
+e1000_shift_out_ee_bits(struct e1000_hw *hw,
+                        uint16_t data,
+                        uint16_t count)
 {
-       uint32_t ctrl;
+       struct e1000_eeprom_info *eeprom = &hw->eeprom;
+       uint32_t eecd;
        uint32_t mask;
-
-       /* We need to shift "count" number of bits out to the PHY. So, the value
-        * in the "data" parameter will be shifted out to the PHY one bit at a 
-        * time. In order to do this, "data" must be broken down into bits.
-        */
-       mask = 0x01;
-       mask <<= (count - 1);
-       
-       ctrl = E1000_READ_REG(hw, CTRL);
-       
-       /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
-       ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
        
-       while(mask) {
-               /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
-                * then raising and lowering the Management Data Clock. A "0" is
-                * shifted out to the PHY by setting the MDIO bit to "0" and then
-                * raising and lowering the clock.
+       /* We need to shift "count" bits out to the EEPROM. So, value in the
+        * "data" parameter will be shifted out to the EEPROM one bit at a time.
+        * In order to do this, "data" must be broken down into bits. 
+        */
+       mask = 0x01 << (count - 1);
+       eecd = E1000_READ_REG(hw, EECD);
+       if (eeprom->type == e1000_eeprom_microwire) {
+               eecd &= ~E1000_EECD_DO;
+       } else if (eeprom->type == e1000_eeprom_spi) {
+               eecd |= E1000_EECD_DO;
+       }
+       do {
+               /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
+                * and then raising and then lowering the clock (the SK bit controls
+                * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
+                * by setting "DI" to "0" and then raising and then lowering the clock.
                 */
-               if(data & mask) ctrl |= E1000_CTRL_MDIO;
-               else ctrl &= ~E1000_CTRL_MDIO;
+               eecd &= ~E1000_EECD_DI;
                
-               E1000_WRITE_REG(hw, CTRL, ctrl);
+               if(data & mask)
+                       eecd |= E1000_EECD_DI;
+               
+               E1000_WRITE_REG(hw, EECD, eecd);
                E1000_WRITE_FLUSH(hw);
                
-               udelay(10);
-
-               e1000_raise_mdi_clk(hw, &ctrl);
-               e1000_lower_mdi_clk(hw, &ctrl);
-
+               udelay(eeprom->delay_usec);
+               
+               e1000_raise_ee_clk(hw, &eecd);
+               e1000_lower_ee_clk(hw, &eecd);
+               
                mask = mask >> 1;
-       }
+               
+       } while(mask);
+
+       /* We leave the "DI" bit set to "0" when we leave this routine. */
+       eecd &= ~E1000_EECD_DI;
+       E1000_WRITE_REG(hw, EECD, eecd);
 }
 
 /******************************************************************************
-* Shifts data bits in from the PHY
-*
-* hw - Struct containing variables accessed by shared code
-*
-* Bits are shifted in in MSB to LSB order. 
-******************************************************************************/
+ * Shift data bits in from the EEPROM
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
 static uint16_t
-e1000_shift_in_mdi_bits(struct e1000_hw *hw)
+e1000_shift_in_ee_bits(struct e1000_hw *hw,
+                       uint16_t count)
 {
-       uint32_t ctrl;
-       uint16_t data = 0;
-       uint8_t i;
-
-       /* In order to read a register from the PHY, we need to shift in a total
-        * of 18 bits from the PHY. The first two bit (turnaround) times are used
-        * to avoid contention on the MDIO pin when a read operation is performed.
-        * These two bits are ignored by us and thrown away. Bits are "shifted in"
-        * by raising the input to the Management Data Clock (setting the MDC bit),
-        * and then reading the value of the MDIO bit.
-        */ 
-       ctrl = E1000_READ_REG(hw, CTRL);
-       
-       /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
-       ctrl &= ~E1000_CTRL_MDIO_DIR;
-       ctrl &= ~E1000_CTRL_MDIO;
-       
-       E1000_WRITE_REG(hw, CTRL, ctrl);
-       E1000_WRITE_FLUSH(hw);
+       uint32_t eecd;
+       uint32_t i;
+       uint16_t data;
        
-       /* Raise and Lower the clock before reading in the data. This accounts for
-        * the turnaround bits. The first clock occurred when we clocked out the
-        * last bit of the Register Address.
+       /* In order to read a register from the EEPROM, we need to shift 'count' 
+        * bits in from the EEPROM. Bits are "shifted in" by raising the clock
+        * input to the EEPROM (setting the SK bit), and then reading the value of
+        * the "DO" bit.  During this "shifting in" process the "DI" bit should
+        * always be clear.
         */
-       e1000_raise_mdi_clk(hw, &ctrl);
-       e1000_lower_mdi_clk(hw, &ctrl);
        
-       for(data = 0, i = 0; i < 16; i++) {
+       eecd = E1000_READ_REG(hw, EECD);
+       
+       eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
+       data = 0;
+       
+       for(i = 0; i < count; i++) {
                data = data << 1;
-               e1000_raise_mdi_clk(hw, &ctrl);
-               ctrl = E1000_READ_REG(hw, CTRL);
-               /* Check to see if we shifted in a "1". */
-               if(ctrl & E1000_CTRL_MDIO) data |= 1;
-               e1000_lower_mdi_clk(hw, &ctrl);
+               e1000_raise_ee_clk(hw, &eecd);
+               
+               eecd = E1000_READ_REG(hw, EECD);
+               
+               eecd &= ~(E1000_EECD_DI);
+               if(eecd & E1000_EECD_DO)
+                       data |= 1;
+               
+               e1000_lower_ee_clk(hw, &eecd);
        }
        
-       e1000_raise_mdi_clk(hw, &ctrl);
-       e1000_lower_mdi_clk(hw, &ctrl);
-       
        return data;
 }
 
-/*****************************************************************************
-* Reads the value from a PHY register, if the value is on a specific non zero
-* page, sets the page first.
-*
-* hw - Struct containing variables accessed by shared code
-* reg_addr - address of the PHY register to read
-******************************************************************************/
-static int
-e1000_read_phy_reg(struct e1000_hw *hw,
-                   uint32_t reg_addr,
-                   uint16_t *phy_data)
+/******************************************************************************
+ * Prepares EEPROM for access
+ *
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 
+ * function should be called before issuing a command to the EEPROM.
+ *****************************************************************************/
+static int32_t
+e1000_acquire_eeprom(struct e1000_hw *hw)
 {
-       uint32_t ret_val;
+       struct e1000_eeprom_info *eeprom = &hw->eeprom;
+       uint32_t eecd, i=0;
 
-       DEBUGFUNC("e1000_read_phy_reg");
+       eecd = E1000_READ_REG(hw, EECD);
 
-       if(hw->phy_type == e1000_phy_igp &&
-          (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
-               if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
-                                                    (uint16_t)reg_addr)))
-                       return ret_val;
+       /* Request EEPROM Access */
+       if(hw->mac_type > e1000_82544) {
+               eecd |= E1000_EECD_REQ;
+               E1000_WRITE_REG(hw, EECD, eecd);
+               eecd = E1000_READ_REG(hw, EECD);
+               while((!(eecd & E1000_EECD_GNT)) &&
+                     (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
+                       i++;
+                       udelay(5);
+                       eecd = E1000_READ_REG(hw, EECD);
+               }
+               if(!(eecd & E1000_EECD_GNT)) {
+                       eecd &= ~E1000_EECD_REQ;
+                       E1000_WRITE_REG(hw, EECD, eecd);
+                       DEBUGOUT("Could not acquire EEPROM grant\n");
+                       return -E1000_ERR_EEPROM;
+               }
        }
 
-       ret_val = e1000_read_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
-                                       phy_data);
+       /* Setup EEPROM for Read/Write */
 
-       return ret_val;
+       if (eeprom->type == e1000_eeprom_microwire) {
+               /* Clear SK and DI */
+               eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
+               E1000_WRITE_REG(hw, EECD, eecd);
+
+               /* Set CS */
+               eecd |= E1000_EECD_CS;
+               E1000_WRITE_REG(hw, EECD, eecd);
+       } else if (eeprom->type == e1000_eeprom_spi) {
+               /* Clear SK and CS */
+               eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
+               E1000_WRITE_REG(hw, EECD, eecd);
+               udelay(1);
+       }
+
+       return E1000_SUCCESS;
 }
 
-static int
-e1000_read_phy_reg_ex(struct e1000_hw *hw,
-                      uint32_t reg_addr,
-                      uint16_t *phy_data)
+/******************************************************************************
+ * Returns EEPROM to a "standby" state
+ * 
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static void
+e1000_standby_eeprom(struct e1000_hw *hw)
 {
-       uint32_t i;
-       uint32_t mdic = 0;
-       const uint32_t phy_addr = 1;
+       struct e1000_eeprom_info *eeprom = &hw->eeprom;
+       uint32_t eecd;
+       
+       eecd = E1000_READ_REG(hw, EECD);
 
-       DEBUGFUNC("e1000_read_phy_reg_ex");
+       if(eeprom->type == e1000_eeprom_microwire) {
+
+               /* Deselect EEPROM */
+               eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
+               E1000_WRITE_REG(hw, EECD, eecd);
+               E1000_WRITE_FLUSH(hw);
+               udelay(eeprom->delay_usec);
        
-       if(reg_addr > MAX_PHY_REG_ADDRESS) {
-               DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
-               return -E1000_ERR_PARAM;
-       }
+               /* Clock high */
+               eecd |= E1000_EECD_SK;
+               E1000_WRITE_REG(hw, EECD, eecd);
+               E1000_WRITE_FLUSH(hw);
+               udelay(eeprom->delay_usec);
        
-       if(hw->mac_type > e1000_82543) {
-               /* Set up Op-code, Phy Address, and register address in the MDI
-                * Control register.  The MAC will take care of interfacing with the
-                * PHY to retrieve the desired data.
-                */
-               mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
-                       (phy_addr << E1000_MDIC_PHY_SHIFT) | 
-                       (E1000_MDIC_OP_READ));
-               
-               E1000_WRITE_REG(hw, MDIC, mdic);
+               /* Select EEPROM */
+               eecd |= E1000_EECD_CS;
+               E1000_WRITE_REG(hw, EECD, eecd);
+               E1000_WRITE_FLUSH(hw);
+               udelay(eeprom->delay_usec);
 
-               /* Poll the ready bit to see if the MDI read completed */
-               for(i = 0; i < 64; i++) {
-                       udelay(50);
-                       mdic = E1000_READ_REG(hw, MDIC);
-                       if(mdic & E1000_MDIC_READY) break;
-               }
-               if(!(mdic & E1000_MDIC_READY)) {
-                       DEBUGOUT("MDI Read did not complete\n");
-                       return -E1000_ERR_PHY;
-               }
-               if(mdic & E1000_MDIC_ERROR) {
-                       DEBUGOUT("MDI Error\n");
-                       return -E1000_ERR_PHY;
-               }
-               *phy_data = (uint16_t) mdic;
-       } else {
-               /* We must first send a preamble through the MDIO pin to signal the
-                * beginning of an MII instruction.  This is done by sending 32
-                * consecutive "1" bits.
-                */
-               e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
-               
-               /* Now combine the next few fields that are required for a read
-                * operation.  We use this method instead of calling the
-                * e1000_shift_out_mdi_bits routine five different times. The format of
-                * a MII read instruction consists of a shift out of 14 bits and is
-                * defined as follows:
-                *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
-                * followed by a shift in of 18 bits.  This first two bits shifted in
-                * are TurnAround bits used to avoid contention on the MDIO pin when a
-                * READ operation is performed.  These two bits are thrown away
-                * followed by a shift in of 16 bits which contains the desired data.
-                */
-               mdic = ((reg_addr) | (phy_addr << 5) | 
-                       (PHY_OP_READ << 10) | (PHY_SOF << 12));
-               
-               e1000_shift_out_mdi_bits(hw, mdic, 14);
-               
-               /* Now that we've shifted out the read command to the MII, we need to
-                * "shift in" the 16-bit value (18 total bits) of the requested PHY
-                * register address.
-                */
-               *phy_data = e1000_shift_in_mdi_bits(hw);
+               /* Clock low */
+               eecd &= ~E1000_EECD_SK;
+               E1000_WRITE_REG(hw, EECD, eecd);
+               E1000_WRITE_FLUSH(hw);
+               udelay(eeprom->delay_usec);
+       } else if(eeprom->type == e1000_eeprom_spi) {
+               /* Toggle CS to flush commands */
+               eecd |= E1000_EECD_CS;
+               E1000_WRITE_REG(hw, EECD, eecd);
+               E1000_WRITE_FLUSH(hw);
+               udelay(eeprom->delay_usec);
+               eecd &= ~E1000_EECD_CS;
+               E1000_WRITE_REG(hw, EECD, eecd);
+               E1000_WRITE_FLUSH(hw);
+               udelay(eeprom->delay_usec);
        }
-       return E1000_SUCCESS;
 }
 
 /******************************************************************************
-* Writes a value to a PHY register
-*
-* hw - Struct containing variables accessed by shared code
-* reg_addr - address of the PHY register to write
-* data - data to write to the PHY
-******************************************************************************/
-static int 
-e1000_write_phy_reg(struct e1000_hw *hw,
-                    uint32_t reg_addr,
-                    uint16_t phy_data)
+ * Terminates a command by inverting the EEPROM's chip select pin
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static void
+e1000_release_eeprom(struct e1000_hw *hw)
+{
+       uint32_t eecd;
+
+       eecd = E1000_READ_REG(hw, EECD);
+
+       if (hw->eeprom.type == e1000_eeprom_spi) {
+               eecd |= E1000_EECD_CS;  /* Pull CS high */
+               eecd &= ~E1000_EECD_SK; /* Lower SCK */
+
+               E1000_WRITE_REG(hw, EECD, eecd);
+
+               udelay(hw->eeprom.delay_usec);
+       } else if(hw->eeprom.type == e1000_eeprom_microwire) {
+               /* cleanup eeprom */
+
+               /* CS on Microwire is active-high */
+               eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
+
+               E1000_WRITE_REG(hw, EECD, eecd);
+
+               /* Rising edge of clock */
+               eecd |= E1000_EECD_SK;
+               E1000_WRITE_REG(hw, EECD, eecd);
+               E1000_WRITE_FLUSH(hw);
+               udelay(hw->eeprom.delay_usec);
+
+               /* Falling edge of clock */
+               eecd &= ~E1000_EECD_SK;
+               E1000_WRITE_REG(hw, EECD, eecd);
+               E1000_WRITE_FLUSH(hw);
+               udelay(hw->eeprom.delay_usec);
+       }
+
+       /* Stop requesting EEPROM access */
+       if(hw->mac_type > e1000_82544) {
+               eecd &= ~E1000_EECD_REQ;
+               E1000_WRITE_REG(hw, EECD, eecd);
+       }
+}
+
+/******************************************************************************
+ * Reads a 16 bit word from the EEPROM.
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static int32_t
+e1000_spi_eeprom_ready(struct e1000_hw *hw)
 {
-       uint32_t ret_val;
+       uint16_t retry_count = 0;
+       uint8_t spi_stat_reg;
 
-       DEBUGFUNC("e1000_write_phy_reg");
+       /* Read "Status Register" repeatedly until the LSB is cleared.  The
+        * EEPROM will signal that the command has been completed by clearing
+        * bit 0 of the internal status register.  If it's not cleared within
+        * 5 milliseconds, then error out.
+        */
+       retry_count = 0;
+       do {
+               e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
+               hw->eeprom.opcode_bits);
+               spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
+               if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
+                       break;
 
-       if(hw->phy_type == e1000_phy_igp &&
-          (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
-               if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
-                                                    (uint16_t)reg_addr)))
-                       return ret_val;
-       }
+               udelay(5);
+               retry_count += 5;
 
-       ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
-                                        phy_data);
+       } while(retry_count < EEPROM_MAX_RETRY_SPI);
 
-       return ret_val;
+       /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
+        * only 0-5mSec on 5V devices)
+        */
+       if(retry_count >= EEPROM_MAX_RETRY_SPI) {
+               DEBUGOUT("SPI EEPROM Status error\n");
+               return -E1000_ERR_EEPROM;
+       }
+
+       return E1000_SUCCESS;
 }
 
+/******************************************************************************
+ * Reads a 16 bit word from the EEPROM.
+ *
+ * hw - Struct containing variables accessed by shared code
+ * offset - offset of  word in the EEPROM to read
+ * data - word read from the EEPROM
+ * words - number of words to read
+ *****************************************************************************/
 static int
-e1000_write_phy_reg_ex(struct e1000_hw *hw,
-                       uint32_t reg_addr,
-                       uint16_t phy_data)
+e1000_read_eeprom(struct e1000_hw *hw,
+                  uint16_t offset,
+                 uint16_t words,
+                  uint16_t *data)
 {
-       uint32_t i;
-       uint32_t mdic = 0;
-       const uint32_t phy_addr = 1;
-       
-       DEBUGFUNC("e1000_write_phy_reg_ex");
+       struct e1000_eeprom_info *eeprom = &hw->eeprom;
+       uint32_t i = 0;
        
-       if(reg_addr > MAX_PHY_REG_ADDRESS) {
-               DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
-               return -E1000_ERR_PARAM;
+       DEBUGFUNC("e1000_read_eeprom");
+
+       /* A check for invalid values:  offset too large, too many words, and not
+        * enough words.
+        */
+       if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
+          (words == 0)) {
+               DEBUGOUT("\"words\" parameter out of bounds\n");
+               return -E1000_ERR_EEPROM;
        }
-       
-       if(hw->mac_type > e1000_82543) {
-               /* Set up Op-code, Phy Address, register address, and data intended
-                * for the PHY register in the MDI Control register.  The MAC will take
-                * care of interfacing with the PHY to send the desired data.
-                */
-               mdic = (((uint32_t) phy_data) |
-                       (reg_addr << E1000_MDIC_REG_SHIFT) |
-                       (phy_addr << E1000_MDIC_PHY_SHIFT) | 
-                       (E1000_MDIC_OP_WRITE));
-               
-               E1000_WRITE_REG(hw, MDIC, mdic);
-               
-               /* Poll the ready bit to see if the MDI read completed */
-               for(i = 0; i < 640; i++) {
-                       udelay(5);
-                       mdic = E1000_READ_REG(hw, MDIC);
-                       if(mdic & E1000_MDIC_READY) break;
+
+       /*  Prepare the EEPROM for reading  */
+       if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
+               return -E1000_ERR_EEPROM;
+
+       if(eeprom->type == e1000_eeprom_spi) {
+               uint16_t word_in;
+               uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
+
+               if(e1000_spi_eeprom_ready(hw)) {
+                       e1000_release_eeprom(hw);
+                       return -E1000_ERR_EEPROM;
                }
-               if(!(mdic & E1000_MDIC_READY)) {
-                       DEBUGOUT("MDI Write did not complete\n");
-                       return -E1000_ERR_PHY;
+
+               e1000_standby_eeprom(hw);
+
+               /* Some SPI eeproms use the 8th address bit embedded in the opcode */
+               if((eeprom->address_bits == 8) && (offset >= 128))
+                       read_opcode |= EEPROM_A8_OPCODE_SPI;
+
+               /* Send the READ command (opcode + addr)  */
+               e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
+               e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
+
+               /* Read the data.  The address of the eeprom internally increments with
+                * each byte (spi) being read, saving on the overhead of eeprom setup
+                * and tear-down.  The address counter will roll over if reading beyond
+                * the size of the eeprom, thus allowing the entire memory to be read
+                * starting from any offset. */
+               for (i = 0; i < words; i++) {
+                       word_in = e1000_shift_in_ee_bits(hw, 16);
+                       data[i] = (word_in >> 8) | (word_in << 8);
+               }
+       } else if(eeprom->type == e1000_eeprom_microwire) {
+               for (i = 0; i < words; i++) {
+                       /*  Send the READ command (opcode + addr)  */
+                       e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
+                                               eeprom->opcode_bits);
+                       e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
+                                               eeprom->address_bits);
+
+                       /* Read the data.  For microwire, each word requires the overhead
+                        * of eeprom setup and tear-down. */
+                       data[i] = e1000_shift_in_ee_bits(hw, 16);
+                       e1000_standby_eeprom(hw);
                }
-       } else {
-               /* We'll need to use the SW defined pins to shift the write command
-                * out to the PHY. We first send a preamble to the PHY to signal the
-                * beginning of the MII instruction.  This is done by sending 32 
-                * consecutive "1" bits.
-                */
-               e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
-               
-               /* Now combine the remaining required fields that will indicate a 
-                * write operation. We use this method instead of calling the
-                * e1000_shift_out_mdi_bits routine for each field in the command. The
-                * format of a MII write instruction is as follows:
-                * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
-                */
-               mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
-                       (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
-               mdic <<= 16;
-               mdic |= (uint32_t) phy_data;
-               
-               e1000_shift_out_mdi_bits(hw, mdic, 32);
        }
 
+       /* End this read operation */
+       e1000_release_eeprom(hw);
+
        return E1000_SUCCESS;
 }
 
 /******************************************************************************
-* Returns the PHY to the power-on reset state
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-static void
-e1000_phy_hw_reset(struct e1000_hw *hw)
+ * Verifies that the EEPROM has a valid checksum
+ * 
+ * hw - Struct containing variables accessed by shared code
+ *
+ * Reads the first 64 16 bit words of the EEPROM and sums the values read.
+ * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
+ * valid.
+ *****************************************************************************/
+static int
+e1000_validate_eeprom_checksum(struct e1000_hw *hw)
 {
-       uint32_t ctrl, ctrl_ext;
+       uint16_t checksum = 0;
+       uint16_t i, eeprom_data;
 
-       DEBUGFUNC("e1000_phy_hw_reset");
-       
-       DEBUGOUT("Resetting Phy...\n");
+       DEBUGFUNC("e1000_validate_eeprom_checksum");
+
+       for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
+               if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
+                       DEBUGOUT("EEPROM Read Error\n");
+                       return -E1000_ERR_EEPROM;
+               }
+               checksum += eeprom_data;
+       }
        
-       if(hw->mac_type > e1000_82543) {
-               /* Read the device control register and assert the E1000_CTRL_PHY_RST
-                * bit. Then, take it out of reset.
-                */
-               ctrl = E1000_READ_REG(hw, CTRL);
-               E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
-               E1000_WRITE_FLUSH(hw);
-               mdelay(10);
-               E1000_WRITE_REG(hw, CTRL, ctrl);
-               E1000_WRITE_FLUSH(hw);
-       } else {
-               /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
-                * bit to put the PHY into reset. Then, take it out of reset.
-                */
-               ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
-               ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
-               ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
-               E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
-               E1000_WRITE_FLUSH(hw);
-               mdelay(10);
-               ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
-               E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
-               E1000_WRITE_FLUSH(hw);
+       if(checksum == (uint16_t) EEPROM_SUM)
+               return E1000_SUCCESS;
+       else {
+               DEBUGOUT("EEPROM Checksum Invalid\n");    
+               return -E1000_ERR_EEPROM;
        }
-       udelay(150);
 }
 
-/******************************************************************************
-* Resets the PHY
-*
-* hw - Struct containing variables accessed by shared code
-*
-* Sets bit 15 of the MII Control regiser
-******************************************************************************/
-static int 
-e1000_phy_reset(struct e1000_hw *hw)
-{
-       int32_t ret_val;
-       uint16_t phy_data;
-
-       DEBUGFUNC("e1000_phy_reset");
-
-       if(hw->mac_type != e1000_82541_rev_2) {
-               if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
-                       return ret_val;
-               
-               phy_data |= MII_CR_RESET;
-               if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
-                       return ret_val;
-               
-               udelay(1);
-       } else e1000_phy_hw_reset(hw);
+/******************************************************************************
+ * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
+ * second function of dual function devices
+ *
+ * hw - Struct containing variables accessed by shared code
+ *****************************************************************************/
+static int 
+e1000_read_mac_addr(struct e1000_hw *hw)
+{
+       uint16_t offset;
+       uint16_t eeprom_data;
+       int i;
 
-       if(hw->phy_type == e1000_phy_igp)
-               e1000_phy_init_script(hw);
+       DEBUGFUNC("e1000_read_mac_addr");
 
+       for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
+               offset = i >> 1;
+               if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
+                       DEBUGOUT("EEPROM Read Error\n");
+                       return -E1000_ERR_EEPROM;
+               }
+               hw->mac_addr[i] = eeprom_data & 0xff;
+               hw->mac_addr[i+1] = (eeprom_data >> 8) & 0xff;
+       }
+       if(((hw->mac_type == e1000_82546) || (hw->mac_type == e1000_82546_rev_3)) &&
+               (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1))
+               /* Invert the last bit if this is the second device */
+               hw->mac_addr[5] ^= 1;
        return E1000_SUCCESS;
 }
 
 /******************************************************************************
-* Probes the expected PHY address for known PHY IDs
-*
-* hw - Struct containing variables accessed by shared code
-******************************************************************************/
-static int
-e1000_detect_gig_phy(struct e1000_hw *hw)
+ * Initializes receive address filters.
+ *
+ * hw - Struct containing variables accessed by shared code 
+ *
+ * Places the MAC address in receive address register 0 and clears the rest
+ * of the receive addresss registers. Clears the multicast table. Assumes
+ * the receiver is in reset when the routine is called.
+ *****************************************************************************/
+static void
+e1000_init_rx_addrs(struct e1000_hw *hw)
 {
-       int32_t phy_init_status, ret_val;
-       uint16_t phy_id_high, phy_id_low;
-       boolean_t match = FALSE;
-
-       DEBUGFUNC("e1000_detect_gig_phy");
+       uint32_t i;
+       uint32_t addr_low;
+       uint32_t addr_high;
        
-       /* Read the PHY ID Registers to identify which PHY is onboard. */
-       if((ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high)))
-               return ret_val;
-
-       hw->phy_id = (uint32_t) (phy_id_high << 16);
-       udelay(20);
-       if((ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low)))
-               return ret_val;
+       DEBUGFUNC("e1000_init_rx_addrs");
        
-       hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
-#ifdef LINUX_DRIVER
-       hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
-#endif
+       /* Setup the receive address. */
+       DEBUGOUT("Programming MAC Address into RAR[0]\n");
+       addr_low = (hw->mac_addr[0] |
+               (hw->mac_addr[1] << 8) |
+               (hw->mac_addr[2] << 16) | (hw->mac_addr[3] << 24));
        
-       switch(hw->mac_type) {
-       case e1000_82543:
-               if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
-               break;
-       case e1000_82544:
-               if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
-               break;
-       case e1000_82540:
-       case e1000_82545:
-       case e1000_82545_rev_3:
-       case e1000_82546:
-       case e1000_82546_rev_3:
-               if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
-               break;
-       case e1000_82541:
-       case e1000_82541_rev_2:
-       case e1000_82547:
-       case e1000_82547_rev_2:
-               if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
-               break;
-       default:
-               DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
-               return -E1000_ERR_CONFIG;
-       }
-       phy_init_status = e1000_set_phy_type(hw);
-
-       if ((match) && (phy_init_status == E1000_SUCCESS)) {
-               DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
-               return E1000_SUCCESS;
+       addr_high = (hw->mac_addr[4] |
+               (hw->mac_addr[5] << 8) | E1000_RAH_AV);
+       
+       E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
+       E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
+       
+       /* Zero out the other 15 receive addresses. */
+       DEBUGOUT("Clearing RAR[1-15]\n");
+       for(i = 1; i < E1000_RAR_ENTRIES; i++) {
+               E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
+               E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
        }
-       DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
-       return -E1000_ERR_PHY;
 }
 
 /******************************************************************************
- * Sets up eeprom variables in the hw struct.  Must be called after mac_type
- * is configured.
+ * Clears the VLAN filer table
  *
  * hw - Struct containing variables accessed by shared code
  *****************************************************************************/
 static void
-e1000_init_eeprom_params(struct e1000_hw *hw)
+e1000_clear_vfta(struct e1000_hw *hw)
 {
-       struct e1000_eeprom_info *eeprom = &hw->eeprom;
-       uint32_t eecd = E1000_READ_REG(hw, EECD);
-       uint16_t eeprom_size;
-
-       DEBUGFUNC("e1000_init_eeprom_params");
+       uint32_t offset;
+    
+       for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
+               E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
+}
 
-       switch (hw->mac_type) {
-       case e1000_82542_rev2_0:
-       case e1000_82542_rev2_1:
-       case e1000_82543:
-       case e1000_82544:
-               eeprom->type = e1000_eeprom_microwire;
-               eeprom->word_size = 64;
-               eeprom->opcode_bits = 3;
-               eeprom->address_bits = 6;
-               eeprom->delay_usec = 50;
-               break;
-       case e1000_82540:
-       case e1000_82545:
-       case e1000_82545_rev_3:
-       case e1000_82546:
-       case e1000_82546_rev_3:
-               eeprom->type = e1000_eeprom_microwire;
-               eeprom->opcode_bits = 3;
-               eeprom->delay_usec = 50;
-               if(eecd & E1000_EECD_SIZE) {
-                       eeprom->word_size = 256;
-                       eeprom->address_bits = 8;
-               } else {
-                       eeprom->word_size = 64;
-                       eeprom->address_bits = 6;
-               }
-               break;
-       case e1000_82541:
-       case e1000_82541_rev_2:
-       case e1000_82547:
-       case e1000_82547_rev_2:
-               if (eecd & E1000_EECD_TYPE) {
-                       eeprom->type = e1000_eeprom_spi;
-                       if (eecd & E1000_EECD_ADDR_BITS) {
-                               eeprom->page_size = 32;
-                               eeprom->address_bits = 16;
-                       } else {
-                               eeprom->page_size = 8;
-                               eeprom->address_bits = 8;
-                       }
-               } else {
-                       eeprom->type = e1000_eeprom_microwire;
-                       eeprom->opcode_bits = 3;
-                       eeprom->delay_usec = 50;
-                       if (eecd & E1000_EECD_ADDR_BITS) {
-                               eeprom->word_size = 256;
-                               eeprom->address_bits = 8;
-                       } else {
-                               eeprom->word_size = 64;
-                               eeprom->address_bits = 6;
-                       }
-               }
-               break;
-       default:
-               eeprom->type = e1000_eeprom_spi;
-               if (eecd & E1000_EECD_ADDR_BITS) {
-                       eeprom->page_size = 32;
-                       eeprom->address_bits = 16;
-               } else {
-                       eeprom->page_size = 8;
-                       eeprom->address_bits = 8;
-               }
-               break;
-       }
+/******************************************************************************
+* Writes a value to one of the devices registers using port I/O (as opposed to
+* memory mapped I/O). Only 82544 and newer devices support port I/O. *
+* hw - Struct containing variables accessed by shared code
+* offset - offset to write to * value - value to write
+*****************************************************************************/
+static void
+e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value)
+{
+       uint32_t io_addr = hw->io_base;
+       uint32_t io_data = hw->io_base + 4;
+       e1000_io_write(hw, io_addr, offset);
+       e1000_io_write(hw, io_data, value);
+}
 
-       if (eeprom->type == e1000_eeprom_spi) {
-               eeprom->opcode_bits = 8;
-               eeprom->delay_usec = 1;
-               eeprom->word_size = 64;
-               if (e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) {
-                       eeprom_size &= EEPROM_SIZE_MASK;
 
-                       switch (eeprom_size) {
-                       case EEPROM_SIZE_16KB:
-                               eeprom->word_size = 8192;
-                               break;
-                       case EEPROM_SIZE_8KB:
-                               eeprom->word_size = 4096;
-                               break;
-                       case EEPROM_SIZE_4KB:
-                               eeprom->word_size = 2048;
-                               break;
-                       case EEPROM_SIZE_2KB:
-                               eeprom->word_size = 1024;
-                               break;
-                       case EEPROM_SIZE_1KB:
-                               eeprom->word_size = 512;
-                               break;
-                       case EEPROM_SIZE_512B:
-                               eeprom->word_size = 256;
-                               break;
-                       case EEPROM_SIZE_128B:
-                       default:
-                               break;
-                       }
-               }
-       }
-}
+/******************************************************************************
+ * Functions from e1000_main.c of the linux driver
+ ******************************************************************************/
 
 /**
  * e1000_reset - Reset the adapter
@@ -3261,6 +3498,8 @@ e1000_reset(struct e1000_hw *hw)
 
        if(hw->mac_type < e1000_82547) {
                pba = E1000_PBA_48K;
+       } else if (hw->mac_type == e1000_80003es2lan) {
+               pba = E1000_PBA_38K;
        } else {
                pba = E1000_PBA_30K;
        }
@@ -3352,14 +3591,32 @@ e1000_sw_init(struct pci_device *pdev, struct e1000_hw *hw)
        return E1000_SUCCESS;
 }
 
+#if 0
+static uint32_t
+e1000_io_read(struct e1000_hw *hw __unused, uint32_t port)
+{
+        return inl(port);
+}
+#endif
+
+static void
+e1000_io_write(struct e1000_hw *hw __unused, uint32_t port, uint32_t value)
+{
+        outl(value, port);
+}
+
+
+/******************************************************************************
+ * Functions not present in the linux driver
+ ******************************************************************************/
+
 static void fill_rx (void)
 {
        struct e1000_rx_desc *rd;
-       rx_last = rx_tail;
        rd = rx_base + rx_tail;
-       rx_tail = (rx_tail + 1) % 8;
        memset (rd, 0, 16);
-       rd->buffer_addr = virt_to_bus(&packet);
+       rd->buffer_addr = virt_to_bus(&packets[MAX_PACKET*(rx_tail%RX_BUFS)]);
+       rx_tail = (rx_tail + 1) % 8;
        E1000_WRITE_REG (&hw, RDT, rx_tail);
 }
 
@@ -3367,6 +3624,7 @@ static void init_descriptor (void)
 {
        unsigned long ptr;
        unsigned long tctl;
+       int i;
 
        ptr = virt_to_phys(tx_pool);
        if (ptr & 0xf)
@@ -3427,7 +3685,8 @@ static void init_descriptor (void)
                E1000_RCTL_BAM | 
                E1000_RCTL_SZ_2048 | 
                E1000_RCTL_MPE);
-       fill_rx();
+       for (i = 0; i < RX_BUFS; i++)
+               fill_rx();
 }
 
 
@@ -3442,6 +3701,7 @@ e1000_poll (struct nic *nic, int retrieve)
        /* nic->packet should contain data on return */
        /* nic->packetlen should contain length of data */
        struct e1000_rx_desc *rd;
+       char *packet = &packets[MAX_PACKET*(rx_last%RX_BUFS)];
        uint32_t icr;
 
        rd = rx_base + rx_last;
@@ -3453,6 +3713,7 @@ e1000_poll (struct nic *nic, int retrieve)
        //      printf("recv: packet %! -> %! len=%d \n", packet+6, packet,rd->Length);
        memcpy (nic->packet, packet, rd->length);
        nic->packetlen = rd->length;
+       rx_last = (rx_last + 1) %8;
        fill_rx ();
 
        /* Acknowledge interrupt. */
@@ -3701,6 +3962,8 @@ PCI_ROM(0x8086, 0x1078, "e1000-82541er",       "Intel EtherExpressPro1000 82541ER
 PCI_ROM(0x8086, 0x1079, "e1000-82546gb-copper",             "Intel EtherExpressPro1000 82546GB Copper"),
 PCI_ROM(0x8086, 0x107a, "e1000-82546gb-fiber",      "Intel EtherExpressPro1000 82546GB Fiber"),
 PCI_ROM(0x8086, 0x107b, "e1000-82546gb-serdes",             "Intel EtherExpressPro1000 82546GB SERDES"),
+PCI_ROM(0x8086, 0x107c, "e1000-82541pi",            "Intel EtherExpressPro1000 82541PI"),
+PCI_ROM(0x8086, 0x1096, "e1000_80003es2lan",        "Intel EtherExpressPro1000 GB COPPER"),
 };
 
 static struct pci_driver e1000_driver __pci_driver = {