patches from Tim Fletcher and Per Jessen for gcc 4.1 compatibility with volatile...
[etherboot.git] / src / drivers / net / tg3.c
1 /* $Id$
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002 Jeff Garzik (jgarzik@mandrakesoft.com)
6  * Copyright (C) 2003 Eric Biederman (ebiederman@lnxi.com)  [etherboot port]
7  */
8
9 /* 11-13-2003   timlegge        Fix Issue with NetGear GA302T 
10  * 11-18-2003   ebiederm        Generalize NetGear Fix to what the code was supposed to be.
11  * 01-06-2005   Alf (Frederic Olivie) Add Dell bcm 5751 (0x1677) support
12  * 04-15-2005   Martin Vogt Add Fujitsu Siemens Computer (FSC) 0x1734 bcm 5751 0x105d support
13  */
14
15 #include "etherboot.h"
16 #include "nic.h"
17 #include "pci.h"
18 #include "timer.h"
19 #include "string.h"
20 #include "tg3.h"
21
22 #define SUPPORT_COPPER_PHY  1
23 #define SUPPORT_FIBER_PHY   1
24 #define SUPPORT_LINK_REPORT 1
25 #define SUPPORT_PARTNO_STR  1
26 #define SUPPORT_PHY_STR     1
27
28 struct tg3 tg3;
29
30 /* Dummy defines for error handling */
31 #define EBUSY  1
32 #define ENODEV 2
33 #define EINVAL 3
34 #define ENOMEM 4
35
36
37 /* These numbers seem to be hard coded in the NIC firmware somehow.
38  * You can't change the ring sizes, but you can change where you place
39  * them in the NIC onboard memory.
40  */
41 #define TG3_RX_RING_SIZE                512
42 #define TG3_DEF_RX_RING_PENDING         20      /* RX_RING_PENDING seems to be o.k. at 20 and 200 */
43 #define TG3_RX_RCB_RING_SIZE    1024
44
45 /*      (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ? \
46          512 : 1024) */
47 #define TG3_TX_RING_SIZE                512
48 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
49
50 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_RING_SIZE)
51 #define TG3_RX_RCB_RING_BYTES   (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_RCB_RING_SIZE)
52
53 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * TG3_TX_RING_SIZE)
54 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
55 #define PREV_TX(N)              (((N) - 1) & (TG3_TX_RING_SIZE - 1))
56
57 #define RX_PKT_BUF_SZ           (1536 + 2 + 64)
58
59
60 static struct bss {
61         struct tg3_rx_buffer_desc rx_std[TG3_RX_RING_SIZE];
62         struct tg3_rx_buffer_desc rx_rcb[TG3_RX_RCB_RING_SIZE];
63         struct tg3_tx_buffer_desc tx_ring[TG3_TX_RING_SIZE];
64         struct tg3_hw_status      hw_status;
65         struct tg3_hw_stats       hw_stats;
66         unsigned char             rx_bufs[TG3_DEF_RX_RING_PENDING][RX_PKT_BUF_SZ];
67 } tg3_bss;
68
69 /**
70  * pci_save_state - save the PCI configuration space of a device before suspending
71  * @dev: - PCI device that we're dealing with
72  * @buffer: - buffer to hold config space context
73  *
74  * @buffer must be large enough to hold the entire PCI 2.2 config space 
75  * (>= 64 bytes).
76  */
77 static int pci_save_state(struct pci_device *dev, uint32_t *buffer)
78 {
79         int i;
80         for (i = 0; i < 16; i++)
81                 pci_read_config_dword(dev, i * 4,&buffer[i]);
82         return 0;
83 }
84
85 /** 
86  * pci_restore_state - Restore the saved state of a PCI device
87  * @dev: - PCI device that we're dealing with
88  * @buffer: - saved PCI config space
89  *
90  */
91 static int pci_restore_state(struct pci_device *dev, uint32_t *buffer)
92 {
93         int i;
94
95         for (i = 0; i < 16; i++)
96                 pci_write_config_dword(dev,i * 4, buffer[i]);
97         return 0;
98 }
99
100 static void tg3_write_indirect_reg32(uint32_t off, uint32_t val)
101 {
102         pci_write_config_dword(tg3.pdev, TG3PCI_REG_BASE_ADDR, off);
103         pci_write_config_dword(tg3.pdev, TG3PCI_REG_DATA, val);
104 }
105
106 #define tw32(reg,val)           tg3_write_indirect_reg32((reg),(val))
107 #define tw32_mailbox(reg, val)  writel(((val) & 0xffffffff), tg3.regs + (reg))
108 #define tw16(reg,val)           writew(((val) & 0xffff), tg3.regs + (reg))
109 #define tw8(reg,val)            writeb(((val) & 0xff), tg3.regs + (reg))
110 #define tr32(reg)               readl(tg3.regs + (reg))
111 #define tr16(reg)               readw(tg3.regs + (reg))
112 #define tr8(reg)                readb(tg3.regs + (reg))
113
114 static void tw32_carefully(uint32_t reg, uint32_t val)
115 {
116         tw32(reg, val);
117         tr32(reg);
118         udelay(100);
119 }
120
121 static void tw32_mailbox2(uint32_t reg, uint32_t val)
122 {
123         tw32_mailbox(reg, val);
124         tr32(reg);
125 }
126
127 static void tg3_write_mem(uint32_t off, uint32_t val)
128 {
129         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
130         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_DATA, val);
131
132         /* Always leave this as zero. */
133         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
134 }
135
136 static void tg3_read_mem(uint32_t off, uint32_t *val)
137 {
138         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
139         pci_read_config_dword(tg3.pdev, TG3PCI_MEM_WIN_DATA, val);
140
141         /* Always leave this as zero. */
142         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
143 }
144
145 static void tg3_disable_ints(struct tg3 *tp)
146 {
147         tw32(TG3PCI_MISC_HOST_CTRL,
148              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
149         tw32_mailbox2(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
150 }
151
152 static void tg3_switch_clocks(struct tg3 *tp)
153 {
154         uint32_t orig_clock_ctrl, clock_ctrl;
155
156         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
157
158         orig_clock_ctrl = clock_ctrl;
159         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | CLOCK_CTRL_CLKRUN_OENABLE | 0x1f);
160         tp->pci_clock_ctrl = clock_ctrl;
161         
162         if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) &&
163             (!((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
164                && (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) &&
165                 (orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE)!=0) {
166                 tw32_carefully(TG3PCI_CLOCK_CTRL, 
167                         clock_ctrl | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
168                 tw32_carefully(TG3PCI_CLOCK_CTRL, 
169                         clock_ctrl | (CLOCK_CTRL_ALTCLK));
170         }
171         tw32_carefully(TG3PCI_CLOCK_CTRL, clock_ctrl);
172 }
173
174 #define PHY_BUSY_LOOPS  5000
175
176 static int tg3_readphy(struct tg3 *tp, int reg, uint32_t *val)
177 {
178         uint32_t frame_val;
179         int loops, ret;
180
181         tw32_carefully(MAC_MI_MODE, tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL);
182
183         *val = 0xffffffff;
184
185         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
186                       MI_COM_PHY_ADDR_MASK);
187         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
188                       MI_COM_REG_ADDR_MASK);
189         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
190         
191         tw32_carefully(MAC_MI_COM, frame_val);
192
193         loops = PHY_BUSY_LOOPS;
194         while (loops-- > 0) {
195                 udelay(10);
196                 frame_val = tr32(MAC_MI_COM);
197
198                 if ((frame_val & MI_COM_BUSY) == 0) {
199                         udelay(5);
200                         frame_val = tr32(MAC_MI_COM);
201                         break;
202                 }
203         }
204
205         ret = -EBUSY;
206         if (loops > 0) {
207                 *val = frame_val & MI_COM_DATA_MASK;
208                 ret = 0;
209         }
210
211         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
212
213         return ret;
214 }
215
216 static int tg3_writephy(struct tg3 *tp, int reg, uint32_t val)
217 {
218         uint32_t frame_val;
219         int loops, ret;
220
221         tw32_carefully(MAC_MI_MODE, tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL);
222
223         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
224                       MI_COM_PHY_ADDR_MASK);
225         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
226                       MI_COM_REG_ADDR_MASK);
227         frame_val |= (val & MI_COM_DATA_MASK);
228         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
229         
230         tw32_carefully(MAC_MI_COM, frame_val);
231
232         loops = PHY_BUSY_LOOPS;
233         while (loops-- > 0) {
234                 udelay(10);
235                 frame_val = tr32(MAC_MI_COM);
236                 if ((frame_val & MI_COM_BUSY) == 0) {
237                         udelay(5);
238                         frame_val = tr32(MAC_MI_COM);
239                         break;
240                 }
241         }
242
243         ret = -EBUSY;
244         if (loops > 0)
245                 ret = 0;
246
247         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
248
249         return ret;
250 }
251
252 static int tg3_writedsp(struct tg3 *tp, uint16_t addr, uint16_t val)
253 {
254         int err;
255         err  = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, addr);
256         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
257         return err;
258 }
259
260
261 static void tg3_phy_set_wirespeed(struct tg3 *tp)
262 {
263         uint32_t val;
264
265         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
266                 return;
267
268         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007);
269         tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
270         tg3_writephy(tp, MII_TG3_AUX_CTRL, (val | (1 << 15) | (1 << 4)));
271 }
272
273 static int tg3_bmcr_reset(struct tg3 *tp)
274 {
275         uint32_t phy_control;
276         int limit, err;
277
278         /* OK, reset it, and poll the BMCR_RESET bit until it
279          * clears or we time out.
280          */
281         phy_control = BMCR_RESET;
282         err = tg3_writephy(tp, MII_BMCR, phy_control);
283         if (err != 0)
284                 return -EBUSY;
285
286         limit = 5000;
287         while (limit--) {
288                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
289                 if (err != 0)
290                         return -EBUSY;
291
292                 if ((phy_control & BMCR_RESET) == 0) {
293                         udelay(40);
294                         break;
295                 }
296                 udelay(10);
297         }
298         if (limit <= 0)
299                 return -EBUSY;
300
301         return 0;
302 }
303
304 static int tg3_wait_macro_done(struct tg3 *tp)
305 {
306         int limit = 100;
307
308         while (limit--) {
309                 uint32_t tmp32;
310
311                 tg3_readphy(tp, 0x16, &tmp32);
312                 if ((tmp32 & 0x1000) == 0)
313                         break;
314         }
315         if (limit <= 0)
316                 return -EBUSY;
317
318         return 0;
319 }
320
321 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
322 {
323         static const uint32_t test_pat[4][6] = {
324         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
325         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
326         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
327         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
328         };
329         int chan;
330
331         for (chan = 0; chan < 4; chan++) {
332                 int i;
333
334                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
335                         (chan * 0x2000) | 0x0200);
336                 tg3_writephy(tp, 0x16, 0x0002);
337
338                 for (i = 0; i < 6; i++)
339                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
340                                 test_pat[chan][i]);
341
342                 tg3_writephy(tp, 0x16, 0x0202);
343                 if (tg3_wait_macro_done(tp)) {
344                         *resetp = 1;
345                         return -EBUSY;
346                 }
347
348                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
349                              (chan * 0x2000) | 0x0200);
350                 tg3_writephy(tp, 0x16, 0x0082);
351                 if (tg3_wait_macro_done(tp)) {
352                         *resetp = 1;
353                         return -EBUSY;
354                 }
355
356                 tg3_writephy(tp, 0x16, 0x0802);
357                 if (tg3_wait_macro_done(tp)) {
358                         *resetp = 1;
359                         return -EBUSY;
360                 }
361
362                 for (i = 0; i < 6; i += 2) {
363                         uint32_t low, high;
364
365                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low);
366                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high);
367                         if (tg3_wait_macro_done(tp)) {
368                                 *resetp = 1;
369                                 return -EBUSY;
370                         }
371                         low &= 0x7fff;
372                         high &= 0x000f;
373                         if (low != test_pat[chan][i] ||
374                             high != test_pat[chan][i+1]) {
375                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
376                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
377                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
378
379                                 return -EBUSY;
380                         }
381                 }
382         }
383
384         return 0;
385 }
386
387 static int tg3_phy_reset_chanpat(struct tg3 *tp)
388 {
389         int chan;
390
391         for (chan = 0; chan < 4; chan++) {
392                 int i;
393
394                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
395                              (chan * 0x2000) | 0x0200);
396                 tg3_writephy(tp, 0x16, 0x0002);
397                 for (i = 0; i < 6; i++)
398                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
399                 tg3_writephy(tp, 0x16, 0x0202);
400                 if (tg3_wait_macro_done(tp))
401                         return -EBUSY;
402         }
403
404         return 0;
405 }
406
407 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
408 {
409         uint32_t reg32, phy9_orig;
410         int retries, do_phy_reset, err;
411
412         retries = 10;
413         do_phy_reset = 1;
414         do {
415                 if (do_phy_reset) {
416                         err = tg3_bmcr_reset(tp);
417                         if (err)
418                                 return err;
419                         do_phy_reset = 0;
420                 }
421                 
422                 /* Disable transmitter and interrupt.  */
423                 tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);
424                 reg32 |= 0x3000;
425                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
426
427                 /* Set full-duplex, 1000 mbps.  */
428                 tg3_writephy(tp, MII_BMCR,
429                         BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
430
431                 /* Set to master mode.  */
432                 tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig);
433                 tg3_writephy(tp, MII_TG3_CTRL,
434                         (MII_TG3_CTRL_AS_MASTER |
435                                 MII_TG3_CTRL_ENABLE_AS_MASTER));
436
437                 /* Enable SM_DSP_CLOCK and 6dB.  */
438                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
439
440                 /* Block the PHY control access.  */
441                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
442                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
443
444                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
445                 if (!err)
446                         break;
447         } while (--retries);
448
449         err = tg3_phy_reset_chanpat(tp);
450         if (err)
451                 return err;
452
453         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
454         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
455
456         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
457         tg3_writephy(tp, 0x16, 0x0000);
458
459         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
460
461         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
462
463         tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);
464         reg32 &= ~0x3000;
465         tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
466
467         return err;
468 }
469
470 /* This will reset the tigon3 PHY if there is no valid
471  * link.
472  */
473 static int tg3_phy_reset(struct tg3 *tp)
474 {
475         uint32_t phy_status;
476         int err;
477
478         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
479         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
480         if (err != 0)
481                 return -EBUSY;
482
483         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
484                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
485                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
486                 err = tg3_phy_reset_5703_4_5(tp);
487                 if (err)
488                         return err;
489                 goto out;
490         }
491         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
492           // Taken from Broadcom's source code
493           tg3_writephy(tp, 0x18, 0x0c00);
494           tg3_writephy(tp, 0x17, 0x000a);
495           tg3_writephy(tp, 0x15, 0x310b);
496           tg3_writephy(tp, 0x17, 0x201f);
497           tg3_writephy(tp, 0x15, 0x9506);
498           tg3_writephy(tp, 0x17, 0x401f);
499           tg3_writephy(tp, 0x15, 0x14e2);
500           tg3_writephy(tp, 0x18, 0x0400);
501         }
502         err = tg3_bmcr_reset(tp);
503         if (err)
504                 return err;
505  out:
506         tg3_phy_set_wirespeed(tp);
507         return 0;
508 }
509
510 static void tg3_set_power_state_0(struct tg3 *tp)
511 {
512         uint16_t power_control;
513         int pm = tp->pm_cap;
514
515         /* Make sure register accesses (indirect or otherwise)
516          * will function correctly.
517          */
518         pci_write_config_dword(tp->pdev,  TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
519
520         pci_read_config_word(tp->pdev, pm + PCI_PM_CTRL, &power_control);
521
522         power_control |= PCI_PM_CTRL_PME_STATUS;
523         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
524         power_control |= 0;
525         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
526
527         tw32_carefully(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
528
529         return;
530 }
531
532
533 #if SUPPORT_LINK_REPORT
534 static void tg3_link_report(struct tg3 *tp)
535 {
536         if (!tp->carrier_ok) {
537                 printf("Link is down.\n");
538         } else {
539                 printf("Link is up at %d Mbps, %s duplex. %s %s %s\n",
540                         (tp->link_config.active_speed == SPEED_1000 ?
541                                1000 :
542                         (tp->link_config.active_speed == SPEED_100 ?
543                                 100 : 10)),
544                         (tp->link_config.active_duplex == DUPLEX_FULL ?  
545                                 "full" : "half"),
546                         (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "TX" : "",
547                         (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "RX" : "",
548                         (tp->tg3_flags & (TG3_FLAG_TX_PAUSE |TG3_FLAG_RX_PAUSE)) ? "flow control" : "");
549         }
550 }
551 #else
552 #define tg3_link_report(tp)
553 #endif
554
555 static void tg3_setup_flow_control(struct tg3 *tp, uint32_t local_adv, uint32_t remote_adv)
556 {
557         uint32_t new_tg3_flags = 0;
558
559         if (local_adv & ADVERTISE_PAUSE_CAP) {
560                 if (local_adv & ADVERTISE_PAUSE_ASYM) {
561                         if (remote_adv & LPA_PAUSE_CAP)
562                                 new_tg3_flags |=
563                                         (TG3_FLAG_RX_PAUSE |
564                                          TG3_FLAG_TX_PAUSE);
565                         else if (remote_adv & LPA_PAUSE_ASYM)
566                                 new_tg3_flags |=
567                                         (TG3_FLAG_RX_PAUSE);
568                 } else {
569                         if (remote_adv & LPA_PAUSE_CAP)
570                                 new_tg3_flags |=
571                                         (TG3_FLAG_RX_PAUSE |
572                                          TG3_FLAG_TX_PAUSE);
573                 }
574         } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
575                 if ((remote_adv & LPA_PAUSE_CAP) &&
576                     (remote_adv & LPA_PAUSE_ASYM))
577                         new_tg3_flags |= TG3_FLAG_TX_PAUSE;
578         }
579
580         tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
581         tp->tg3_flags |= new_tg3_flags;
582
583         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
584                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
585         else
586                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
587
588         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
589                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
590         else
591                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
592 }
593
594 #if SUPPORT_COPPER_PHY
595 static void tg3_aux_stat_to_speed_duplex(
596         struct tg3 *tp __unused, uint32_t val, uint8_t *speed, uint8_t *duplex)
597 {
598         static const uint8_t map[] = {
599                 [0] = (SPEED_INVALID << 2) | DUPLEX_INVALID,
600                 [MII_TG3_AUX_STAT_10HALF >> 8]   = (SPEED_10 << 2) | DUPLEX_HALF,
601                 [MII_TG3_AUX_STAT_10FULL >> 8]   = (SPEED_10 << 2) | DUPLEX_FULL,
602                 [MII_TG3_AUX_STAT_100HALF >> 8]  = (SPEED_100 << 2) | DUPLEX_HALF,
603                 [MII_TG3_AUX_STAT_100_4 >> 8] = (SPEED_INVALID << 2) | DUPLEX_INVALID,
604                 [MII_TG3_AUX_STAT_100FULL >> 8]  = (SPEED_100 << 2) | DUPLEX_FULL,
605                 [MII_TG3_AUX_STAT_1000HALF >> 8] = (SPEED_1000 << 2) | DUPLEX_HALF,
606                 [MII_TG3_AUX_STAT_1000FULL >> 8] = (SPEED_1000 << 2) | DUPLEX_FULL,
607         };
608         uint8_t result;
609         result = map[(val & MII_TG3_AUX_STAT_SPDMASK) >> 8];
610         *speed = result >> 2;
611         *duplex = result & 3;
612 }
613
614 static int tg3_phy_copper_begin(struct tg3 *tp)
615 {
616         uint32_t new_adv;
617
618         tp->link_config.advertising =
619                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
620                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
621                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
622                         ADVERTISED_Autoneg | ADVERTISED_MII);
623         
624         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) {
625                 tp->link_config.advertising &=
626                         ~(ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
627         }
628         
629         new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
630         if (tp->link_config.advertising & ADVERTISED_10baseT_Half) {
631                 new_adv |= ADVERTISE_10HALF;
632         }
633         if (tp->link_config.advertising & ADVERTISED_10baseT_Full) {
634                 new_adv |= ADVERTISE_10FULL;
635         }
636         if (tp->link_config.advertising & ADVERTISED_100baseT_Half) {
637                 new_adv |= ADVERTISE_100HALF;
638         }
639         if (tp->link_config.advertising & ADVERTISED_100baseT_Full) {
640                 new_adv |= ADVERTISE_100FULL;
641         }
642         tg3_writephy(tp, MII_ADVERTISE, new_adv);
643         
644         if (tp->link_config.advertising &
645                 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
646                 new_adv = 0;
647                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) {
648                         new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
649                 }
650                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) {
651                         new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
652                 }
653                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
654                         (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
655                                 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) {
656                         new_adv |= (MII_TG3_CTRL_AS_MASTER |
657                                 MII_TG3_CTRL_ENABLE_AS_MASTER);
658                 }
659                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
660         } else {
661                 tg3_writephy(tp, MII_TG3_CTRL, 0);
662         }
663
664         tg3_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
665
666         return 0;
667 }
668
669 static int tg3_init_5401phy_dsp(struct tg3 *tp)
670 {
671         int err;
672
673         /* Turn off tap power management. */
674         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c20);
675         
676         err |= tg3_writedsp(tp, 0x0012, 0x1804);
677         err |= tg3_writedsp(tp, 0x0013, 0x1204);
678         err |= tg3_writedsp(tp, 0x8006, 0x0132);
679         err |= tg3_writedsp(tp, 0x8006, 0x0232);
680         err |= tg3_writedsp(tp, 0x201f, 0x0a20);
681
682         udelay(40);
683
684         return err;
685 }
686
687 static int tg3_setup_copper_phy(struct tg3 *tp)
688 {
689         int current_link_up;
690         uint32_t bmsr, dummy;
691         int i, err;
692
693         tw32_carefully(MAC_STATUS,
694                 (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED
695                  | MAC_STATUS_LNKSTATE_CHANGED));
696
697         tp->mi_mode = MAC_MI_MODE_BASE;
698         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
699
700         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
701
702         /* Some third-party PHYs need to be reset on link going
703          * down.
704          */
705         if (    (       (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
706                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
707                         (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)) &&
708                 (tp->carrier_ok)) {
709                 tg3_readphy(tp, MII_BMSR, &bmsr);
710                 tg3_readphy(tp, MII_BMSR, &bmsr);
711                 if (!(bmsr & BMSR_LSTATUS))
712                         tg3_phy_reset(tp);
713         }
714
715         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
716                 tg3_readphy(tp, MII_BMSR, &bmsr);
717                 tg3_readphy(tp, MII_BMSR, &bmsr);
718
719                 if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
720                         bmsr = 0;
721
722                 if (!(bmsr & BMSR_LSTATUS)) {
723                         err = tg3_init_5401phy_dsp(tp);
724                         if (err)
725                                 return err;
726
727                         tg3_readphy(tp, MII_BMSR, &bmsr);
728                         for (i = 0; i < 1000; i++) {
729                                 udelay(10);
730                                 tg3_readphy(tp, MII_BMSR, &bmsr);
731                                 if (bmsr & BMSR_LSTATUS) {
732                                         udelay(40);
733                                         break;
734                                 }
735                         }
736
737                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
738                             !(bmsr & BMSR_LSTATUS) &&
739                             tp->link_config.active_speed == SPEED_1000) {
740                                 err = tg3_phy_reset(tp);
741                                 if (!err)
742                                         err = tg3_init_5401phy_dsp(tp);
743                                 if (err)
744                                         return err;
745                         }
746                 }
747         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
748                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
749                 /* 5701 {A0,B0} CRC bug workaround */
750                 tg3_writephy(tp, 0x15, 0x0a75);
751                 tg3_writephy(tp, 0x1c, 0x8c68);
752                 tg3_writephy(tp, 0x1c, 0x8d68);
753                 tg3_writephy(tp, 0x1c, 0x8c68);
754         }
755
756         /* Clear pending interrupts... */
757         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
758         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
759
760         tg3_writephy(tp, MII_TG3_IMASK, ~0);
761
762         if (tp->led_mode == led_mode_three_link)
763                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
764                              MII_TG3_EXT_CTRL_LNK3_LED_MODE);
765         else
766                 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
767
768         current_link_up = 0;
769
770         tg3_readphy(tp, MII_BMSR, &bmsr);
771         tg3_readphy(tp, MII_BMSR, &bmsr);
772
773         if (bmsr & BMSR_LSTATUS) {
774                 uint32_t aux_stat, bmcr;
775
776                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
777                 for (i = 0; i < 2000; i++) {
778                         udelay(10);
779                         tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
780                         if (aux_stat)
781                                 break;
782                 }
783
784                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
785                         &tp->link_config.active_speed,
786                         &tp->link_config.active_duplex);
787                 tg3_readphy(tp, MII_BMCR, &bmcr);
788                 tg3_readphy(tp, MII_BMCR, &bmcr);
789                 if (bmcr & BMCR_ANENABLE) {
790                         uint32_t gig_ctrl;
791                         
792                         current_link_up = 1;
793                         
794                         /* Force autoneg restart if we are exiting
795                          * low power mode.
796                          */
797                         tg3_readphy(tp, MII_TG3_CTRL, &gig_ctrl);
798                         if (!(gig_ctrl & (MII_TG3_CTRL_ADV_1000_HALF |
799                                       MII_TG3_CTRL_ADV_1000_FULL))) {
800                                 current_link_up = 0;
801                         }
802                 } else {
803                         current_link_up = 0;
804                 }
805         }
806
807         if (current_link_up == 1 &&
808                 (tp->link_config.active_duplex == DUPLEX_FULL)) {
809                 uint32_t local_adv, remote_adv;
810
811                 tg3_readphy(tp, MII_ADVERTISE, &local_adv);
812                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
813
814                 tg3_readphy(tp, MII_LPA, &remote_adv);
815                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
816
817                 /* If we are not advertising full pause capability,
818                  * something is wrong.  Bring the link down and reconfigure.
819                  */
820                 if (local_adv != ADVERTISE_PAUSE_CAP) {
821                         current_link_up = 0;
822                 } else {
823                         tg3_setup_flow_control(tp, local_adv, remote_adv);
824                 }
825         }
826
827         if (current_link_up == 0) {
828                 uint32_t tmp;
829
830                 tg3_phy_copper_begin(tp);
831
832                 tg3_readphy(tp, MII_BMSR, &tmp);
833                 tg3_readphy(tp, MII_BMSR, &tmp);
834                 if (tmp & BMSR_LSTATUS)
835                         current_link_up = 1;
836         }
837
838         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
839         if (current_link_up == 1) {
840                 if (tp->link_config.active_speed == SPEED_100 ||
841                     tp->link_config.active_speed == SPEED_10)
842                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
843                 else
844                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
845         } else
846                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
847
848         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
849         if (tp->link_config.active_duplex == DUPLEX_HALF)
850                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
851
852         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
853         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
854                 if ((tp->led_mode == led_mode_link10) ||
855                     (current_link_up == 1 &&
856                      tp->link_config.active_speed == SPEED_10))
857                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
858         } else {
859                 if (current_link_up == 1)
860                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
861                 tw32(MAC_LED_CTRL, LED_CTRL_PHY_MODE_1);
862         }
863
864         /* ??? Without this setting Netgear GA302T PHY does not
865          * ??? send/receive packets...
866          * With this other PHYs cannot bring up the link
867          */
868         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
869                 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
870                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
871                 tw32_carefully(MAC_MI_MODE, tp->mi_mode);
872         }
873
874         tw32_carefully(MAC_MODE, tp->mac_mode);
875
876         /* Link change polled. */
877         tw32_carefully(MAC_EVENT, 0);
878
879         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
880             current_link_up == 1 &&
881             tp->link_config.active_speed == SPEED_1000 &&
882             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
883              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
884                 udelay(120);
885                 tw32_carefully(MAC_STATUS,
886                         (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED));
887                 tg3_write_mem(
888                               NIC_SRAM_FIRMWARE_MBOX,
889                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
890         }
891
892         if (current_link_up != tp->carrier_ok) {
893                 tp->carrier_ok = current_link_up;
894                 tg3_link_report(tp);
895         }
896
897         return 0;
898 }
899 #else
900 #define tg3_setup_copper_phy(TP) (-EINVAL)
901 #endif /* SUPPORT_COPPER_PHY */
902
903 #if SUPPORT_FIBER_PHY
904 struct tg3_fiber_aneginfo {
905         int state;
906 #define ANEG_STATE_UNKNOWN              0
907 #define ANEG_STATE_AN_ENABLE            1
908 #define ANEG_STATE_RESTART_INIT         2
909 #define ANEG_STATE_RESTART              3
910 #define ANEG_STATE_DISABLE_LINK_OK      4
911 #define ANEG_STATE_ABILITY_DETECT_INIT  5
912 #define ANEG_STATE_ABILITY_DETECT       6
913 #define ANEG_STATE_ACK_DETECT_INIT      7
914 #define ANEG_STATE_ACK_DETECT           8
915 #define ANEG_STATE_COMPLETE_ACK_INIT    9
916 #define ANEG_STATE_COMPLETE_ACK         10
917 #define ANEG_STATE_IDLE_DETECT_INIT     11
918 #define ANEG_STATE_IDLE_DETECT          12
919 #define ANEG_STATE_LINK_OK              13
920 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
921 #define ANEG_STATE_NEXT_PAGE_WAIT       15
922
923         uint32_t flags;
924 #define MR_AN_ENABLE            0x00000001
925 #define MR_RESTART_AN           0x00000002
926 #define MR_AN_COMPLETE          0x00000004
927 #define MR_PAGE_RX              0x00000008
928 #define MR_NP_LOADED            0x00000010
929 #define MR_TOGGLE_TX            0x00000020
930 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
931 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
932 #define MR_LP_ADV_SYM_PAUSE     0x00000100
933 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
934 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
935 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
936 #define MR_LP_ADV_NEXT_PAGE     0x00001000
937 #define MR_TOGGLE_RX            0x00002000
938 #define MR_NP_RX                0x00004000
939
940 #define MR_LINK_OK              0x80000000
941
942         unsigned long link_time, cur_time;
943
944         uint32_t ability_match_cfg;
945         int ability_match_count;
946
947         char ability_match, idle_match, ack_match;
948
949         uint32_t txconfig, rxconfig;
950 #define ANEG_CFG_NP             0x00000080
951 #define ANEG_CFG_ACK            0x00000040
952 #define ANEG_CFG_RF2            0x00000020
953 #define ANEG_CFG_RF1            0x00000010
954 #define ANEG_CFG_PS2            0x00000001
955 #define ANEG_CFG_PS1            0x00008000
956 #define ANEG_CFG_HD             0x00004000
957 #define ANEG_CFG_FD             0x00002000
958 #define ANEG_CFG_INVAL          0x00001f06
959
960 };
961 #define ANEG_OK         0
962 #define ANEG_DONE       1
963 #define ANEG_TIMER_ENAB 2
964 #define ANEG_FAILED     -1
965
966 #define ANEG_STATE_SETTLE_TIME  10000
967
968 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
969                                    struct tg3_fiber_aneginfo *ap)
970 {
971         unsigned long delta;
972         uint32_t rx_cfg_reg;
973         int ret;
974
975         if (ap->state == ANEG_STATE_UNKNOWN) {
976                 ap->rxconfig = 0;
977                 ap->link_time = 0;
978                 ap->cur_time = 0;
979                 ap->ability_match_cfg = 0;
980                 ap->ability_match_count = 0;
981                 ap->ability_match = 0;
982                 ap->idle_match = 0;
983                 ap->ack_match = 0;
984         }
985         ap->cur_time++;
986
987         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
988                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
989
990                 if (rx_cfg_reg != ap->ability_match_cfg) {
991                         ap->ability_match_cfg = rx_cfg_reg;
992                         ap->ability_match = 0;
993                         ap->ability_match_count = 0;
994                 } else {
995                         if (++ap->ability_match_count > 1) {
996                                 ap->ability_match = 1;
997                                 ap->ability_match_cfg = rx_cfg_reg;
998                         }
999                 }
1000                 if (rx_cfg_reg & ANEG_CFG_ACK)
1001                         ap->ack_match = 1;
1002                 else
1003                         ap->ack_match = 0;
1004
1005                 ap->idle_match = 0;
1006         } else {
1007                 ap->idle_match = 1;
1008                 ap->ability_match_cfg = 0;
1009                 ap->ability_match_count = 0;
1010                 ap->ability_match = 0;
1011                 ap->ack_match = 0;
1012
1013                 rx_cfg_reg = 0;
1014         }
1015
1016         ap->rxconfig = rx_cfg_reg;
1017         ret = ANEG_OK;
1018
1019         switch(ap->state) {
1020         case ANEG_STATE_UNKNOWN:
1021                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
1022                         ap->state = ANEG_STATE_AN_ENABLE;
1023
1024                 /* fallthru */
1025         case ANEG_STATE_AN_ENABLE:
1026                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
1027                 if (ap->flags & MR_AN_ENABLE) {
1028                         ap->link_time = 0;
1029                         ap->cur_time = 0;
1030                         ap->ability_match_cfg = 0;
1031                         ap->ability_match_count = 0;
1032                         ap->ability_match = 0;
1033                         ap->idle_match = 0;
1034                         ap->ack_match = 0;
1035
1036                         ap->state = ANEG_STATE_RESTART_INIT;
1037                 } else {
1038                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
1039                 }
1040                 break;
1041
1042         case ANEG_STATE_RESTART_INIT:
1043                 ap->link_time = ap->cur_time;
1044                 ap->flags &= ~(MR_NP_LOADED);
1045                 ap->txconfig = 0;
1046                 tw32(MAC_TX_AUTO_NEG, 0);
1047                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1048                 tw32_carefully(MAC_MODE, tp->mac_mode);
1049
1050                 ret = ANEG_TIMER_ENAB;
1051                 ap->state = ANEG_STATE_RESTART;
1052
1053                 /* fallthru */
1054         case ANEG_STATE_RESTART:
1055                 delta = ap->cur_time - ap->link_time;
1056                 if (delta > ANEG_STATE_SETTLE_TIME) {
1057                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
1058                 } else {
1059                         ret = ANEG_TIMER_ENAB;
1060                 }
1061                 break;
1062
1063         case ANEG_STATE_DISABLE_LINK_OK:
1064                 ret = ANEG_DONE;
1065                 break;
1066
1067         case ANEG_STATE_ABILITY_DETECT_INIT:
1068                 ap->flags &= ~(MR_TOGGLE_TX);
1069                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
1070                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1071                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1072                 tw32_carefully(MAC_MODE, tp->mac_mode);
1073
1074                 ap->state = ANEG_STATE_ABILITY_DETECT;
1075                 break;
1076
1077         case ANEG_STATE_ABILITY_DETECT:
1078                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
1079                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
1080                 }
1081                 break;
1082
1083         case ANEG_STATE_ACK_DETECT_INIT:
1084                 ap->txconfig |= ANEG_CFG_ACK;
1085                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1086                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1087                 tw32_carefully(MAC_MODE, tp->mac_mode);
1088
1089                 ap->state = ANEG_STATE_ACK_DETECT;
1090
1091                 /* fallthru */
1092         case ANEG_STATE_ACK_DETECT:
1093                 if (ap->ack_match != 0) {
1094                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
1095                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
1096                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
1097                         } else {
1098                                 ap->state = ANEG_STATE_AN_ENABLE;
1099                         }
1100                 } else if (ap->ability_match != 0 &&
1101                            ap->rxconfig == 0) {
1102                         ap->state = ANEG_STATE_AN_ENABLE;
1103                 }
1104                 break;
1105
1106         case ANEG_STATE_COMPLETE_ACK_INIT:
1107                 if (ap->rxconfig & ANEG_CFG_INVAL) {
1108                         ret = ANEG_FAILED;
1109                         break;
1110                 }
1111                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
1112                                MR_LP_ADV_HALF_DUPLEX |
1113                                MR_LP_ADV_SYM_PAUSE |
1114                                MR_LP_ADV_ASYM_PAUSE |
1115                                MR_LP_ADV_REMOTE_FAULT1 |
1116                                MR_LP_ADV_REMOTE_FAULT2 |
1117                                MR_LP_ADV_NEXT_PAGE |
1118                                MR_TOGGLE_RX |
1119                                MR_NP_RX);
1120                 if (ap->rxconfig & ANEG_CFG_FD)
1121                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
1122                 if (ap->rxconfig & ANEG_CFG_HD)
1123                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
1124                 if (ap->rxconfig & ANEG_CFG_PS1)
1125                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
1126                 if (ap->rxconfig & ANEG_CFG_PS2)
1127                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
1128                 if (ap->rxconfig & ANEG_CFG_RF1)
1129                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
1130                 if (ap->rxconfig & ANEG_CFG_RF2)
1131                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
1132                 if (ap->rxconfig & ANEG_CFG_NP)
1133                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
1134
1135                 ap->link_time = ap->cur_time;
1136
1137                 ap->flags ^= (MR_TOGGLE_TX);
1138                 if (ap->rxconfig & 0x0008)
1139                         ap->flags |= MR_TOGGLE_RX;
1140                 if (ap->rxconfig & ANEG_CFG_NP)
1141                         ap->flags |= MR_NP_RX;
1142                 ap->flags |= MR_PAGE_RX;
1143
1144                 ap->state = ANEG_STATE_COMPLETE_ACK;
1145                 ret = ANEG_TIMER_ENAB;
1146                 break;
1147
1148         case ANEG_STATE_COMPLETE_ACK:
1149                 if (ap->ability_match != 0 &&
1150                     ap->rxconfig == 0) {
1151                         ap->state = ANEG_STATE_AN_ENABLE;
1152                         break;
1153                 }
1154                 delta = ap->cur_time - ap->link_time;
1155                 if (delta > ANEG_STATE_SETTLE_TIME) {
1156                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
1157                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
1158                         } else {
1159                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
1160                                     !(ap->flags & MR_NP_RX)) {
1161                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
1162                                 } else {
1163                                         ret = ANEG_FAILED;
1164                                 }
1165                         }
1166                 }
1167                 break;
1168
1169         case ANEG_STATE_IDLE_DETECT_INIT:
1170                 ap->link_time = ap->cur_time;
1171                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
1172                 tw32_carefully(MAC_MODE, tp->mac_mode);
1173
1174                 ap->state = ANEG_STATE_IDLE_DETECT;
1175                 ret = ANEG_TIMER_ENAB;
1176                 break;
1177
1178         case ANEG_STATE_IDLE_DETECT:
1179                 if (ap->ability_match != 0 &&
1180                     ap->rxconfig == 0) {
1181                         ap->state = ANEG_STATE_AN_ENABLE;
1182                         break;
1183                 }
1184                 delta = ap->cur_time - ap->link_time;
1185                 if (delta > ANEG_STATE_SETTLE_TIME) {
1186                         /* XXX another gem from the Broadcom driver :( */
1187                         ap->state = ANEG_STATE_LINK_OK;
1188                 }
1189                 break;
1190
1191         case ANEG_STATE_LINK_OK:
1192                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
1193                 ret = ANEG_DONE;
1194                 break;
1195
1196         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
1197                 /* ??? unimplemented */
1198                 break;
1199
1200         case ANEG_STATE_NEXT_PAGE_WAIT:
1201                 /* ??? unimplemented */
1202                 break;
1203
1204         default:
1205                 ret = ANEG_FAILED;
1206                 break;
1207         };
1208
1209         return ret;
1210 }
1211
1212 static int tg3_setup_fiber_phy(struct tg3 *tp)
1213 {
1214         uint32_t orig_pause_cfg;
1215         uint16_t orig_active_speed;
1216         uint8_t orig_active_duplex;
1217         int current_link_up;
1218         int i;
1219
1220         orig_pause_cfg =
1221                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
1222                                   TG3_FLAG_TX_PAUSE));
1223         orig_active_speed = tp->link_config.active_speed;
1224         orig_active_duplex = tp->link_config.active_duplex;
1225
1226         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
1227         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
1228         tw32_carefully(MAC_MODE, tp->mac_mode);
1229
1230         /* Reset when initting first time or we have a link. */
1231         if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) ||
1232             (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED)) {
1233                 /* Set PLL lock range. */
1234                 tg3_writephy(tp, 0x16, 0x8007);
1235
1236                 /* SW reset */
1237                 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
1238
1239                 /* Wait for reset to complete. */
1240                 mdelay(5);
1241
1242                 /* Config mode; select PMA/Ch 1 regs. */
1243                 tg3_writephy(tp, 0x10, 0x8411);
1244
1245                 /* Enable auto-lock and comdet, select txclk for tx. */
1246                 tg3_writephy(tp, 0x11, 0x0a10);
1247
1248                 tg3_writephy(tp, 0x18, 0x00a0);
1249                 tg3_writephy(tp, 0x16, 0x41ff);
1250
1251                 /* Assert and deassert POR. */
1252                 tg3_writephy(tp, 0x13, 0x0400);
1253                 udelay(40);
1254                 tg3_writephy(tp, 0x13, 0x0000);
1255
1256                 tg3_writephy(tp, 0x11, 0x0a50);
1257                 udelay(40);
1258                 tg3_writephy(tp, 0x11, 0x0a10);
1259
1260                 /* Wait for signal to stabilize */
1261                 mdelay(150);
1262
1263                 /* Deselect the channel register so we can read the PHYID
1264                  * later.
1265                  */
1266                 tg3_writephy(tp, 0x10, 0x8011);
1267         }
1268
1269         /* Disable link change interrupt.  */
1270         tw32_carefully(MAC_EVENT, 0);
1271
1272         current_link_up = 0;
1273         if (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) {
1274                 if (!(tp->tg3_flags & TG3_FLAG_GOT_SERDES_FLOWCTL)) {
1275                         struct tg3_fiber_aneginfo aninfo;
1276                         int status = ANEG_FAILED;
1277                         unsigned int tick;
1278                         uint32_t tmp;
1279
1280                         memset(&aninfo, 0, sizeof(aninfo));
1281                         aninfo.flags |= (MR_AN_ENABLE);
1282
1283                         tw32(MAC_TX_AUTO_NEG, 0);
1284
1285                         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
1286                         tw32_carefully(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
1287
1288                         tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
1289
1290                         aninfo.state = ANEG_STATE_UNKNOWN;
1291                         aninfo.cur_time = 0;
1292                         tick = 0;
1293                         while (++tick < 195000) {
1294                                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
1295                                 if (status == ANEG_DONE ||
1296                                     status == ANEG_FAILED)
1297                                         break;
1298
1299                                 udelay(1);
1300                         }
1301
1302                         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
1303                         tw32_carefully(MAC_MODE, tp->mac_mode);
1304
1305                         if (status == ANEG_DONE &&
1306                             (aninfo.flags &
1307                              (MR_AN_COMPLETE | MR_LINK_OK |
1308                               MR_LP_ADV_FULL_DUPLEX))) {
1309                                 uint32_t local_adv, remote_adv;
1310
1311                                 local_adv = ADVERTISE_PAUSE_CAP;
1312                                 remote_adv = 0;
1313                                 if (aninfo.flags & MR_LP_ADV_SYM_PAUSE)
1314                                         remote_adv |= LPA_PAUSE_CAP;
1315                                 if (aninfo.flags & MR_LP_ADV_ASYM_PAUSE)
1316                                         remote_adv |= LPA_PAUSE_ASYM;
1317
1318                                 tg3_setup_flow_control(tp, local_adv, remote_adv);
1319
1320                                 tp->tg3_flags |=
1321                                         TG3_FLAG_GOT_SERDES_FLOWCTL;
1322                                 current_link_up = 1;
1323                         }
1324                         for (i = 0; i < 60; i++) {
1325                                 udelay(20);
1326                                 tw32_carefully(MAC_STATUS,
1327                                         (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED));
1328                                 if ((tr32(MAC_STATUS) &
1329                                      (MAC_STATUS_SYNC_CHANGED |
1330                                       MAC_STATUS_CFG_CHANGED)) == 0)
1331                                         break;
1332                         }
1333                         if (current_link_up == 0 &&
1334                             (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED)) {
1335                                 current_link_up = 1;
1336                         }
1337                 } else {
1338                         /* Forcing 1000FD link up. */
1339                         current_link_up = 1;
1340                 }
1341         }
1342
1343         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1344         tw32_carefully(MAC_MODE, tp->mac_mode);
1345
1346         tp->hw_status->status =
1347                 (SD_STATUS_UPDATED |
1348                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
1349
1350         for (i = 0; i < 100; i++) {
1351                 udelay(20);
1352                 tw32_carefully(MAC_STATUS,
1353                         (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED));
1354                 if ((tr32(MAC_STATUS) &
1355                      (MAC_STATUS_SYNC_CHANGED |
1356                       MAC_STATUS_CFG_CHANGED)) == 0)
1357                         break;
1358         }
1359
1360         if ((tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) == 0)
1361                 current_link_up = 0;
1362
1363         if (current_link_up == 1) {
1364                 tp->link_config.active_speed = SPEED_1000;
1365                 tp->link_config.active_duplex = DUPLEX_FULL;
1366         } else {
1367                 tp->link_config.active_speed = SPEED_INVALID;
1368                 tp->link_config.active_duplex = DUPLEX_INVALID;
1369         }
1370
1371         if (current_link_up != tp->carrier_ok) {
1372                 tp->carrier_ok = current_link_up;
1373                 tg3_link_report(tp);
1374         } else {
1375                 uint32_t now_pause_cfg =
1376                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
1377                                          TG3_FLAG_TX_PAUSE);
1378                 if (orig_pause_cfg != now_pause_cfg ||
1379                     orig_active_speed != tp->link_config.active_speed ||
1380                     orig_active_duplex != tp->link_config.active_duplex)
1381                         tg3_link_report(tp);
1382         }
1383
1384         if ((tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) == 0) {
1385                 tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_LINK_POLARITY);
1386                 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
1387                         tw32_carefully(MAC_MODE, tp->mac_mode);
1388                 }
1389         }
1390
1391         return 0;
1392 }
1393 #else
1394 #define tg3_setup_fiber_phy(TP) (-EINVAL)
1395 #endif /* SUPPORT_FIBER_PHY */
1396
1397 static int tg3_setup_phy(struct tg3 *tp)
1398 {
1399         int err;
1400
1401         if (tp->phy_id == PHY_ID_SERDES) {
1402                 err = tg3_setup_fiber_phy(tp);
1403         } else {
1404                 err = tg3_setup_copper_phy(tp);
1405         }
1406
1407         if (tp->link_config.active_speed == SPEED_1000 &&
1408             tp->link_config.active_duplex == DUPLEX_HALF)
1409                 tw32(MAC_TX_LENGTHS,
1410                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1411                       (6 << TX_LENGTHS_IPG_SHIFT) |
1412                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1413         else
1414                 tw32(MAC_TX_LENGTHS,
1415                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1416                       (6 << TX_LENGTHS_IPG_SHIFT) |
1417                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1418
1419         return err;
1420 }
1421
1422
1423 #define MAX_WAIT_CNT 1000
1424
1425 /* To stop a block, clear the enable bit and poll till it
1426  * clears.  
1427  */
1428 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, uint32_t enable_bit)
1429 {
1430         unsigned int i;
1431         uint32_t val;
1432
1433         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1434                 switch(ofs) {
1435                 case RCVLSC_MODE:
1436                 case DMAC_MODE:
1437                 case MBFREE_MODE:
1438                 case BUFMGR_MODE:
1439                 case MEMARB_MODE:
1440                         /* We can't enable/disable these bits of the
1441                          * 5705, just say success.
1442                          */
1443                         return 0;
1444                 default:
1445                         break;
1446                 }
1447         }
1448         val = tr32(ofs);
1449         val &= ~enable_bit;
1450         tw32(ofs, val);
1451         tr32(ofs);
1452
1453         for (i = 0; i < MAX_WAIT_CNT; i++) {
1454                 udelay(100);
1455                 val = tr32(ofs);
1456                 if ((val & enable_bit) == 0)
1457                         break;
1458         }
1459
1460         if (i == MAX_WAIT_CNT) {
1461                 printf("tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
1462                        ofs, enable_bit);
1463                 return -ENODEV;
1464         }
1465
1466         return 0;
1467 }
1468
1469 static int tg3_abort_hw(struct tg3 *tp)
1470 {
1471         int i, err;
1472
1473         tg3_disable_ints(tp);
1474
1475         tp->rx_mode &= ~RX_MODE_ENABLE;
1476         tw32_carefully(MAC_RX_MODE, tp->rx_mode);
1477
1478         err  = tg3_stop_block(tp, RCVBDI_MODE,   RCVBDI_MODE_ENABLE);
1479         err |= tg3_stop_block(tp, RCVLPC_MODE,   RCVLPC_MODE_ENABLE);
1480         err |= tg3_stop_block(tp, RCVLSC_MODE,   RCVLSC_MODE_ENABLE);
1481         err |= tg3_stop_block(tp, RCVDBDI_MODE,  RCVDBDI_MODE_ENABLE);
1482         err |= tg3_stop_block(tp, RCVDCC_MODE,   RCVDCC_MODE_ENABLE);
1483         err |= tg3_stop_block(tp, RCVCC_MODE,    RCVCC_MODE_ENABLE);
1484
1485         err |= tg3_stop_block(tp, SNDBDS_MODE,   SNDBDS_MODE_ENABLE);
1486         err |= tg3_stop_block(tp, SNDBDI_MODE,   SNDBDI_MODE_ENABLE);
1487         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1488         err |= tg3_stop_block(tp, RDMAC_MODE,    RDMAC_MODE_ENABLE);
1489         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
1490         err |= tg3_stop_block(tp, SNDBDC_MODE,   SNDBDC_MODE_ENABLE);
1491         if (err)
1492                 goto out;
1493
1494         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
1495         tw32_carefully(MAC_MODE, tp->mac_mode);
1496
1497         tp->tx_mode &= ~TX_MODE_ENABLE;
1498         tw32_carefully(MAC_TX_MODE, tp->tx_mode);
1499
1500         for (i = 0; i < MAX_WAIT_CNT; i++) {
1501                 udelay(100);
1502                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
1503                         break;
1504         }
1505         if (i >= MAX_WAIT_CNT) {
1506                 printf("tg3_abort_hw timed out TX_MODE_ENABLE will not clear MAC_TX_MODE=%x\n",
1507                         tr32(MAC_TX_MODE));
1508                 return -ENODEV;
1509         }
1510
1511         err  = tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE);
1512         err |= tg3_stop_block(tp, WDMAC_MODE,  WDMAC_MODE_ENABLE);
1513         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE);
1514
1515         tw32(FTQ_RESET, 0xffffffff);
1516         tw32(FTQ_RESET, 0x00000000);
1517
1518         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE);
1519         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE);
1520         if (err)
1521                 goto out;
1522
1523         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
1524
1525 out:
1526         return err;
1527 }
1528
1529 static void tg3_chip_reset(struct tg3 *tp)
1530 {
1531         uint32_t val;
1532
1533         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_5704)) {
1534                 /* Force NVRAM to settle.
1535                  * This deals with a chip bug which can result in EEPROM
1536                  * corruption.
1537                  */
1538                 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
1539                         int i;
1540         
1541                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
1542                         for (i = 0; i < 100000; i++) {
1543                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
1544                                         break;
1545                                 udelay(10);
1546                         }
1547                 }
1548         }
1549         /* In Etherboot we don't need to worry about the 5701
1550          * REG_WRITE_BUG because we do all register writes indirectly.
1551          */
1552
1553         // Alf: here patched
1554         /* do the reset */
1555         val = GRC_MISC_CFG_CORECLK_RESET;
1556         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
1557             || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1558                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
1559         }
1560
1561         // Alf : Please VALIDATE THIS.
1562         // It is necessary in my case (5751) to prevent a reboot, but
1563         // I have no idea about a side effect on any other version.
1564         // It appears to be what's done in tigon3.c from Broadcom
1565         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
1566           tw32(GRC_MISC_CFG, 0x20000000) ;
1567           val |= 0x20000000 ;
1568         }
1569
1570         tw32(GRC_MISC_CFG, val);
1571
1572         /* Flush PCI posted writes.  The normal MMIO registers
1573          * are inaccessible at this time so this is the only
1574          * way to make this reliably.  I tried to use indirect
1575          * register read/write but this upset some 5701 variants.
1576          */
1577         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
1578
1579         udelay(120);
1580
1581         /* Re-enable indirect register accesses. */
1582         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
1583                                tp->misc_host_ctrl);
1584
1585         /* Set MAX PCI retry to zero. */
1586         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
1587         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
1588             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
1589                 val |= PCISTATE_RETRY_SAME_DMA;
1590         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
1591
1592         pci_restore_state(tp->pdev, tp->pci_cfg_state);
1593
1594         /* Make sure PCI-X relaxed ordering bit is clear. */
1595         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
1596         val &= ~PCIX_CAPS_RELAXED_ORDERING;
1597         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
1598
1599         tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
1600
1601         if (((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0) &&
1602                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
1603                 tp->pci_clock_ctrl |=
1604                         (CLOCK_CTRL_FORCE_CLKRUN | CLOCK_CTRL_CLKRUN_OENABLE);
1605                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
1606         }
1607
1608         tw32(TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
1609 }
1610
1611 static void tg3_stop_fw(struct tg3 *tp)
1612 {
1613         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
1614                 uint32_t val;
1615                 int i;
1616
1617                 tg3_write_mem(NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1618                 val = tr32(GRC_RX_CPU_EVENT);
1619                 val |= (1 << 14);
1620                 tw32(GRC_RX_CPU_EVENT, val);
1621
1622                 /* Wait for RX cpu to ACK the event.  */
1623                 for (i = 0; i < 100; i++) {
1624                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
1625                                 break;
1626                         udelay(1);
1627                 }
1628         }
1629 }
1630
1631 static int tg3_restart_fw(struct tg3 *tp, uint32_t state)
1632 {
1633         uint32_t val;
1634         int i;
1635         
1636         tg3_write_mem(NIC_SRAM_FIRMWARE_MBOX, 
1637                 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1638         /* Wait for firmware initialization to complete. */
1639         for (i = 0; i < 100000; i++) {
1640                 tg3_read_mem(NIC_SRAM_FIRMWARE_MBOX, &val);
1641                 if (val == (uint32_t) ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1642                         break;
1643                 udelay(10);
1644         }
1645         if (i >= 100000 &&
1646                     !(tp->tg3_flags2 & TG3_FLG2_SUN_5704)) {
1647                 printf("Firmware will not restart magic=%x\n",
1648                         val);
1649                 return -ENODEV;
1650         }
1651         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1652           state = DRV_STATE_SUSPEND;
1653         }
1654
1655         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
1656             (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)) {
1657           // Enable PCIE bug fix
1658           tg3_read_mem(0x7c00, &val);
1659           tg3_write_mem(0x7c00, val | 0x02000000);
1660         }
1661         tg3_write_mem(NIC_SRAM_FW_DRV_STATE_MBOX, state);
1662         return 0;
1663 }
1664
1665 static int tg3_halt(struct tg3 *tp)
1666 {
1667         tg3_stop_fw(tp);
1668         tg3_abort_hw(tp);
1669         tg3_chip_reset(tp);
1670         return tg3_restart_fw(tp, DRV_STATE_UNLOAD);
1671 }
1672
1673 static void __tg3_set_mac_addr(struct tg3 *tp)
1674 {
1675         uint32_t addr_high, addr_low;
1676         int i;
1677
1678         addr_high = ((tp->nic->node_addr[0] << 8) |
1679                      tp->nic->node_addr[1]);
1680         addr_low = ((tp->nic->node_addr[2] << 24) |
1681                     (tp->nic->node_addr[3] << 16) |
1682                     (tp->nic->node_addr[4] <<  8) |
1683                     (tp->nic->node_addr[5] <<  0));
1684         for (i = 0; i < 4; i++) {
1685                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
1686                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
1687         }
1688
1689         if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
1690                 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
1691                 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705)) {
1692                 for(i = 0; i < 12; i++) {
1693                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
1694                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
1695                 }
1696         }
1697         addr_high = (tp->nic->node_addr[0] +
1698                      tp->nic->node_addr[1] +
1699                      tp->nic->node_addr[2] +
1700                      tp->nic->node_addr[3] +
1701                      tp->nic->node_addr[4] +
1702                      tp->nic->node_addr[5]) &
1703                 TX_BACKOFF_SEED_MASK;
1704         tw32(MAC_TX_BACKOFF_SEED, addr_high);
1705 }
1706
1707 static void tg3_set_bdinfo(struct tg3 *tp, uint32_t bdinfo_addr,
1708                            dma_addr_t mapping, uint32_t maxlen_flags,
1709                            uint32_t nic_addr)
1710 {
1711         tg3_write_mem((bdinfo_addr +
1712                        TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
1713                       ((uint64_t) mapping >> 32));
1714         tg3_write_mem((bdinfo_addr +
1715                        TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
1716                       ((uint64_t) mapping & 0xffffffff));
1717         tg3_write_mem((bdinfo_addr +
1718                        TG3_BDINFO_MAXLEN_FLAGS),
1719                        maxlen_flags);
1720         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1721                 tg3_write_mem((bdinfo_addr + TG3_BDINFO_NIC_ADDR), nic_addr);
1722         }
1723 }
1724
1725
1726 static void tg3_init_rings(struct tg3 *tp)
1727 {
1728         unsigned i;
1729
1730         /* Zero out the tg3 variables */
1731         memset(&tg3_bss, 0, sizeof(tg3_bss));
1732         tp->rx_std    = &tg3_bss.rx_std[0];
1733         tp->rx_rcb    = &tg3_bss.rx_rcb[0];
1734         tp->tx_ring   = &tg3_bss.tx_ring[0];
1735         tp->hw_status = &tg3_bss.hw_status;
1736         tp->hw_stats  = &tg3_bss.hw_stats;
1737         tp->mac_mode  = 0;
1738
1739
1740         /* Initialize tx/rx rings for packet processing.
1741          *
1742          * The chip has been shut down and the driver detached from
1743          * the networking, so no interrupts or new tx packets will
1744          * end up in the driver.
1745          */
1746
1747         /* Initialize invariants of the rings, we only set this
1748          * stuff once.  This works because the card does not
1749          * write into the rx buffer posting rings.
1750          */
1751         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
1752                 struct tg3_rx_buffer_desc *rxd;
1753
1754                 rxd = &tp->rx_std[i];
1755                 rxd->idx_len = (RX_PKT_BUF_SZ - 2 - 64) << RXD_LEN_SHIFT;
1756                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
1757                 rxd->opaque = (RXD_OPAQUE_RING_STD | (i << RXD_OPAQUE_INDEX_SHIFT));
1758
1759                 /* Note where the receive buffer for the ring is placed */
1760                 rxd->addr_hi = 0;
1761                 rxd->addr_lo = virt_to_bus(
1762                         &tg3_bss.rx_bufs[i%TG3_DEF_RX_RING_PENDING][2]);
1763         }
1764 }
1765
1766 #define TG3_WRITE_SETTINGS(TABLE) \
1767 do { \
1768         const uint32_t *_table, *_end; \
1769         _table = TABLE; \
1770         _end = _table + sizeof(TABLE)/sizeof(TABLE[0]);  \
1771         for(; _table < _end; _table += 2) { \
1772                 tw32(_table[0], _table[1]); \
1773         } \
1774 } while(0)
1775
1776
1777 /* initialize/reset the tg3 */
1778 static int tg3_setup_hw(struct tg3 *tp)
1779 {
1780         uint32_t val, rdmac_mode;
1781         int i, err, limit;
1782
1783         /* Simply don't support setups with extremly buggy firmware in etherboot */
1784         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
1785                 printf("Error 5701_A0 firmware bug detected\n");
1786                 return -EINVAL;
1787         }
1788
1789         tg3_disable_ints(tp);
1790
1791         /* Originally this was all in tg3_init_hw */
1792
1793         /* Force the chip into D0. */
1794         tg3_set_power_state_0(tp);
1795
1796         tg3_switch_clocks(tp);
1797
1798         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
1799
1800         // This should go somewhere else
1801 #define T3_PCIE_CAPABILITY_ID_REG           0xD0
1802 #define T3_PCIE_CAPABILITY_ID               0x10
1803 #define T3_PCIE_CAPABILITY_REG              0xD2
1804
1805         /* Originally this was all in tg3_reset_hw */
1806
1807         tg3_stop_fw(tp);
1808
1809         /* No need to call tg3_abort_hw here, it is called before tg3_setup_hw. */
1810
1811         tg3_chip_reset(tp);
1812
1813         tw32(GRC_MODE, tp->grc_mode);  /* Redundant? */
1814
1815         err = tg3_restart_fw(tp, DRV_STATE_START);
1816         if (err)
1817                 return err;
1818
1819         if (tp->phy_id == PHY_ID_SERDES) {
1820                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
1821         }
1822         tw32_carefully(MAC_MODE, tp->mac_mode);
1823
1824
1825         /* This works around an issue with Athlon chipsets on
1826          * B3 tigon3 silicon.  This bit has no effect on any
1827          * other revision.
1828          * Alf: Except 5750 ! (which reboots)
1829          */
1830
1831         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
1832           tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
1833         tw32_carefully(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
1834
1835         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
1836             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
1837                 val = tr32(TG3PCI_PCISTATE);
1838                 val |= PCISTATE_RETRY_SAME_DMA;
1839                 tw32(TG3PCI_PCISTATE, val);
1840         }
1841
1842         /* Descriptor ring init may make accesses to the
1843          * NIC SRAM area to setup the TX descriptors, so we
1844          * can only do this after the hardware has been
1845          * successfully reset.
1846          */
1847         tg3_init_rings(tp);
1848
1849         /* Clear statistics/status block in chip */
1850         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1851                 for (i = NIC_SRAM_STATS_BLK;
1852                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
1853                      i += sizeof(uint32_t)) {
1854                         tg3_write_mem(i, 0);
1855                         udelay(40);
1856                 }
1857         }
1858
1859         /* This value is determined during the probe time DMA
1860          * engine test, tg3_setup_dma.
1861          */
1862         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
1863
1864         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
1865                           GRC_MODE_4X_NIC_SEND_RINGS |
1866                           GRC_MODE_NO_TX_PHDR_CSUM |
1867                           GRC_MODE_NO_RX_PHDR_CSUM);
1868         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
1869         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1870         tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
1871
1872         tw32(GRC_MODE,
1873                 tp->grc_mode | 
1874                 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
1875
1876         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
1877         tw32(GRC_MISC_CFG,
1878              (65 << GRC_MISC_CFG_PRESCALAR_SHIFT));
1879
1880         /* Initialize MBUF/DESC pool. */
1881         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1882                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
1883                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
1884                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
1885                 else
1886                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
1887                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
1888                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
1889         }
1890         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)) {
1891                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
1892                      tp->bufmgr_config.mbuf_read_dma_low_water);
1893                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
1894                      tp->bufmgr_config.mbuf_mac_rx_low_water);
1895                 tw32(BUFMGR_MB_HIGH_WATER,
1896                      tp->bufmgr_config.mbuf_high_water);
1897         } else {
1898                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
1899                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
1900                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
1901                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
1902                 tw32(BUFMGR_MB_HIGH_WATER,
1903                      tp->bufmgr_config.mbuf_high_water_jumbo);
1904         }
1905         tw32(BUFMGR_DMA_LOW_WATER,
1906              tp->bufmgr_config.dma_low_water);
1907         tw32(BUFMGR_DMA_HIGH_WATER,
1908              tp->bufmgr_config.dma_high_water);
1909
1910         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
1911         for (i = 0; i < 2000; i++) {
1912                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
1913                         break;
1914                 udelay(10);
1915         }
1916         if (i >= 2000) {
1917                 printf("tg3_setup_hw cannot enable BUFMGR\n");
1918                 return -ENODEV;
1919         }
1920
1921         tw32(FTQ_RESET, 0xffffffff);
1922         tw32(FTQ_RESET, 0x00000000);
1923         for (i = 0; i < 2000; i++) {
1924                 if (tr32(FTQ_RESET) == 0x00000000)
1925                         break;
1926                 udelay(10);
1927         }
1928         if (i >= 2000) {
1929                 printf("tg3_setup_hw cannot reset FTQ\n");
1930                 return -ENODEV;
1931         }
1932
1933         /* Initialize TG3_BDINFO's at:
1934          *  RCVDBDI_STD_BD:     standard eth size rx ring
1935          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
1936          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
1937          *
1938          * like so:
1939          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
1940          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
1941          *                              ring attribute flags
1942          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
1943          *
1944          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
1945          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
1946          *
1947          * ??? No space allocated for mini receive ring? :(
1948          *
1949          * The size of each ring is fixed in the firmware, but the location is
1950          * configurable.
1951          */
1952         {
1953                 static const uint32_t table_all[] = {
1954                         /* Setup replenish thresholds. */
1955                         RCVBDI_STD_THRESH, TG3_DEF_RX_RING_PENDING / 8,
1956
1957                         /* Etherboot lives below 4GB */
1958                         RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, 0,
1959                         RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, NIC_SRAM_RX_BUFFER_DESC,
1960                 };
1961                 static const uint32_t table_not_5705[] = {
1962                         /* Buffer maximum length */
1963                         RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT,
1964                         
1965                         /* Disable the mini frame rx ring */
1966                         RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,      BDINFO_FLAGS_DISABLED,
1967                         
1968                         /* Disable the jumbo frame rx ring */
1969                         RCVBDI_JUMBO_THRESH, 0,
1970                         RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, BDINFO_FLAGS_DISABLED,
1971                         
1972                         
1973                 };
1974                 TG3_WRITE_SETTINGS(table_all);
1975                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, 
1976                         virt_to_bus(tp->rx_std));
1977                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1978                         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
1979                                 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
1980                 } else {
1981                         TG3_WRITE_SETTINGS(table_not_5705);
1982                 }
1983         }
1984
1985         
1986         /* There is only one send ring on 5705, no need to explicitly
1987          * disable the others.
1988          */
1989         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1990                 /* Clear out send RCB ring in SRAM. */
1991                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
1992                         tg3_write_mem(i + TG3_BDINFO_MAXLEN_FLAGS, BDINFO_FLAGS_DISABLED);
1993         }
1994
1995         tp->tx_prod = 0;
1996         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
1997         tw32_mailbox2(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
1998
1999         tg3_set_bdinfo(tp,
2000                 NIC_SRAM_SEND_RCB,
2001                 virt_to_bus(tp->tx_ring),
2002                 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
2003                 NIC_SRAM_TX_BUFFER_DESC);
2004
2005         /* There is only one receive return ring on 5705, no need to explicitly
2006          * disable the others.
2007          */
2008         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
2009                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK; i += TG3_BDINFO_SIZE) {
2010                         tg3_write_mem(i + TG3_BDINFO_MAXLEN_FLAGS,
2011                                 BDINFO_FLAGS_DISABLED);
2012                 }
2013         }
2014
2015         tp->rx_rcb_ptr = 0;
2016         tw32_mailbox2(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
2017
2018         tg3_set_bdinfo(tp,
2019                 NIC_SRAM_RCV_RET_RCB,
2020                 virt_to_bus(tp->rx_rcb),
2021                 (TG3_RX_RCB_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
2022                 0);
2023
2024         tp->rx_std_ptr = TG3_DEF_RX_RING_PENDING;
2025         tw32_mailbox2(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
2026                      tp->rx_std_ptr);
2027
2028         tw32_mailbox2(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW, 0);
2029
2030         /* Initialize MAC address and backoff seed. */
2031         __tg3_set_mac_addr(tp);
2032
2033         /* Calculate RDMAC_MODE setting early, we need it to determine
2034          * the RCVLPC_STATE_ENABLE mask.
2035          */
2036         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
2037                 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
2038                 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
2039                 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
2040                 RDMAC_MODE_LNGREAD_ENAB);
2041         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
2042                 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
2043         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2044                 if (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
2045                         if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
2046                                 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
2047                                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
2048                         }
2049                 }
2050         }
2051
2052         /* Setup host coalescing engine. */
2053         tw32(HOSTCC_MODE, 0);
2054         for (i = 0; i < 2000; i++) {
2055                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
2056                         break;
2057                 udelay(10);
2058         }
2059
2060         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
2061                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
2062         tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
2063
2064         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
2065         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
2066                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
2067                                        GRC_LCLCTRL_GPIO_OUTPUT1);
2068         tw32_carefully(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
2069
2070         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
2071         tr32(MAILBOX_INTERRUPT_0);
2072
2073         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
2074                 tw32_carefully(DMAC_MODE, DMAC_MODE_ENABLE);
2075         }
2076
2077         val = ( WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
2078                 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
2079                 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
2080                 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
2081                 WDMAC_MODE_LNGREAD_ENAB);
2082         if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) &&
2083                 ((tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) != 0) &&
2084                 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
2085                 val |= WDMAC_MODE_RX_ACCEL;
2086         }
2087         tw32_carefully(WDMAC_MODE, val);
2088
2089         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
2090                 val = tr32(TG3PCI_X_CAPS);
2091                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
2092                         val &= PCIX_CAPS_BURST_MASK;
2093                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
2094                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2095                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
2096                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
2097                         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
2098                                 val |= (tp->split_mode_max_reqs <<
2099                                         PCIX_CAPS_SPLIT_SHIFT);
2100                 }
2101                 tw32(TG3PCI_X_CAPS, val);
2102         }
2103
2104         tw32_carefully(RDMAC_MODE, rdmac_mode);
2105         {
2106                 static const uint32_t table_all[] = {
2107                         /* MTU + ethernet header + FCS + optional VLAN tag */
2108                         MAC_RX_MTU_SIZE, ETH_MAX_MTU + ETH_HLEN + 8,
2109                         
2110                         /* The slot time is changed by tg3_setup_phy if we
2111                          * run at gigabit with half duplex.
2112                          */
2113                         MAC_TX_LENGTHS, 
2114                         (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2115                         (6 << TX_LENGTHS_IPG_SHIFT) |
2116                         (32 << TX_LENGTHS_SLOT_TIME_SHIFT),
2117                         
2118                         /* Receive rules. */
2119                         MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS,
2120                         RCVLPC_CONFIG, 0x0181,
2121                         
2122                         /* Receive/send statistics. */
2123                         RCVLPC_STATS_ENABLE, 0xffffff,
2124                         RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE,
2125                         SNDDATAI_STATSENAB, 0xffffff,
2126                         SNDDATAI_STATSCTRL, (SNDDATAI_SCTRL_ENABLE |SNDDATAI_SCTRL_FASTUPD),
2127                         
2128                         /* Host coalescing engine */
2129                         HOSTCC_RXCOL_TICKS, 0,
2130                         HOSTCC_TXCOL_TICKS, LOW_TXCOL_TICKS,
2131                         HOSTCC_RXMAX_FRAMES, 1,
2132                         HOSTCC_TXMAX_FRAMES, LOW_RXMAX_FRAMES,
2133                         HOSTCC_RXCOAL_MAXF_INT, 1,
2134                         HOSTCC_TXCOAL_MAXF_INT, 0,
2135                         
2136                         /* Status/statistics block address. */
2137                         /* Etherboot lives below 4GB, so HIGH == 0 */
2138                         HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, 0,
2139
2140                         /* No need to enable 32byte coalesce mode. */
2141                         HOSTCC_MODE, HOSTCC_MODE_ENABLE | 0,
2142                         
2143                         RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE,
2144                         RCVLPC_MODE, RCVLPC_MODE_ENABLE,
2145                         
2146                         RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE,
2147
2148                         SNDDATAC_MODE, SNDDATAC_MODE_ENABLE,
2149                         SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE,
2150                         RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB,
2151                         RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ,
2152                         SNDDATAI_MODE, SNDDATAI_MODE_ENABLE,
2153                         SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE,
2154                         SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE,
2155                         
2156                         /* Accept all multicast frames. */
2157                         MAC_HASH_REG_0, 0xffffffff,
2158                         MAC_HASH_REG_1, 0xffffffff,
2159                         MAC_HASH_REG_2, 0xffffffff,
2160                         MAC_HASH_REG_3, 0xffffffff,
2161                 };
2162                 static const uint32_t table_not_5705[] = {
2163                         /* Host coalescing engine */
2164                         HOSTCC_RXCOAL_TICK_INT, 0,
2165                         HOSTCC_TXCOAL_TICK_INT, 0,
2166
2167                         /* Status/statistics block address. */
2168                         /* Etherboot lives below 4GB, so HIGH == 0 */
2169                         HOSTCC_STAT_COAL_TICKS, DEFAULT_STAT_COAL_TICKS,
2170                         HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, 0,
2171                         HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK,
2172                         HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK,
2173
2174                         RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE,
2175
2176                         MBFREE_MODE, MBFREE_MODE_ENABLE,
2177                 };
2178                 TG3_WRITE_SETTINGS(table_all);
2179                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
2180                         virt_to_bus(tp->hw_stats));
2181                 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
2182                         virt_to_bus(tp->hw_status));
2183                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
2184                         TG3_WRITE_SETTINGS(table_not_5705);
2185                 }
2186         }
2187
2188         tp->tx_mode = TX_MODE_ENABLE;
2189         tw32_carefully(MAC_TX_MODE, tp->tx_mode);
2190
2191         tp->rx_mode = RX_MODE_ENABLE;
2192         tw32_carefully(MAC_RX_MODE, tp->rx_mode);
2193
2194         tp->mi_mode = MAC_MI_MODE_BASE;
2195         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
2196
2197         tw32(MAC_LED_CTRL, 0);
2198         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2199         if (tp->phy_id == PHY_ID_SERDES) {
2200                 tw32_carefully(MAC_RX_MODE, RX_MODE_RESET);
2201         }
2202         tp->rx_mode |= RX_MODE_KEEP_VLAN_TAG; /* drop tagged vlan packets */
2203         tw32_carefully(MAC_RX_MODE, tp->rx_mode);
2204
2205         if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
2206                 tw32(MAC_SERDES_CFG, 0x616000);
2207
2208         /* Prevent chip from dropping frames when flow control
2209          * is enabled.
2210          */
2211         tw32(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
2212         tr32(MAC_LOW_WMARK_MAX_RX_FRAME);
2213
2214         err = tg3_setup_phy(tp);
2215
2216         /* Ignore CRC stats */
2217
2218         /* Initialize receive rules. */
2219         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
2220         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
2221         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
2222         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
2223
2224         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
2225             || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750))
2226                 limit = 8;
2227         else
2228                 limit = 16;
2229         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
2230                 limit -= 4;
2231         switch (limit) {
2232         case 16:        tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
2233         case 15:        tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
2234         case 14:        tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
2235         case 13:        tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
2236         case 12:        tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
2237         case 11:        tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
2238         case 10:        tw32(MAC_RCV_RULE_9,  0);  tw32(MAC_RCV_VALUE_9,  0);
2239         case 9:         tw32(MAC_RCV_RULE_8,  0);  tw32(MAC_RCV_VALUE_8,  0);
2240         case 8:         tw32(MAC_RCV_RULE_7,  0);  tw32(MAC_RCV_VALUE_7,  0);
2241         case 7:         tw32(MAC_RCV_RULE_6,  0);  tw32(MAC_RCV_VALUE_6,  0);
2242         case 6:         tw32(MAC_RCV_RULE_5,  0);  tw32(MAC_RCV_VALUE_5,  0);
2243         case 5:         tw32(MAC_RCV_RULE_4,  0);  tw32(MAC_RCV_VALUE_4,  0);
2244         case 4:         /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
2245         case 3:         /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
2246         case 2:
2247         case 1:
2248         default:
2249                 break;
2250         };
2251
2252         return err;
2253 }
2254
2255
2256
2257 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
2258 static void tg3_nvram_init(struct tg3 *tp)
2259 {
2260         tw32(GRC_EEPROM_ADDR,
2261              (EEPROM_ADDR_FSM_RESET |
2262               (EEPROM_DEFAULT_CLOCK_PERIOD <<
2263                EEPROM_ADDR_CLKPERD_SHIFT)));
2264
2265         mdelay(1);
2266
2267         /* Enable seeprom accesses. */
2268         tw32_carefully(GRC_LOCAL_CTRL,
2269                 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
2270
2271         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2272             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2273                 uint32_t nvcfg1 = tr32(NVRAM_CFG1);
2274
2275                 tp->tg3_flags |= TG3_FLAG_NVRAM;
2276                 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
2277                         if (nvcfg1 & NVRAM_CFG1_BUFFERED_MODE)
2278                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
2279                 } else {
2280                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
2281                         tw32(NVRAM_CFG1, nvcfg1);
2282                 }
2283
2284         } else {
2285                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
2286         }
2287 }
2288
2289
2290 static int tg3_nvram_read_using_eeprom(
2291         struct tg3 *tp __unused, uint32_t offset, uint32_t *val)
2292 {
2293         uint32_t tmp;
2294         int i;
2295
2296         if (offset > EEPROM_ADDR_ADDR_MASK ||
2297                 (offset % 4) != 0) {
2298                 return -EINVAL;
2299         }
2300
2301         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2302                                         EEPROM_ADDR_DEVID_MASK |
2303                                         EEPROM_ADDR_READ);
2304         tw32(GRC_EEPROM_ADDR,
2305              tmp |
2306              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2307              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2308               EEPROM_ADDR_ADDR_MASK) |
2309              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2310
2311         for (i = 0; i < 10000; i++) {
2312                 tmp = tr32(GRC_EEPROM_ADDR);
2313
2314                 if (tmp & EEPROM_ADDR_COMPLETE)
2315                         break;
2316                 udelay(100);
2317         }
2318         if (!(tmp & EEPROM_ADDR_COMPLETE)) {
2319                 return -EBUSY;
2320         }
2321
2322         *val = tr32(GRC_EEPROM_DATA);
2323         return 0;
2324 }
2325
2326 static int tg3_nvram_read(struct tg3 *tp, uint32_t offset, uint32_t *val)
2327 {
2328         int i, saw_done_clear;
2329
2330         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2331                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2332
2333         if (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED)
2334                 offset = ((offset / NVRAM_BUFFERED_PAGE_SIZE) <<
2335                           NVRAM_BUFFERED_PAGE_POS) +
2336                         (offset % NVRAM_BUFFERED_PAGE_SIZE);
2337
2338         if (offset > NVRAM_ADDR_MSK)
2339                 return -EINVAL;
2340
2341         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2342         for (i = 0; i < 1000; i++) {
2343                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2344                         break;
2345                 udelay(20);
2346         }
2347
2348         tw32(NVRAM_ADDR, offset);
2349         tw32(NVRAM_CMD,
2350              NVRAM_CMD_RD | NVRAM_CMD_GO |
2351              NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2352
2353         /* Wait for done bit to clear then set again. */
2354         saw_done_clear = 0;
2355         for (i = 0; i < 1000; i++) {
2356                 udelay(10);
2357                 if (!saw_done_clear &&
2358                     !(tr32(NVRAM_CMD) & NVRAM_CMD_DONE))
2359                         saw_done_clear = 1;
2360                 else if (saw_done_clear &&
2361                          (tr32(NVRAM_CMD) & NVRAM_CMD_DONE))
2362                         break;
2363         }
2364         if (i >= 1000) {
2365                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2366                 return -EBUSY;
2367         }
2368
2369         *val = bswap_32(tr32(NVRAM_RDDATA));
2370         tw32(NVRAM_SWARB, 0x20);
2371
2372         return 0;
2373 }
2374
2375 struct subsys_tbl_ent {
2376         uint16_t subsys_vendor, subsys_devid;
2377         uint32_t phy_id;
2378 };
2379
2380 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
2381         /* Broadcom boards. */
2382         { 0x14e4, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
2383         { 0x14e4, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
2384         { 0x14e4, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
2385         { 0x14e4, 0x0003, PHY_ID_SERDES  }, /* BCM95700A9 */
2386         { 0x14e4, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
2387         { 0x14e4, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
2388         { 0x14e4, 0x0007, PHY_ID_SERDES  }, /* BCM95701A7 */
2389         { 0x14e4, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
2390         { 0x14e4, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
2391         { 0x14e4, 0x0009, PHY_ID_BCM5701 }, /* BCM95703Ax1 */
2392         { 0x14e4, 0x8009, PHY_ID_BCM5701 }, /* BCM95703Ax2 */
2393
2394         /* 3com boards. */
2395         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
2396         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
2397         /* { PCI_VENDOR_ID_3COM, 0x1002, PHY_ID_XXX },     3C996CT */
2398         /* { PCI_VENDOR_ID_3COM, 0x1003, PHY_ID_XXX },     3C997T */
2399         { PCI_VENDOR_ID_3COM, 0x1004, PHY_ID_SERDES  }, /* 3C996SX */
2400         /* { PCI_VENDOR_ID_3COM, 0x1005, PHY_ID_XXX },     3C997SZ */
2401         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
2402         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
2403
2404         /* DELL boards. */
2405         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
2406         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
2407         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
2408         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
2409         { PCI_VENDOR_ID_DELL, 0x0179, PHY_ID_BCM5751 }, /* EtherXpress */
2410         
2411         /* Fujitsu Siemens Computer */
2412         { PCI_VENDOR_ID_FSC, 0x105d, PHY_ID_BCM5751 }, /* Futro C200 */ 
2413
2414         /* Compaq boards. */
2415         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
2416         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
2417         { PCI_VENDOR_ID_COMPAQ, 0x007d, PHY_ID_SERDES  }, /* CHANGELING */
2418         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
2419         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }  /* NC7780_2 */
2420 };
2421
2422 static int tg3_phy_probe(struct tg3 *tp)
2423 {
2424         uint32_t eeprom_phy_id, hw_phy_id_1, hw_phy_id_2;
2425         uint32_t hw_phy_id, hw_phy_id_masked;
2426         enum phy_led_mode eeprom_led_mode;
2427         uint32_t val;
2428         unsigned i;
2429         int eeprom_signature_found, err;
2430
2431         tp->phy_id = PHY_ID_INVALID;
2432
2433         for (i = 0; i < sizeof(subsys_id_to_phy_id)/sizeof(subsys_id_to_phy_id[0]); i++) {
2434                 if ((subsys_id_to_phy_id[i].subsys_vendor == tp->subsystem_vendor) &&
2435                         (subsys_id_to_phy_id[i].subsys_devid == tp->subsystem_device)) {
2436                         tp->phy_id = subsys_id_to_phy_id[i].phy_id;
2437                         break;
2438                 }
2439         }
2440
2441         eeprom_phy_id = PHY_ID_INVALID;
2442         eeprom_led_mode = led_mode_auto;
2443         eeprom_signature_found = 0;
2444         tg3_read_mem(NIC_SRAM_DATA_SIG, &val);
2445         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
2446                 uint32_t nic_cfg;
2447
2448                 tg3_read_mem(NIC_SRAM_DATA_CFG, &nic_cfg);
2449                 tp->nic_sram_data_cfg = nic_cfg;
2450
2451                 eeprom_signature_found = 1;
2452
2453                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
2454                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) {
2455                         eeprom_phy_id = PHY_ID_SERDES;
2456                 } else {
2457                         uint32_t nic_phy_id;
2458
2459                         tg3_read_mem(NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
2460                         if (nic_phy_id != 0) {
2461                                 uint32_t id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
2462                                 uint32_t id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
2463
2464                                 eeprom_phy_id  = (id1 >> 16) << 10;
2465                                 eeprom_phy_id |= (id2 & 0xfc00) << 16;
2466                                 eeprom_phy_id |= (id2 & 0x03ff) <<  0;
2467                         }
2468                 }
2469
2470                 switch (nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK) {
2471                 case NIC_SRAM_DATA_CFG_LED_TRIPLE_SPD:
2472                         eeprom_led_mode = led_mode_three_link;
2473                         break;
2474
2475                 case NIC_SRAM_DATA_CFG_LED_LINK_SPD:
2476                         eeprom_led_mode = led_mode_link10;
2477                         break;
2478
2479                 default:
2480                         eeprom_led_mode = led_mode_auto;
2481                         break;
2482                 };
2483                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
2484                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
2485                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) &&
2486                         (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP)) {
2487                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
2488                 }
2489
2490                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE)
2491                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
2492                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
2493                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
2494         }
2495
2496         /* Now read the physical PHY_ID from the chip and verify
2497          * that it is sane.  If it doesn't look good, we fall back
2498          * to either the hard-coded table based PHY_ID and failing
2499          * that the value found in the eeprom area.
2500          */
2501         err  = tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
2502         err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
2503
2504         hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
2505         hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
2506         hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
2507
2508         hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
2509
2510         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
2511                 tp->phy_id = hw_phy_id;
2512         } else {
2513                 /* phy_id currently holds the value found in the
2514                  * subsys_id_to_phy_id[] table or PHY_ID_INVALID
2515                  * if a match was not found there.
2516                  */
2517                 if (tp->phy_id == PHY_ID_INVALID) {
2518                         if (!eeprom_signature_found ||
2519                             !KNOWN_PHY_ID(eeprom_phy_id & PHY_ID_MASK))
2520                                 return -ENODEV;
2521                         tp->phy_id = eeprom_phy_id;
2522                 }
2523         }
2524
2525         err = tg3_phy_reset(tp);
2526         if (err)
2527                 return err;
2528
2529         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2530             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2531                 uint32_t mii_tg3_ctrl;
2532                 
2533                 /* These chips, when reset, only advertise 10Mb
2534                  * capabilities.  Fix that.
2535                  */
2536                 err  = tg3_writephy(tp, MII_ADVERTISE,
2537                                     (ADVERTISE_CSMA |
2538                                      ADVERTISE_PAUSE_CAP |
2539                                      ADVERTISE_10HALF |
2540                                      ADVERTISE_10FULL |
2541                                      ADVERTISE_100HALF |
2542                                      ADVERTISE_100FULL));
2543                 mii_tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
2544                                 MII_TG3_CTRL_ADV_1000_FULL |
2545                                 MII_TG3_CTRL_AS_MASTER |
2546                                 MII_TG3_CTRL_ENABLE_AS_MASTER);
2547                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2548                         mii_tg3_ctrl = 0;
2549
2550                 err |= tg3_writephy(tp, MII_TG3_CTRL, mii_tg3_ctrl);
2551                 err |= tg3_writephy(tp, MII_BMCR,
2552                                     (BMCR_ANRESTART | BMCR_ANENABLE));
2553         }
2554
2555         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
2556                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2557                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2558                 tg3_writedsp(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
2559         }
2560
2561         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2562                 tg3_writephy(tp, 0x1c, 0x8d68);
2563                 tg3_writephy(tp, 0x1c, 0x8d68);
2564         }
2565
2566         /* Enable Ethernet@WireSpeed */
2567         tg3_phy_set_wirespeed(tp);
2568
2569         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
2570                 err = tg3_init_5401phy_dsp(tp);
2571         }
2572
2573         /* Determine the PHY led mode. 
2574          * Be careful if this gets set wrong it can result in an inability to 
2575          * establish a link.
2576          */
2577         if (tp->phy_id == PHY_ID_SERDES) {
2578                 tp->led_mode = led_mode_three_link;
2579         }
2580         else if (tp->subsystem_vendor == PCI_VENDOR_ID_DELL) {
2581                 tp->led_mode = led_mode_link10;
2582         } else {
2583                 tp->led_mode = led_mode_three_link;
2584                 if (eeprom_signature_found &&
2585                     eeprom_led_mode != led_mode_auto)
2586                         tp->led_mode = eeprom_led_mode;
2587         }
2588
2589         if (tp->phy_id == PHY_ID_SERDES)
2590                 tp->link_config.advertising =
2591                         (ADVERTISED_1000baseT_Half |
2592                          ADVERTISED_1000baseT_Full |
2593                          ADVERTISED_Autoneg |
2594                          ADVERTISED_FIBRE);
2595         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2596                 tp->link_config.advertising &=
2597                         ~(ADVERTISED_1000baseT_Half |
2598                           ADVERTISED_1000baseT_Full);
2599
2600         return err;
2601 }
2602
2603 #if SUPPORT_PARTNO_STR
2604 static void tg3_read_partno(struct tg3 *tp)
2605 {
2606         unsigned char vpd_data[256];
2607         int i;
2608
2609         for (i = 0; i < 256; i += 4) {
2610                 uint32_t tmp;
2611
2612                 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
2613                         goto out_not_found;
2614
2615                 vpd_data[i + 0] = ((tmp >>  0) & 0xff);
2616                 vpd_data[i + 1] = ((tmp >>  8) & 0xff);
2617                 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
2618                 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
2619         }
2620
2621         /* Now parse and find the part number. */
2622         for (i = 0; i < 256; ) {
2623                 unsigned char val = vpd_data[i];
2624                 int block_end;
2625
2626                 if (val == 0x82 || val == 0x91) {
2627                         i = (i + 3 +
2628                              (vpd_data[i + 1] +
2629                               (vpd_data[i + 2] << 8)));
2630                         continue;
2631                 }
2632
2633                 if (val != 0x90)
2634                         goto out_not_found;
2635
2636                 block_end = (i + 3 +
2637                              (vpd_data[i + 1] +
2638                               (vpd_data[i + 2] << 8)));
2639                 i += 3;
2640                 while (i < block_end) {
2641                         if (vpd_data[i + 0] == 'P' &&
2642                             vpd_data[i + 1] == 'N') {
2643                                 int partno_len = vpd_data[i + 2];
2644
2645                                 if (partno_len > 24)
2646                                         goto out_not_found;
2647
2648                                 memcpy(tp->board_part_number,
2649                                        &vpd_data[i + 3],
2650                                        partno_len);
2651
2652                                 /* Success. */
2653                                 return;
2654                         }
2655                 }
2656
2657                 /* Part number not found. */
2658                 goto out_not_found;
2659         }
2660
2661 out_not_found:
2662         memcpy(tp->board_part_number, "none", sizeof("none"));
2663 }
2664 #else
2665 #define tg3_read_partno(TP) ((TP)->board_part_number[0] = '\0')
2666 #endif
2667
2668 static int tg3_get_invariants(struct tg3 *tp)
2669 {
2670         uint32_t misc_ctrl_reg;
2671         uint32_t pci_state_reg, grc_misc_cfg;
2672         uint16_t pci_cmd;
2673         uint8_t  pci_latency;
2674         uint32_t val ;
2675         int err;
2676
2677         /* Read the subsystem vendor and device ids */
2678         pci_read_config_word(tp->pdev, PCI_SUBSYSTEM_VENDOR_ID, &tp->subsystem_vendor);
2679         pci_read_config_word(tp->pdev, PCI_SUBSYSTEM_ID, &tp->subsystem_device);
2680
2681         /* The sun_5704 code needs infrastructure etherboot does have
2682          * ignore it for now.
2683          */
2684
2685         /* If we have an AMD 762 or Intel ICH/ICH0 chipset, write
2686          * reordering to the mailbox registers done by the host
2687          * controller can cause major troubles.  We read back from
2688          * every mailbox register write to force the writes to be
2689          * posted to the chip in order.
2690          *
2691          * TG3_FLAG_MBOX_WRITE_REORDER has been forced on.
2692          */
2693
2694         /* Force memory write invalidate off.  If we leave it on,
2695          * then on 5700_BX chips we have to enable a workaround.
2696          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundry
2697          * to match the cacheline size.  The Broadcom driver have this
2698          * workaround but turns MWI off all the times so never uses
2699          * it.  This seems to suggest that the workaround is insufficient.
2700          */
2701         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
2702         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
2703         /* Also, force SERR#/PERR# in PCI command. */
2704         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
2705         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
2706
2707         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
2708          * has the register indirect write enable bit set before
2709          * we try to access any of the MMIO registers.  It is also
2710          * critical that the PCI-X hw workaround situation is decided
2711          * before that as well.
2712          */
2713         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, &misc_ctrl_reg);
2714
2715         tp->pci_chip_rev_id = (misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT);
2716
2717         /* Initialize misc host control in PCI block. */
2718         tp->misc_host_ctrl |= (misc_ctrl_reg &
2719                                MISC_HOST_CTRL_CHIPREV);
2720         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
2721                                tp->misc_host_ctrl);
2722
2723         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, &pci_latency);
2724         if (pci_latency < 64) {
2725                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, 64);
2726         }
2727
2728         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &pci_state_reg);
2729
2730         /* If this is a 5700 BX chipset, and we are in PCI-X
2731          * mode, enable register write workaround.
2732          *
2733          * The workaround is to use indirect register accesses
2734          * for all chip writes not to mailbox registers.
2735          *
2736          * In etherboot to simplify things we just always use this work around.
2737          */
2738         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
2739                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
2740         }
2741         /* Back to back register writes can cause problems on the 5701,
2742          * the workaround is to read back all reg writes except those to
2743          * mailbox regs.
2744          * In etherboot we always use indirect register accesses so
2745          * we don't see this.
2746          */
2747
2748         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
2749                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
2750         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
2751                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
2752
2753         /* Chip-specific fixup from Broadcom driver */
2754         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
2755             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
2756                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
2757                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
2758         }
2759
2760         /* determine if it is PCIE system */
2761         // Alf : I have no idea what this is about...
2762         // But it's definitely usefull
2763         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
2764           val = tr32(TG3PCI_MSI_CAP_ID) ;
2765           if (((val >> 8) & 0xff) == T3_PCIE_CAPABILITY_ID_REG) {
2766             val = tr32(T3_PCIE_CAPABILITY_ID_REG) ;
2767             if ((val & 0xff) == T3_PCIE_CAPABILITY_ID) {
2768               tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS ;
2769             }
2770           }
2771         }
2772
2773         /* Force the chip into D0. */
2774         tg3_set_power_state_0(tp);
2775
2776         /* Etherboot does not ask the tg3 to do checksums */
2777         /* Etherboot does not ask the tg3 to do jumbo frames */
2778         /* Ehterboot does not ask the tg3 to use WakeOnLan. */
2779
2780         /* A few boards don't want Ethernet@WireSpeed phy feature */
2781         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
2782             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
2783                 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2784                         (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
2785                         (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1))) {
2786                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
2787         }
2788
2789         /* Avoid tagged irq status etherboot does not use irqs */
2790
2791         /* Only 5701 and later support tagged irq status mode.
2792          * Also, 5788 chips cannot use tagged irq status.
2793          *
2794          * However, since etherboot does not use irqs avoid tagged irqs
2795          * status  because the interrupt condition is more difficult to
2796          * fully clear in that mode.
2797          */
2798         
2799         /* Since some 5700_AX && 5700_BX have problems with 32BYTE
2800          * coalesce_mode, and the rest work fine anything set.
2801          * Don't enable HOST_CC_MODE_32BYTE in etherboot.
2802          */
2803
2804         /* Initialize MAC MI mode, polling disabled. */
2805         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
2806
2807         /* Initialize data/descriptor byte/word swapping. */
2808         tw32(GRC_MODE, tp->grc_mode);
2809
2810         tg3_switch_clocks(tp);
2811
2812         /* Clear this out for sanity. */
2813         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
2814
2815         /* Etherboot does not need to check if the PCIX_TARGET_HWBUG
2816          * is needed.  It always uses it.
2817          */
2818         
2819         udelay(50);
2820         tg3_nvram_init(tp);
2821
2822         /* The TX descriptors will reside in main memory.
2823          */
2824
2825         /* See which board we are using.
2826          */
2827         grc_misc_cfg = tr32(GRC_MISC_CFG);
2828         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
2829
2830         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
2831             grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
2832                 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
2833                 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
2834         }
2835
2836         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
2837             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
2838              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
2839                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
2840
2841 #define PCI_DEVICE_ID_TIGON3_5901       0x170d
2842 #define PCI_DEVICE_ID_TIGON3_5901_2     0x170e
2843
2844         /* these are limited to 10/100 only */
2845         if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) &&
2846                     ((grc_misc_cfg == 0x8000) || (grc_misc_cfg == 0x4000))) ||
2847                 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2848                         (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM) &&
2849                         ((tp->pdev->dev_id == PCI_DEVICE_ID_TIGON3_5901) ||
2850                                 (tp->pdev->dev_id == PCI_DEVICE_ID_TIGON3_5901_2)))) {
2851                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
2852         }
2853
2854         err = tg3_phy_probe(tp);
2855         if (err) {
2856                 printf("phy probe failed, err %d\n", err);
2857         }
2858
2859         tg3_read_partno(tp);
2860
2861
2862         /* 5700 BX chips need to have their TX producer index mailboxes
2863          * written twice to workaround a bug.
2864          * In etherboot we do this unconditionally to simplify things.
2865          */
2866
2867         /* 5700 chips can get confused if TX buffers straddle the
2868          * 4GB address boundary in some cases.
2869          * 
2870          * In etherboot we can ignore the problem as etherboot lives below 4GB.
2871          */
2872
2873         /* In etherboot wake-on-lan is unconditionally disabled */
2874         return err;
2875 }
2876
2877 static int  tg3_get_device_address(struct tg3 *tp)
2878 {
2879         struct nic *nic = tp->nic;
2880         uint32_t hi, lo, mac_offset;
2881
2882         if (PCI_FUNC(tp->pdev->devfn) == 0)
2883                 mac_offset = 0x7c;
2884         else
2885                 mac_offset = 0xcc;
2886
2887         /* First try to get it from MAC address mailbox. */
2888         tg3_read_mem(NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
2889         if ((hi >> 16) == 0x484b) {
2890                 nic->node_addr[0] = (hi >>  8) & 0xff;
2891                 nic->node_addr[1] = (hi >>  0) & 0xff;
2892
2893                 tg3_read_mem(NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
2894                 nic->node_addr[2] = (lo >> 24) & 0xff;
2895                 nic->node_addr[3] = (lo >> 16) & 0xff;
2896                 nic->node_addr[4] = (lo >>  8) & 0xff;
2897                 nic->node_addr[5] = (lo >>  0) & 0xff;
2898         }
2899         /* Next, try NVRAM. */
2900         else if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
2901                  !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
2902                 nic->node_addr[0] = ((hi >> 16) & 0xff);
2903                 nic->node_addr[1] = ((hi >> 24) & 0xff);
2904                 nic->node_addr[2] = ((lo >>  0) & 0xff);
2905                 nic->node_addr[3] = ((lo >>  8) & 0xff);
2906                 nic->node_addr[4] = ((lo >> 16) & 0xff);
2907                 nic->node_addr[5] = ((lo >> 24) & 0xff);
2908         }
2909         /* Finally just fetch it out of the MAC control regs. */
2910         else {
2911                 hi = tr32(MAC_ADDR_0_HIGH);
2912                 lo = tr32(MAC_ADDR_0_LOW);
2913
2914                 nic->node_addr[5] = lo & 0xff;
2915                 nic->node_addr[4] = (lo >> 8) & 0xff;
2916                 nic->node_addr[3] = (lo >> 16) & 0xff;
2917                 nic->node_addr[2] = (lo >> 24) & 0xff;
2918                 nic->node_addr[1] = hi & 0xff;
2919                 nic->node_addr[0] = (hi >> 8) & 0xff;
2920         }
2921
2922         return 0;
2923 }
2924
2925
2926 static int tg3_setup_dma(struct tg3 *tp)
2927 {
2928         tw32(TG3PCI_CLOCK_CTRL, 0);
2929
2930         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) == 0) {
2931                 tp->dma_rwctrl =
2932                         (0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
2933                         (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
2934                         (0x7 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
2935                         (0x7 << DMA_RWCTRL_READ_WATER_SHIFT) |
2936                         (0x0f << DMA_RWCTRL_MIN_DMA_SHIFT);
2937                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2938                         tp->dma_rwctrl &= ~(DMA_RWCTRL_MIN_DMA << DMA_RWCTRL_MIN_DMA_SHIFT);
2939                 }
2940         } else {
2941                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
2942                         tp->dma_rwctrl =
2943                                 (0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
2944                                 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
2945                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
2946                                 (0x7 << DMA_RWCTRL_READ_WATER_SHIFT) |
2947                                 (0x00 << DMA_RWCTRL_MIN_DMA_SHIFT);
2948                 else
2949                         tp->dma_rwctrl =
2950                                 (0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
2951                                 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
2952                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
2953                                 (0x3 << DMA_RWCTRL_READ_WATER_SHIFT) |
2954                                 (0x0f << DMA_RWCTRL_MIN_DMA_SHIFT);
2955
2956                 /* Wheee, some more chip bugs... */
2957                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
2958                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)) {
2959                         uint32_t ccval = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
2960
2961                         if ((ccval == 0x6) || (ccval == 0x7)) {
2962                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
2963                         }
2964                 }
2965         }
2966
2967         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
2968                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)) {
2969                 tp->dma_rwctrl &= ~(DMA_RWCTRL_MIN_DMA << DMA_RWCTRL_MIN_DMA_SHIFT);
2970         }
2971
2972         /*
2973           Alf : Tried that, but it does not work. Should be this way though :-(
2974         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
2975           tp->dma_rwctrl |= 0x001f0000;
2976         }
2977         */
2978         tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
2979
2980         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
2981
2982         return 0;
2983 }
2984
2985 static void tg3_init_link_config(struct tg3 *tp)
2986 {
2987         tp->link_config.advertising =
2988                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2989                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2990                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
2991                  ADVERTISED_Autoneg | ADVERTISED_MII);
2992         tp->carrier_ok = 0;
2993         tp->link_config.active_speed = SPEED_INVALID;
2994         tp->link_config.active_duplex = DUPLEX_INVALID;
2995 }
2996
2997
2998 #if SUPPORT_PHY_STR
2999 static const char * tg3_phy_string(struct tg3 *tp)
3000 {
3001         switch (tp->phy_id & PHY_ID_MASK) {
3002         case PHY_ID_BCM5400:    return "5400";
3003         case PHY_ID_BCM5401:    return "5401";
3004         case PHY_ID_BCM5411:    return "5411";
3005         case PHY_ID_BCM5701:    return "5701";
3006         case PHY_ID_BCM5703:    return "5703";
3007         case PHY_ID_BCM5704:    return "5704";
3008         case PHY_ID_BCM5705:    return "5705";
3009         case PHY_ID_BCM5750:    return "5750";
3010         case PHY_ID_BCM5751:    return "5751"; 
3011         case PHY_ID_BCM8002:    return "8002/serdes";
3012         case PHY_ID_SERDES:     return "serdes";
3013         default:                return "unknown";
3014         };
3015 }
3016 #else
3017 #define tg3_phy_string(TP) "?"
3018 #endif
3019
3020
3021 static void tg3_poll_link(struct tg3 *tp)
3022 {
3023         uint32_t mac_stat;
3024
3025         mac_stat = tr32(MAC_STATUS);
3026         if (tp->phy_id == PHY_ID_SERDES) {
3027                 if (tp->carrier_ok?
3028                         (mac_stat & MAC_STATUS_LNKSTATE_CHANGED):
3029                         (mac_stat & MAC_STATUS_PCS_SYNCED)) {
3030                         tw32_carefully(MAC_MODE, tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK);
3031                         tw32_carefully(MAC_MODE, tp->mac_mode);
3032
3033                         tg3_setup_phy(tp);
3034                 }
3035         }
3036         else {
3037                 if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) {
3038                         tg3_setup_phy(tp);
3039                 }
3040         }
3041 }
3042
3043 /**************************************************************************
3044 POLL - Wait for a frame
3045 ***************************************************************************/
3046 static void tg3_ack_irqs(struct tg3 *tp)
3047 {
3048         if (tp->hw_status->status & SD_STATUS_UPDATED) {
3049                 /*
3050                  * writing any value to intr-mbox-0 clears PCI INTA# and
3051                  * chip-internal interrupt pending events.
3052                  * writing non-zero to intr-mbox-0 additional tells the
3053                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3054                  * event coalescing.
3055                  */
3056                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 
3057                         0x00000001);
3058                 /*
3059                  * Flush PCI write.  This also guarantees that our
3060                  * status block has been flushed to host memory.
3061                  */
3062                 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
3063                 tp->hw_status->status &= ~SD_STATUS_UPDATED;
3064         }
3065 }
3066
3067 static int tg3_poll(struct nic *nic, int retrieve)
3068 {
3069         /* return true if there's an ethernet packet ready to read */
3070         /* nic->packet should contain data on return */
3071         /* nic->packetlen should contain length of data */
3072
3073         struct tg3 *tp = &tg3;
3074         int result;
3075
3076         result = 0;
3077
3078         if ( (tp->hw_status->idx[0].rx_producer != tp->rx_rcb_ptr) && !retrieve ) 
3079           return 1;
3080
3081         tg3_ack_irqs(tp);
3082
3083         if (tp->hw_status->idx[0].rx_producer != tp->rx_rcb_ptr) {
3084                 struct tg3_rx_buffer_desc *desc;
3085                 unsigned int len;
3086                 desc = &tp->rx_rcb[tp->rx_rcb_ptr];
3087                 if ((desc->opaque & RXD_OPAQUE_RING_MASK) == RXD_OPAQUE_RING_STD) {
3088                         len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3089                         
3090                         nic->packetlen = len;
3091                         memcpy(nic->packet, bus_to_virt(desc->addr_lo), len);
3092                         result = 1;
3093                 }
3094                 tp->rx_rcb_ptr = (tp->rx_rcb_ptr + 1) % TG3_RX_RCB_RING_SIZE;
3095                 
3096                 /* ACK the status ring */
3097                 tw32_mailbox2(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, tp->rx_rcb_ptr);
3098
3099                 /* Refill RX ring. */
3100                 if (result) {
3101                         tp->rx_std_ptr = (tp->rx_std_ptr + 1) % TG3_RX_RING_SIZE;
3102                         tw32_mailbox2(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW, tp->rx_std_ptr);
3103                 }
3104         }
3105         tg3_poll_link(tp);
3106         return result;
3107 }
3108
3109 /**************************************************************************
3110 TRANSMIT - Transmit a frame
3111 ***************************************************************************/
3112 #if 0
3113 static void tg3_set_txd(struct tg3 *tp, int entry,
3114         dma_addr_t mapping, int len, uint32_t flags,
3115         uint32_t mss_and_is_end)
3116 {
3117         struct tg3_tx_buffer_desc *txd =  &tp->tx_ring[entry];
3118         int is_end = (mss_and_is_end & 0x1);
3119         if (is_end) {
3120                 flags |= TXD_FLAG_END;
3121         }
3122
3123         txd->addr_hi   = 0;
3124         txd->addr_lo   = mapping & 0xffffffff;
3125         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3126         txd->vlan_tag  = 0 << TXD_VLAN_TAG_SHIFT;
3127 }
3128 #endif
3129
3130 static void tg3_transmit(struct nic *nic, const char *dst_addr,
3131         unsigned int type, unsigned int size, const char *packet)
3132 {
3133         static struct eth_frame {
3134                 uint8_t  dst_addr[ETH_ALEN];
3135                 uint8_t  src_addr[ETH_ALEN];
3136                 uint16_t type;
3137                 uint8_t  data [ETH_FRAME_LEN - ETH_HLEN];
3138         } frame[2];
3139         static int frame_idx;
3140         
3141         /* send the packet to destination */
3142         struct tg3_tx_buffer_desc *txd;
3143         struct tg3 *tp;
3144         uint32_t entry;
3145         int i;
3146
3147         /* Wait until there is a free packet frame */
3148         tp = &tg3;
3149         i = 0;
3150         entry = tp->tx_prod;
3151         while((tp->hw_status->idx[0].tx_consumer != entry) &&
3152                 (tp->hw_status->idx[0].tx_consumer != PREV_TX(entry))) {
3153                 mdelay(10);     /* give the nick a chance */
3154                 poll_interruptions();
3155                 if (++i > 500) { /* timeout 5s for transmit */
3156                         printf("transmit timed out\n");
3157                         tg3_halt(tp);
3158                         tg3_setup_hw(tp);
3159                         return;
3160                 }
3161         }
3162         if (i != 0) {
3163                 printf("#");
3164         }
3165         
3166         /* Copy the packet to the our local buffer */
3167         memcpy(&frame[frame_idx].dst_addr, dst_addr, ETH_ALEN);
3168         memcpy(&frame[frame_idx].src_addr, nic->node_addr, ETH_ALEN);
3169         frame[frame_idx].type = htons(type);
3170         memset(&frame[frame_idx].data, 0, sizeof(frame[frame_idx].data));
3171         memcpy(&frame[frame_idx].data, packet, size);
3172
3173         /* Setup the ring buffer entry to transmit */
3174         txd            = &tp->tx_ring[entry];
3175         txd->addr_hi   = 0; /* Etherboot runs under 4GB */
3176         txd->addr_lo   = virt_to_bus(&frame[frame_idx]);
3177         txd->len_flags = ((size + ETH_HLEN) << TXD_LEN_SHIFT) | TXD_FLAG_END;
3178         txd->vlan_tag  = 0 << TXD_VLAN_TAG_SHIFT;
3179
3180         /* Advance to the next entry */
3181         entry = NEXT_TX(entry);
3182         frame_idx ^= 1;
3183
3184         /* Packets are ready, update Tx producer idx local and on card */
3185         tw32_mailbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3186         tw32_mailbox2((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3187         tp->tx_prod = entry;
3188 }
3189
3190 /**************************************************************************
3191 DISABLE - Turn off ethernet interface
3192 ***************************************************************************/
3193 static void tg3_disable(struct dev *dev __unused)
3194 {
3195         struct tg3 *tp = &tg3;
3196         /* put the card in its initial state */
3197         /* This function serves 3 purposes.
3198          * This disables DMA and interrupts so we don't receive
3199          *  unexpected packets or interrupts from the card after
3200          *  etherboot has finished. 
3201          * This frees resources so etherboot may use
3202          *  this driver on another interface
3203          * This allows etherboot to reinitialize the interface
3204          *  if something is something goes wrong.
3205          */
3206         tg3_halt(tp);
3207         tp->tg3_flags &= ~(TG3_FLAG_INIT_COMPLETE|TG3_FLAG_GOT_SERDES_FLOWCTL);
3208         tp->carrier_ok = 0;
3209         iounmap((void *)tp->regs);
3210 }
3211
3212 /**************************************************************************
3213 IRQ - Enable, Disable, or Force interrupts
3214 ***************************************************************************/
3215 static void tg3_irq(struct nic *nic __unused, irq_action_t action __unused)
3216 {
3217   switch ( action ) {
3218   case DISABLE :
3219     break;
3220   case ENABLE :
3221     break;
3222   case FORCE :
3223     break;
3224   }
3225 }
3226
3227 /**************************************************************************
3228 PROBE - Look for an adapter, this routine's visible to the outside
3229 You should omit the last argument struct pci_device * for a non-PCI NIC
3230 ***************************************************************************/
3231 static int tg3_probe(struct dev *dev, struct pci_device *pdev)
3232 {
3233         struct nic *nic = (struct nic *)dev;
3234         struct tg3 *tp = &tg3;
3235         unsigned long tg3reg_base, tg3reg_len;
3236         int i, err, pm_cap;
3237
3238         if (pdev == 0)
3239                 return 0;
3240
3241         memset(tp, 0, sizeof(*tp));
3242
3243         adjust_pci_device(pdev);
3244
3245         nic->irqno  = 0;
3246         nic->ioaddr = pdev->ioaddr & ~3;
3247
3248         /* Find power-management capability. */
3249         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3250         if (pm_cap == 0) {
3251                 printf("Cannot find PowerManagement capability, aborting.\n");
3252                 return 0;
3253         }
3254         tg3reg_base = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
3255         if (tg3reg_base == -1UL) {
3256                 printf("Unuseable bar\n");
3257                 return 0;
3258         }
3259         tg3reg_len  = pci_bar_size(pdev,  PCI_BASE_ADDRESS_0);
3260
3261         tp->pdev       = pdev;
3262         tp->nic        = nic;
3263         tp->pm_cap     = pm_cap;
3264         tp->rx_mode    = 0;
3265         tp->tx_mode    = 0;
3266         tp->mi_mode    = MAC_MI_MODE_BASE;
3267         tp->tg3_flags  = 0 & ~TG3_FLAG_INIT_COMPLETE; 
3268         
3269         /* The word/byte swap controls here control register access byte
3270          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
3271          * setting below.
3272          */
3273         tp->misc_host_ctrl =
3274                 MISC_HOST_CTRL_MASK_PCI_INT |
3275                 MISC_HOST_CTRL_WORD_SWAP |
3276                 MISC_HOST_CTRL_INDIR_ACCESS |
3277                 MISC_HOST_CTRL_PCISTATE_RW;
3278
3279         /* The NONFRM (non-frame) byte/word swap controls take effect
3280          * on descriptor entries, anything which isn't packet data.
3281          *
3282          * The StrongARM chips on the board (one for tx, one for rx)
3283          * are running in big-endian mode.
3284          */
3285         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
3286                         GRC_MODE_WSWAP_NONFRM_DATA);
3287 #if __BYTE_ORDER == __BIG_ENDIAN
3288         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
3289 #endif
3290         tp->regs = (unsigned long) ioremap(tg3reg_base, tg3reg_len);
3291         if (tp->regs == 0UL) {
3292                 printf("Cannot map device registers, aborting\n");
3293                 return 0;
3294         }
3295
3296         tg3_init_link_config(tp);
3297
3298         err = tg3_get_invariants(tp);
3299         if (err) {
3300                 printf("Problem fetching invariants of chip, aborting.\n");
3301                 goto err_out_iounmap;
3302         }
3303
3304         err = tg3_get_device_address(tp);
3305         if (err) {
3306                 printf("Could not obtain valid ethernet address, aborting.\n");
3307                 goto err_out_iounmap;
3308         }
3309         printf("Ethernet addr: %!\n", nic->node_addr);
3310
3311         tg3_setup_dma(tp);
3312
3313         /* Now that we have fully setup the chip, save away a snapshot
3314          * of the PCI config space.  We need to restore this after
3315          * GRC_MISC_CFG core clock resets and some resume events.
3316          */
3317         pci_save_state(tp->pdev, tp->pci_cfg_state);
3318
3319         printf("Tigon3 [partno(%s) rev %hx PHY(%s)] (PCI%s:%s:%s)\n",
3320                 tp->board_part_number,
3321                 tp->pci_chip_rev_id,
3322                 tg3_phy_string(tp),
3323                 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "X" : ""),
3324                 ((tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) ?
3325                         ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "133MHz" : "66MHz") :
3326                         ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "100MHz" : "33MHz")),
3327                 ((tp->tg3_flags & TG3_FLAG_PCI_32BIT) ? "32-bit" : "64-bit"));
3328
3329
3330         err = tg3_setup_hw(tp); 
3331         if (err) {
3332                 goto err_out_disable;
3333         } 
3334         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
3335
3336         /* Wait for a reasonable time for the link to come up */
3337         tg3_poll_link(tp);
3338         for(i = 0; !tp->carrier_ok && (i < VALID_LINK_TIMEOUT*100); i++) {
3339                 mdelay(1);
3340                 tg3_poll_link(tp);
3341         }
3342         if (!tp->carrier_ok){
3343                 printf("Valid link not established\n");
3344                 goto err_out_disable;
3345         }
3346
3347         dev->disable  = tg3_disable;
3348         nic->poll     = tg3_poll;
3349         nic->transmit = tg3_transmit;
3350         nic->irq      = tg3_irq;
3351
3352         return 1;
3353
3354  err_out_iounmap:
3355         iounmap((void *)tp->regs);
3356         return 0;
3357  err_out_disable:
3358         tg3_disable(dev);
3359         return 0;
3360 }
3361
3362 static struct pci_id tg3_nics[] = {
3363 PCI_ROM(0x14e4, 0x1644, "tg3-5700",        "Broadcom Tigon 3 5700"),
3364 PCI_ROM(0x14e4, 0x1645, "tg3-5701",        "Broadcom Tigon 3 5701"),
3365 PCI_ROM(0x14e4, 0x1646, "tg3-5702",        "Broadcom Tigon 3 5702"),
3366 PCI_ROM(0x14e4, 0x1647, "tg3-5703",        "Broadcom Tigon 3 5703"),
3367 PCI_ROM(0x14e4, 0x1648, "tg3-5704",        "Broadcom Tigon 3 5704"),
3368 PCI_ROM(0x14e4, 0x164d, "tg3-5702FE",      "Broadcom Tigon 3 5702FE"),
3369 PCI_ROM(0x14e4, 0x1653, "tg3-5705",        "Broadcom Tigon 3 5705"),
3370 PCI_ROM(0x14e4, 0x1654, "tg3-5705_2",      "Broadcom Tigon 3 5705_2"),
3371 PCI_ROM(0x14e4, 0x165d, "tg3-5705M",       "Broadcom Tigon 3 5705M"),
3372 PCI_ROM(0x14e4, 0x165e, "tg3-5705M_2",     "Broadcom Tigon 3 5705M_2"),
3373 PCI_ROM(0x14e4, 0x1677, "tg3-5751",        "Broadcom Tigon 3 5751"),
3374 PCI_ROM(0x14e4, 0x1696, "tg3-5782",        "Broadcom Tigon 3 5782"),
3375 PCI_ROM(0x14e4, 0x169c, "tg3-5788",        "Broadcom Tigon 3 5788"),
3376 PCI_ROM(0x14e4, 0x16a6, "tg3-5702X",       "Broadcom Tigon 3 5702X"),
3377 PCI_ROM(0x14e4, 0x16a7, "tg3-5703X",       "Broadcom Tigon 3 5703X"),
3378 PCI_ROM(0x14e4, 0x16a8, "tg3-5704S",       "Broadcom Tigon 3 5704S"),
3379 PCI_ROM(0x14e4, 0x16c6, "tg3-5702A3",      "Broadcom Tigon 3 5702A3"),
3380 PCI_ROM(0x14e4, 0x16c7, "tg3-5703A3",      "Broadcom Tigon 3 5703A3"),
3381 PCI_ROM(0x14e4, 0x170d, "tg3-5901",        "Broadcom Tigon 3 5901"),
3382 PCI_ROM(0x14e4, 0x170e, "tg3-5901_2",      "Broadcom Tigon 3 5901_2"),
3383 PCI_ROM(0x1148, 0x4400, "tg3-9DXX",        "Syskonnect 9DXX"),
3384 PCI_ROM(0x1148, 0x4500, "tg3-9MXX",        "Syskonnect 9MXX"),
3385 PCI_ROM(0x173b, 0x03e8, "tg3-ac1000",      "Altima AC1000"),
3386 PCI_ROM(0x173b, 0x03e9, "tg3-ac1001",      "Altima AC1001"),
3387 PCI_ROM(0x173b, 0x03ea, "tg3-ac9100",      "Altima AC9100"),
3388 PCI_ROM(0x173b, 0x03eb, "tg3-ac1003",      "Altima AC1003"),
3389 };
3390
3391 static struct pci_driver tg3_driver __pci_driver = {
3392         .type     = NIC_DRIVER,
3393         .name     = "TG3",
3394         .probe    = tg3_probe,
3395         .ids      = tg3_nics,
3396         .id_count = sizeof(tg3_nics)/sizeof(tg3_nics[0]),
3397         .class    = 0,
3398 };