Fixed receive buffer overflow on driver unload, which caused receiver to malfunction...
[etherboot.git] / src / drivers / net / e1000.c
1 /**************************************************************************
2 Etherboot -  BOOTP/TFTP Bootstrap Program
3 Inter Pro 1000 for Etherboot
4 Drivers are port from Intel's Linux driver e1000-4.3.15
5
6 ***************************************************************************/
7 /*******************************************************************************
8
9   
10   Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
11   
12   This program is free software; you can redistribute it and/or modify it 
13   under the terms of the GNU General Public License as published by the Free 
14   Software Foundation; either version 2 of the License, or (at your option) 
15   any later version.
16   
17   This program is distributed in the hope that it will be useful, but WITHOUT 
18   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
19   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
20   more details.
21   
22   You should have received a copy of the GNU General Public License along with
23   this program; if not, write to the Free Software Foundation, Inc., 59 
24   Temple Place - Suite 330, Boston, MA  02111-1307, USA.
25   
26   The full GNU General Public License is included in this distribution in the
27   file called LICENSE.
28   
29   Contact Information:
30   Linux NICS <linux.nics@intel.com>
31   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32
33 *******************************************************************************/
34 /*
35  *  Copyright (C) Archway Digital Solutions.
36  *
37  *  written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
38  *  2/9/2002
39  *
40  *  Copyright (C) Linux Networx.
41  *  Massive upgrade to work with the new intel gigabit NICs.
42  *  <ebiederman at lnxi dot com>
43  *
44  *  Support for 82541ei & 82547ei chips from Intel's Linux driver 5.1.13 added by
45  *  Georg Baum <gbaum@users.sf.net>, sponsored by PetaMem GmbH and linkLINE Communications, Inc.
46  *
47  *  01/2004: Updated to Linux driver 5.2.22 by Georg Baum <gbaum@users.sf.net>
48  */
49
50 /* to get some global routines like printf */
51 #include "etherboot.h"
52 /* to get the interface to the body of the program */
53 #include "nic.h"
54 /* to get the PCI support functions, if this is a PCI NIC */
55 #include "pci.h"
56 #include "timer.h"
57
58 typedef unsigned char *dma_addr_t;
59
60 typedef enum {
61         FALSE = 0,
62         TRUE = 1
63 } boolean_t;
64
65 #define DEBUG 0
66
67
68 /* Some pieces of code are disabled with #if 0 ... #endif.
69  * They are not deleted to show where the etherboot driver differs
70  * from the linux driver below the function level.
71  * Some member variables of the hw struct have been eliminated
72  * and the corresponding inplace checks inserted instead.
73  * Pieces such as LED handling that we definitely don't need are deleted.
74  *
75  * Please keep the function ordering so that it is easy to produce diffs
76  * against the linux driver.
77  *
78  * The following defines should not be needed normally,
79  * but may be helpful for debugging purposes. */
80
81 /* Define this if you want to program the transmission control register
82  * the way the Linux driver does it. */
83 #undef LINUX_DRIVER_TCTL
84
85 /* Define this to behave more like the Linux driver. */
86 #undef LINUX_DRIVER
87
88 #include "e1000_hw.h"
89
90 /* NIC specific static variables go here */
91 static struct e1000_hw hw;
92 static char tx_pool[128 + 16];
93 static char rx_pool[128 + 16];
94 static char packet[2096];
95
96 static struct e1000_tx_desc *tx_base;
97 static struct e1000_rx_desc *rx_base;
98
99 static int tx_tail;
100 static int rx_tail, rx_last;
101
102 /* Function forward declarations */
103 static int e1000_setup_link(struct e1000_hw *hw);
104 static int e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
105 static int e1000_setup_copper_link(struct e1000_hw *hw);
106 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
107 static void e1000_config_collision_dist(struct e1000_hw *hw);
108 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
109 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
110 static int e1000_check_for_link(struct e1000_hw *hw);
111 static int e1000_wait_autoneg(struct e1000_hw *hw);
112 static void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, uint16_t *duplex);
113 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
114 static int e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
115 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
116 static int e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
117 static void e1000_phy_hw_reset(struct e1000_hw *hw);
118 static int e1000_phy_reset(struct e1000_hw *hw);
119 static int e1000_detect_gig_phy(struct e1000_hw *hw);
120 static int e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset, uint16_t words, uint16_t *data);
121 static void e1000_init_rx_addrs(struct e1000_hw *hw);
122 static void e1000_clear_vfta(struct e1000_hw *hw);
123 static void e1000_io_write(struct e1000_hw *hw __unused, uint32_t port, uint32_t value);
124 static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
125
126 /* Printing macros... */
127
128 #define E1000_ERR(args...) printf("e1000: " args)
129
130 #if DEBUG >= 3
131 #define E1000_DBG(args...) printf("e1000: " args)
132 #else
133 #define E1000_DBG(args...)
134 #endif
135
136 #define MSGOUT(S, A, B)     printk(S "\n", A, B)
137 #if DEBUG >= 2
138 #define DEBUGFUNC(F)        DEBUGOUT(F "\n");
139 #else
140 #define DEBUGFUNC(F)
141 #endif
142 #if DEBUG >= 1
143 #define DEBUGOUT(S) printf(S)
144 #define DEBUGOUT1(S,A) printf(S,A)
145 #define DEBUGOUT2(S,A,B) printf(S,A,B)
146 #define DEBUGOUT3(S,A,B,C) printf(S,A,B,C)
147 #define DEBUGOUT7(S,A,B,C,D,E,F,G) printf(S,A,B,C,D,E,F,G)
148 #else
149 #define DEBUGOUT(S)
150 #define DEBUGOUT1(S,A)
151 #define DEBUGOUT2(S,A,B)
152 #define DEBUGOUT3(S,A,B,C)
153 #define DEBUGOUT7(S,A,B,C,D,E,F,G)
154 #endif
155
156 #define E1000_WRITE_REG(a, reg, value) ( \
157     ((a)->mac_type >= e1000_82543) ? \
158         (writel((value), ((a)->hw_addr + E1000_##reg))) : \
159         (writel((value), ((a)->hw_addr + E1000_82542_##reg))))
160
161 #define E1000_READ_REG(a, reg) ( \
162     ((a)->mac_type >= e1000_82543) ? \
163         readl((a)->hw_addr + E1000_##reg) : \
164         readl((a)->hw_addr + E1000_82542_##reg))
165
166 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
167     ((a)->mac_type >= e1000_82543) ? \
168         writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))) : \
169         writel((value), ((a)->hw_addr + E1000_82542_##reg + ((offset) << 2))))
170
171 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \
172     ((a)->mac_type >= e1000_82543) ? \
173         readl((a)->hw_addr + E1000_##reg + ((offset) << 2)) : \
174         readl((a)->hw_addr + E1000_82542_##reg + ((offset) << 2)))
175
176 #define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);}
177
178
179 /******************************************************************************
180  * Inline functions from e1000_main.c of the linux driver
181  ******************************************************************************/
182
183 static inline void e1000_pci_set_mwi(struct e1000_hw *hw)
184 {
185         pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
186 }
187
188 static inline void e1000_pci_clear_mwi(struct e1000_hw *hw)
189 {
190         pci_write_config_word(hw->pdev, PCI_COMMAND,
191                               hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
192 }
193
194
195 /******************************************************************************
196  * Functions from e1000_hw.c of the linux driver
197  ******************************************************************************/
198
199 /******************************************************************************
200  * Set the phy type member in the hw struct.
201  *
202  * hw - Struct containing variables accessed by shared code
203  *****************************************************************************/
204 static int32_t
205 e1000_set_phy_type(struct e1000_hw *hw)
206 {
207         DEBUGFUNC("e1000_set_phy_type");
208
209         switch(hw->phy_id) {
210         case M88E1000_E_PHY_ID:
211         case M88E1000_I_PHY_ID:
212         case M88E1011_I_PHY_ID:
213                 hw->phy_type = e1000_phy_m88;
214                 break;
215         case IGP01E1000_I_PHY_ID:
216                 hw->phy_type = e1000_phy_igp;
217                 break;
218         default:
219                 /* Should never have loaded on this device */
220                 hw->phy_type = e1000_phy_undefined;
221                 return -E1000_ERR_PHY_TYPE;
222         }
223
224         return E1000_SUCCESS;
225 }
226
227 /******************************************************************************
228  * IGP phy init script - initializes the GbE PHY
229  *
230  * hw - Struct containing variables accessed by shared code
231  *****************************************************************************/
232 static void
233 e1000_phy_init_script(struct e1000_hw *hw)
234 {
235         DEBUGFUNC("e1000_phy_init_script");
236
237 #if 0
238         /* See e1000_sw_init() of the Linux driver */
239         if(hw->phy_init_script) {
240 #else
241         if((hw->mac_type == e1000_82541) ||
242            (hw->mac_type == e1000_82547) ||
243            (hw->mac_type == e1000_82541_rev_2) ||
244            (hw->mac_type == e1000_82547_rev_2)) {
245 #endif
246                 mdelay(20);
247
248                 e1000_write_phy_reg(hw,0x0000,0x0140);
249
250                 mdelay(5);
251
252                 if(hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547) {
253                         e1000_write_phy_reg(hw, 0x1F95, 0x0001);
254
255                         e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
256
257                         e1000_write_phy_reg(hw, 0x1F79, 0x0018);
258
259                         e1000_write_phy_reg(hw, 0x1F30, 0x1600);
260
261                         e1000_write_phy_reg(hw, 0x1F31, 0x0014);
262
263                         e1000_write_phy_reg(hw, 0x1F32, 0x161C);
264
265                         e1000_write_phy_reg(hw, 0x1F94, 0x0003);
266
267                         e1000_write_phy_reg(hw, 0x1F96, 0x003F);
268
269                         e1000_write_phy_reg(hw, 0x2010, 0x0008);
270                 } else {
271                         e1000_write_phy_reg(hw, 0x1F73, 0x0099);
272                 }
273
274                 e1000_write_phy_reg(hw, 0x0000, 0x3300);
275
276
277                 if(hw->mac_type == e1000_82547) {
278                         uint16_t fused, fine, coarse;
279
280                         /* Move to analog registers page */
281                         e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
282
283                         if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
284                                 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
285
286                                 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
287                                 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
288
289                                 if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
290                                         coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
291                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
292                                 } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
293                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
294
295                                 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
296                                         (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
297                                         (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
298
299                                 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
300                                 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
301                                                 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
302                         }
303                 }
304         }
305 }
306
307 /******************************************************************************
308  * Set the mac type member in the hw struct.
309  * 
310  * hw - Struct containing variables accessed by shared code
311  *****************************************************************************/
312 static int
313 e1000_set_mac_type(struct e1000_hw *hw)
314 {
315         DEBUGFUNC("e1000_set_mac_type");
316
317         switch (hw->device_id) {
318         case E1000_DEV_ID_82542:
319                 switch (hw->revision_id) {
320                 case E1000_82542_2_0_REV_ID:
321                         hw->mac_type = e1000_82542_rev2_0;
322                         break;
323                 case E1000_82542_2_1_REV_ID:
324                         hw->mac_type = e1000_82542_rev2_1;
325                         break;
326                 default:
327                         /* Invalid 82542 revision ID */
328                         return -E1000_ERR_MAC_TYPE;
329                 }
330                 break;
331         case E1000_DEV_ID_82543GC_FIBER:
332         case E1000_DEV_ID_82543GC_COPPER:
333                 hw->mac_type = e1000_82543;
334                 break;
335         case E1000_DEV_ID_82544EI_COPPER:
336         case E1000_DEV_ID_82544EI_FIBER:
337         case E1000_DEV_ID_82544GC_COPPER:
338         case E1000_DEV_ID_82544GC_LOM:
339                 hw->mac_type = e1000_82544;
340                 break;
341         case E1000_DEV_ID_82540EM:
342         case E1000_DEV_ID_82540EM_LOM:
343         case E1000_DEV_ID_82540EP:
344         case E1000_DEV_ID_82540EP_LOM:
345         case E1000_DEV_ID_82540EP_LP:
346                 hw->mac_type = e1000_82540;
347                 break;
348         case E1000_DEV_ID_82545EM_COPPER:
349         case E1000_DEV_ID_82545EM_FIBER:
350                 hw->mac_type = e1000_82545;
351                 break;
352         case E1000_DEV_ID_82545GM_COPPER:
353         case E1000_DEV_ID_82545GM_FIBER:
354         case E1000_DEV_ID_82545GM_SERDES:
355                 hw->mac_type = e1000_82545_rev_3;
356                 break;
357         case E1000_DEV_ID_82546EB_COPPER:
358         case E1000_DEV_ID_82546EB_FIBER:
359         case E1000_DEV_ID_82546EB_QUAD_COPPER:
360                 hw->mac_type = e1000_82546;
361                 break;
362         case E1000_DEV_ID_82546GB_COPPER:
363         case E1000_DEV_ID_82546GB_FIBER:
364         case E1000_DEV_ID_82546GB_SERDES:
365                 hw->mac_type = e1000_82546_rev_3;
366                 break;
367         case E1000_DEV_ID_82541EI:
368         case E1000_DEV_ID_82541EI_MOBILE:
369                 hw->mac_type = e1000_82541;
370                 break;
371         case E1000_DEV_ID_82541ER:
372         case E1000_DEV_ID_82541GI:
373         case E1000_DEV_ID_82541GI_MOBILE:
374                 hw->mac_type = e1000_82541_rev_2;
375                 break;
376         case E1000_DEV_ID_82547EI:
377                 hw->mac_type = e1000_82547;
378                 break;
379         case E1000_DEV_ID_82547GI:
380                 hw->mac_type = e1000_82547_rev_2;
381                 break;
382         default:
383                 /* Should never have loaded on this device */
384                 return -E1000_ERR_MAC_TYPE;
385         }
386
387         return E1000_SUCCESS;
388 }
389
390 /*****************************************************************************
391  * Set media type and TBI compatibility.
392  *
393  * hw - Struct containing variables accessed by shared code
394  * **************************************************************************/
395 static void
396 e1000_set_media_type(struct e1000_hw *hw)
397 {
398         uint32_t status;
399
400         DEBUGFUNC("e1000_set_media_type");
401         
402         if(hw->mac_type != e1000_82543) {
403                 /* tbi_compatibility is only valid on 82543 */
404                 hw->tbi_compatibility_en = FALSE;
405         }
406
407         switch (hw->device_id) {
408                 case E1000_DEV_ID_82545GM_SERDES:
409                 case E1000_DEV_ID_82546GB_SERDES:
410                         hw->media_type = e1000_media_type_internal_serdes;
411                         break;
412                 default:
413                         if(hw->mac_type >= e1000_82543) {
414                                 status = E1000_READ_REG(hw, STATUS);
415                                 if(status & E1000_STATUS_TBIMODE) {
416                                         hw->media_type = e1000_media_type_fiber;
417                                         /* tbi_compatibility not valid on fiber */
418                                         hw->tbi_compatibility_en = FALSE;
419                                 } else {
420                                         hw->media_type = e1000_media_type_copper;
421                                 }
422                         } else {
423                                 /* This is an 82542 (fiber only) */
424                                 hw->media_type = e1000_media_type_fiber;
425                         }
426         }
427 }
428
429 /******************************************************************************
430  * Reset the transmit and receive units; mask and clear all interrupts.
431  *
432  * hw - Struct containing variables accessed by shared code
433  *****************************************************************************/
434 static void
435 e1000_reset_hw(struct e1000_hw *hw)
436 {
437         uint32_t ctrl;
438         uint32_t ctrl_ext;
439         uint32_t icr;
440         uint32_t manc;
441         
442         DEBUGFUNC("e1000_reset_hw");
443         
444         /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
445         if(hw->mac_type == e1000_82542_rev2_0) {
446                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
447                 e1000_pci_clear_mwi(hw);
448         }
449
450         /* Clear interrupt mask to stop board from generating interrupts */
451         DEBUGOUT("Masking off all interrupts\n");
452         E1000_WRITE_REG(hw, IMC, 0xffffffff);
453         
454         /* Disable the Transmit and Receive units.  Then delay to allow
455          * any pending transactions to complete before we hit the MAC with
456          * the global reset.
457          */
458         E1000_WRITE_REG(hw, RCTL, 0);
459         E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
460         E1000_WRITE_FLUSH(hw);
461
462         /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
463         hw->tbi_compatibility_on = FALSE;
464
465         /* Delay to allow any outstanding PCI transactions to complete before
466          * resetting the device
467          */ 
468         mdelay(10);
469
470         ctrl = E1000_READ_REG(hw, CTRL);
471
472         /* Must reset the PHY before resetting the MAC */
473         if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
474                 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
475                 mdelay(5);
476         }
477
478         /* Issue a global reset to the MAC.  This will reset the chip's
479          * transmit, receive, DMA, and link units.  It will not effect
480          * the current PCI configuration.  The global reset bit is self-
481          * clearing, and should clear within a microsecond.
482          */
483         DEBUGOUT("Issuing a global reset to MAC\n");
484
485         switch(hw->mac_type) {
486                 case e1000_82544:
487                 case e1000_82540:
488                 case e1000_82545:
489                 case e1000_82546:
490                 case e1000_82541:
491                 case e1000_82541_rev_2:
492                         /* These controllers can't ack the 64-bit write when issuing the
493                          * reset, so use IO-mapping as a workaround to issue the reset */
494                         E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
495                         break;
496                 case e1000_82545_rev_3:
497                 case e1000_82546_rev_3:
498                         /* Reset is performed on a shadow of the control register */
499                         E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
500                         break;
501                 default:
502                         E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
503                         break;
504         }
505
506         /* After MAC reset, force reload of EEPROM to restore power-on settings to
507          * device.  Later controllers reload the EEPROM automatically, so just wait
508          * for reload to complete.
509          */
510         switch(hw->mac_type) {
511                 case e1000_82542_rev2_0:
512                 case e1000_82542_rev2_1:
513                 case e1000_82543:
514                 case e1000_82544:
515                         /* Wait for reset to complete */
516                         udelay(10);
517                         ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
518                         ctrl_ext |= E1000_CTRL_EXT_EE_RST;
519                         E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
520                         E1000_WRITE_FLUSH(hw);
521                         /* Wait for EEPROM reload */
522                         mdelay(2);
523                         break;
524                 case e1000_82541:
525                 case e1000_82541_rev_2:
526                 case e1000_82547:
527                 case e1000_82547_rev_2:
528                         /* Wait for EEPROM reload */
529                         mdelay(20);
530                         break;
531                 default:
532                         /* Wait for EEPROM reload (it happens automatically) */
533                         mdelay(5);
534                         break;
535         }
536
537         /* Disable HW ARPs on ASF enabled adapters */
538         if(hw->mac_type >= e1000_82540) {
539                 manc = E1000_READ_REG(hw, MANC);
540                 manc &= ~(E1000_MANC_ARP_EN);
541                 E1000_WRITE_REG(hw, MANC, manc);
542         }
543
544         if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
545                 e1000_phy_init_script(hw);
546         }
547
548         /* Clear interrupt mask to stop board from generating interrupts */
549         DEBUGOUT("Masking off all interrupts\n");
550         E1000_WRITE_REG(hw, IMC, 0xffffffff);
551         
552         /* Clear any pending interrupt events. */
553         icr = E1000_READ_REG(hw, ICR);
554
555         /* If MWI was previously enabled, reenable it. */
556         if(hw->mac_type == e1000_82542_rev2_0) {
557 #ifdef LINUX_DRIVER
558                 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
559 #endif
560                         e1000_pci_set_mwi(hw);
561         }
562 }
563
564 /******************************************************************************
565  * Performs basic configuration of the adapter.
566  *
567  * hw - Struct containing variables accessed by shared code
568  * 
569  * Assumes that the controller has previously been reset and is in a 
570  * post-reset uninitialized state. Initializes the receive address registers,
571  * multicast table, and VLAN filter table. Calls routines to setup link
572  * configuration and flow control settings. Clears all on-chip counters. Leaves
573  * the transmit and receive units disabled and uninitialized.
574  *****************************************************************************/
575 static int
576 e1000_init_hw(struct e1000_hw *hw)
577 {
578         uint32_t ctrl, status;
579         uint32_t i;
580         int32_t ret_val;
581         uint16_t pcix_cmd_word;
582         uint16_t pcix_stat_hi_word;
583         uint16_t cmd_mmrbc;
584         uint16_t stat_mmrbc;
585         e1000_bus_type bus_type = e1000_bus_type_unknown;
586
587         DEBUGFUNC("e1000_init_hw");
588
589         /* Set the media type and TBI compatibility */
590         e1000_set_media_type(hw);
591
592         /* Disabling VLAN filtering. */
593         DEBUGOUT("Initializing the IEEE VLAN\n");
594         E1000_WRITE_REG(hw, VET, 0);
595         
596         e1000_clear_vfta(hw);
597         
598         /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
599         if(hw->mac_type == e1000_82542_rev2_0) {
600                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
601                 e1000_pci_clear_mwi(hw);
602                 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
603                 E1000_WRITE_FLUSH(hw);
604                 mdelay(5);
605         }
606         
607         /* Setup the receive address. This involves initializing all of the Receive
608          * Address Registers (RARs 0 - 15).
609          */
610         e1000_init_rx_addrs(hw);
611         
612         /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
613         if(hw->mac_type == e1000_82542_rev2_0) {
614                 E1000_WRITE_REG(hw, RCTL, 0);
615                 E1000_WRITE_FLUSH(hw);
616                 mdelay(1);
617 #ifdef LINUX_DRIVER
618                 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
619 #endif
620                         e1000_pci_set_mwi(hw);
621         }
622         
623         /* Zero out the Multicast HASH table */
624         DEBUGOUT("Zeroing the MTA\n");
625         for(i = 0; i < E1000_MC_TBL_SIZE; i++)
626                 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
627         
628 #if 0
629         /* Set the PCI priority bit correctly in the CTRL register.  This
630          * determines if the adapter gives priority to receives, or if it
631          * gives equal priority to transmits and receives.
632          */
633         if(hw->dma_fairness) {
634                 ctrl = E1000_READ_REG(hw, CTRL);
635                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
636         }
637 #endif
638
639         switch(hw->mac_type) {
640                 case e1000_82545_rev_3:
641                 case e1000_82546_rev_3:
642                         break;
643                 default:
644                         if (hw->mac_type >= e1000_82543) {
645                                 /* See e1000_get_bus_info() of the Linux driver */
646                                 status = E1000_READ_REG(hw, STATUS);
647                                 bus_type = (status & E1000_STATUS_PCIX_MODE) ?
648                                         e1000_bus_type_pcix : e1000_bus_type_pci;
649                         }
650
651                         /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
652                         if(bus_type == e1000_bus_type_pcix) {
653                                 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
654                                 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
655                                 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
656                                         PCIX_COMMAND_MMRBC_SHIFT;
657                                 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
658                                         PCIX_STATUS_HI_MMRBC_SHIFT;
659                                 if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
660                                         stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
661                                 if(cmd_mmrbc > stat_mmrbc) {
662                                         pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
663                                         pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
664                                         pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, pcix_cmd_word);
665                                 }
666                         }
667                         break;
668         }
669
670         /* Call a subroutine to configure the link and setup flow control. */
671         ret_val = e1000_setup_link(hw);
672         
673         /* Set the transmit descriptor write-back policy */
674         if(hw->mac_type > e1000_82544) {
675                 ctrl = E1000_READ_REG(hw, TXDCTL);
676                 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
677                 E1000_WRITE_REG(hw, TXDCTL, ctrl);
678         }
679
680 #if 0
681         /* Clear all of the statistics registers (clear on read).  It is
682          * important that we do this after we have tried to establish link
683          * because the symbol error count will increment wildly if there
684          * is no link.
685          */
686         e1000_clear_hw_cntrs(hw);
687 #endif
688
689         return ret_val;
690 }
691
692 /******************************************************************************
693  * Adjust SERDES output amplitude based on EEPROM setting.
694  *
695  * hw - Struct containing variables accessed by shared code.
696  *****************************************************************************/
697 static int32_t
698 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
699 {
700         uint16_t eeprom_data;
701         int32_t  ret_val;
702
703         DEBUGFUNC("e1000_adjust_serdes_amplitude");
704
705         if(hw->media_type != e1000_media_type_internal_serdes)
706                 return E1000_SUCCESS;
707
708         switch(hw->mac_type) {
709                 case e1000_82545_rev_3:
710                 case e1000_82546_rev_3:
711                         break;
712                 default:
713                         return E1000_SUCCESS;
714         }
715
716         if ((ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
717                                         &eeprom_data))) {
718                 return ret_val;
719         }
720
721         if(eeprom_data != EEPROM_RESERVED_WORD) {
722                 /* Adjust SERDES output amplitude only. */
723                 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
724                 if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL,
725                                                   eeprom_data)))
726                         return ret_val;
727         }
728
729         return E1000_SUCCESS;
730 }
731                                                                    
732 /******************************************************************************
733  * Configures flow control and link settings.
734  * 
735  * hw - Struct containing variables accessed by shared code
736  * 
737  * Determines which flow control settings to use. Calls the apropriate media-
738  * specific link configuration function. Configures the flow control settings.
739  * Assuming the adapter has a valid link partner, a valid link should be
740  * established. Assumes the hardware has previously been reset and the 
741  * transmitter and receiver are not enabled.
742  *****************************************************************************/
743 static int
744 e1000_setup_link(struct e1000_hw *hw)
745 {
746         uint32_t ctrl_ext;
747         int32_t ret_val;
748         uint16_t eeprom_data;
749
750         DEBUGFUNC("e1000_setup_link");
751         
752         /* Read and store word 0x0F of the EEPROM. This word contains bits
753          * that determine the hardware's default PAUSE (flow control) mode,
754          * a bit that determines whether the HW defaults to enabling or
755          * disabling auto-negotiation, and the direction of the
756          * SW defined pins. If there is no SW over-ride of the flow
757          * control setting, then the variable hw->fc will
758          * be initialized based on a value in the EEPROM.
759          */
760         if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
761                 DEBUGOUT("EEPROM Read Error\n");
762                 return -E1000_ERR_EEPROM;
763         }
764         
765         if(hw->fc == e1000_fc_default) {
766                 if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
767                         hw->fc = e1000_fc_none;
768                 else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 
769                         EEPROM_WORD0F_ASM_DIR)
770                         hw->fc = e1000_fc_tx_pause;
771                 else
772                         hw->fc = e1000_fc_full;
773         }
774         
775         /* We want to save off the original Flow Control configuration just
776          * in case we get disconnected and then reconnected into a different
777          * hub or switch with different Flow Control capabilities.
778          */
779         if(hw->mac_type == e1000_82542_rev2_0)
780                 hw->fc &= (~e1000_fc_tx_pause);
781
782 #if 0
783         /* See e1000_sw_init() of the Linux driver */
784         if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
785 #else
786         if((hw->mac_type < e1000_82543) && (hw->mac_type >= e1000_82543))
787 #endif
788                 hw->fc &= (~e1000_fc_rx_pause);
789         
790 #if 0
791         hw->original_fc = hw->fc;
792 #endif
793
794         DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
795         
796         /* Take the 4 bits from EEPROM word 0x0F that determine the initial
797          * polarity value for the SW controlled pins, and setup the
798          * Extended Device Control reg with that info.
799          * This is needed because one of the SW controlled pins is used for
800          * signal detection.  So this should be done before e1000_setup_pcs_link()
801          * or e1000_phy_setup() is called.
802          */
803         if(hw->mac_type == e1000_82543) {
804                 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 
805                         SWDPIO__EXT_SHIFT);
806                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
807         }
808         
809         /* Call the necessary subroutine to configure the link. */
810         ret_val = (hw->media_type == e1000_media_type_copper) ?
811                 e1000_setup_copper_link(hw) :
812                 e1000_setup_fiber_serdes_link(hw);
813         if (ret_val < 0) {
814                 return ret_val;
815         }
816         
817         /* Initialize the flow control address, type, and PAUSE timer
818          * registers to their default values.  This is done even if flow
819          * control is disabled, because it does not hurt anything to
820          * initialize these registers.
821          */
822         DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
823         
824         E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
825         E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
826         E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
827 #if 0
828         E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
829 #else
830         E1000_WRITE_REG(hw, FCTTV, FC_DEFAULT_TX_TIMER);
831 #endif
832         
833         /* Set the flow control receive threshold registers.  Normally,
834          * these registers will be set to a default threshold that may be
835          * adjusted later by the driver's runtime code.  However, if the
836          * ability to transmit pause frames in not enabled, then these
837          * registers will be set to 0. 
838          */
839         if(!(hw->fc & e1000_fc_tx_pause)) {
840                 E1000_WRITE_REG(hw, FCRTL, 0);
841                 E1000_WRITE_REG(hw, FCRTH, 0);
842         } else {
843                 /* We need to set up the Receive Threshold high and low water marks
844                  * as well as (optionally) enabling the transmission of XON frames.
845                  */
846 #if 0
847                 if(hw->fc_send_xon) {
848                         E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
849                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
850                 } else {
851                         E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
852                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
853                 }
854 #else
855                 E1000_WRITE_REG(hw, FCRTL, (FC_DEFAULT_LO_THRESH | E1000_FCRTL_XONE));
856                 E1000_WRITE_REG(hw, FCRTH, FC_DEFAULT_HI_THRESH);
857 #endif
858         }
859         return ret_val;
860 }
861
862 /******************************************************************************
863  * Sets up link for a fiber based or serdes based adapter
864  *
865  * hw - Struct containing variables accessed by shared code
866  *
867  * Manipulates Physical Coding Sublayer functions in order to configure
868  * link. Assumes the hardware has been previously reset and the transmitter
869  * and receiver are not enabled.
870  *****************************************************************************/
871 static int
872 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
873 {
874         uint32_t ctrl;
875         uint32_t status;
876         uint32_t txcw = 0;
877         uint32_t i;
878         uint32_t signal = 0;
879         int32_t ret_val;
880
881         DEBUGFUNC("e1000_setup_fiber_serdes_link");
882
883         /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 
884          * set when the optics detect a signal. On older adapters, it will be 
885          * cleared when there is a signal.  This applies to fiber media only.
886          * If we're on serdes media, adjust the output amplitude to value set in
887          * the EEPROM.
888          */
889         ctrl = E1000_READ_REG(hw, CTRL);
890         if(hw->media_type == e1000_media_type_fiber)
891                 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
892
893         if((ret_val = e1000_adjust_serdes_amplitude(hw)))
894                 return ret_val;
895
896         /* Take the link out of reset */
897         ctrl &= ~(E1000_CTRL_LRST);
898
899 #if 0
900         /* Adjust VCO speed to improve BER performance */
901         if((ret_val = e1000_set_vco_speed(hw)))
902                 return ret_val;
903 #endif
904
905         e1000_config_collision_dist(hw);
906         
907         /* Check for a software override of the flow control settings, and setup
908          * the device accordingly.  If auto-negotiation is enabled, then software
909          * will have to set the "PAUSE" bits to the correct value in the Tranmsit
910          * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
911          * auto-negotiation is disabled, then software will have to manually 
912          * configure the two flow control enable bits in the CTRL register.
913          *
914          * The possible values of the "fc" parameter are:
915          *      0:  Flow control is completely disabled
916          *      1:  Rx flow control is enabled (we can receive pause frames, but 
917          *          not send pause frames).
918          *      2:  Tx flow control is enabled (we can send pause frames but we do
919          *          not support receiving pause frames).
920          *      3:  Both Rx and TX flow control (symmetric) are enabled.
921          */
922         switch (hw->fc) {
923         case e1000_fc_none:
924                 /* Flow control is completely disabled by a software over-ride. */
925                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
926                 break;
927         case e1000_fc_rx_pause:
928                 /* RX Flow control is enabled and TX Flow control is disabled by a 
929                  * software over-ride. Since there really isn't a way to advertise 
930                  * that we are capable of RX Pause ONLY, we will advertise that we
931                  * support both symmetric and asymmetric RX PAUSE. Later, we will
932                  *  disable the adapter's ability to send PAUSE frames.
933                  */
934                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
935                 break;
936         case e1000_fc_tx_pause:
937                 /* TX Flow control is enabled, and RX Flow control is disabled, by a 
938                  * software over-ride.
939                  */
940                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
941                 break;
942         case e1000_fc_full:
943                 /* Flow control (both RX and TX) is enabled by a software over-ride. */
944                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
945                 break;
946         default:
947                 DEBUGOUT("Flow control param set incorrectly\n");
948                 return -E1000_ERR_CONFIG;
949                 break;
950         }
951         
952         /* Since auto-negotiation is enabled, take the link out of reset (the link
953          * will be in reset, because we previously reset the chip). This will
954          * restart auto-negotiation.  If auto-neogtiation is successful then the
955          * link-up status bit will be set and the flow control enable bits (RFCE
956          * and TFCE) will be set according to their negotiated value.
957          */
958         DEBUGOUT("Auto-negotiation enabled\n");
959         
960         E1000_WRITE_REG(hw, TXCW, txcw);
961         E1000_WRITE_REG(hw, CTRL, ctrl);
962         E1000_WRITE_FLUSH(hw);
963         
964         hw->txcw = txcw;
965         mdelay(1);
966         
967         /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
968          * indication in the Device Status Register.  Time-out if a link isn't 
969          * seen in 500 milliseconds seconds (Auto-negotiation should complete in 
970          * less than 500 milliseconds even if the other end is doing it in SW).
971          * For internal serdes, we just assume a signal is present, then poll.
972          */
973         if(hw->media_type == e1000_media_type_internal_serdes ||
974            (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
975                 DEBUGOUT("Looking for Link\n");
976                 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
977                         mdelay(10);
978                         status = E1000_READ_REG(hw, STATUS);
979                         if(status & E1000_STATUS_LU) break;
980                 }
981                 if(i == (LINK_UP_TIMEOUT / 10)) {
982                         DEBUGOUT("Never got a valid link from auto-neg!!!\n");
983                         hw->autoneg_failed = 1;
984                         /* AutoNeg failed to achieve a link, so we'll call 
985                          * e1000_check_for_link. This routine will force the link up if
986                          * we detect a signal. This will allow us to communicate with
987                          * non-autonegotiating link partners.
988                          */
989                         if((ret_val = e1000_check_for_link(hw))) {
990                                 DEBUGOUT("Error while checking for link\n");
991                                 return ret_val;
992                         }
993                         hw->autoneg_failed = 0;
994                 } else {
995                         hw->autoneg_failed = 0;
996                         DEBUGOUT("Valid Link Found\n");
997                 }
998         } else {
999                 DEBUGOUT("No Signal Detected\n");
1000         }
1001         return E1000_SUCCESS;
1002 }
1003
1004 /******************************************************************************
1005 * Detects which PHY is present and the speed and duplex
1006 *
1007 * hw - Struct containing variables accessed by shared code
1008 ******************************************************************************/
1009 static int
1010 e1000_setup_copper_link(struct e1000_hw *hw)
1011 {
1012         uint32_t ctrl;
1013         int32_t ret_val;
1014         uint16_t i;
1015         uint16_t phy_data;
1016         
1017         DEBUGFUNC("e1000_setup_copper_link");
1018         
1019         ctrl = E1000_READ_REG(hw, CTRL);
1020         /* With 82543, we need to force speed and duplex on the MAC equal to what
1021          * the PHY speed and duplex configuration is. In addition, we need to
1022          * perform a hardware reset on the PHY to take it out of reset.
1023          */
1024         if(hw->mac_type > e1000_82543) {
1025                 ctrl |= E1000_CTRL_SLU;
1026                 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1027                 E1000_WRITE_REG(hw, CTRL, ctrl);
1028         } else {
1029                 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1030                 E1000_WRITE_REG(hw, CTRL, ctrl);
1031                 e1000_phy_hw_reset(hw);
1032         }
1033         
1034         /* Make sure we have a valid PHY */
1035         if((ret_val = e1000_detect_gig_phy(hw))) {
1036                 DEBUGOUT("Error, did not detect valid phy.\n");
1037                 return ret_val;
1038         }
1039         DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1040
1041         if(hw->mac_type <= e1000_82543 ||
1042            hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1043 #if 0
1044            hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1045                 hw->phy_reset_disable = FALSE;
1046
1047         if(!hw->phy_reset_disable) {
1048 #else
1049            hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
1050 #endif
1051         if (hw->phy_type == e1000_phy_igp) {
1052
1053                 if((ret_val = e1000_phy_reset(hw))) {
1054                         DEBUGOUT("Error Resetting the PHY\n");
1055                         return ret_val;
1056                 }
1057
1058                 /* Wait 10ms for MAC to configure PHY from eeprom settings */
1059                 mdelay(15);
1060
1061 #if 0
1062                 /* disable lplu d3 during driver init */
1063                 if((ret_val = e1000_set_d3_lplu_state(hw, FALSE))) {
1064                         DEBUGOUT("Error Disabling LPLU D3\n");
1065                         return ret_val;
1066                 }
1067
1068                 /* Configure mdi-mdix settings */
1069                 if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1070                                                  &phy_data)))
1071                         return ret_val;
1072
1073                 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1074                         hw->dsp_config_state = e1000_dsp_config_disabled;
1075                         /* Force MDI for IGP B-0 PHY */
1076                         phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
1077                                       IGP01E1000_PSCR_FORCE_MDI_MDIX);
1078                         hw->mdix = 1;
1079
1080                 } else {
1081                         hw->dsp_config_state = e1000_dsp_config_enabled;
1082                         phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1083
1084                         switch (hw->mdix) {
1085                         case 1:
1086                                 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1087                                 break;
1088                         case 2:
1089                                 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1090                                 break;
1091                         case 0:
1092                         default:
1093                                 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1094                                 break;
1095                         }
1096                 }
1097                 if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1098                                                   phy_data)))
1099                         return ret_val;
1100
1101                 /* set auto-master slave resolution settings */
1102                 e1000_ms_type phy_ms_setting = hw->master_slave;
1103
1104                 if(hw->ffe_config_state == e1000_ffe_config_active)
1105                         hw->ffe_config_state = e1000_ffe_config_enabled;
1106
1107                 if(hw->dsp_config_state == e1000_dsp_config_activated)
1108                         hw->dsp_config_state = e1000_dsp_config_enabled;
1109 #endif
1110
1111                 /* when autonegotiation advertisment is only 1000Mbps then we
1112                  * should disable SmartSpeed and enable Auto MasterSlave
1113                  * resolution as hardware default. */
1114                 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1115                         /* Disable SmartSpeed */
1116                         if((ret_val = e1000_read_phy_reg(hw,
1117                                                          IGP01E1000_PHY_PORT_CONFIG,
1118                                                          &phy_data)))
1119                                 return ret_val;
1120                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1121                         if((ret_val = e1000_write_phy_reg(hw,
1122                                                           IGP01E1000_PHY_PORT_CONFIG,
1123                                                           phy_data)))
1124                                 return ret_val;
1125                         /* Set auto Master/Slave resolution process */
1126                         if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
1127                                                          &phy_data)))
1128                                 return ret_val;
1129                         phy_data &= ~CR_1000T_MS_ENABLE;
1130                         if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1131                                                           phy_data)))
1132                                 return ret_val;
1133                 }
1134
1135                 if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
1136                                                  &phy_data)))
1137                         return ret_val;
1138
1139 #if 0
1140                 /* load defaults for future use */
1141                 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1142                                             ((phy_data & CR_1000T_MS_VALUE) ?
1143                                              e1000_ms_force_master :
1144                                              e1000_ms_force_slave) :
1145                                              e1000_ms_auto;
1146
1147                 switch (phy_ms_setting) {
1148                 case e1000_ms_force_master:
1149                         phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1150                         break;
1151                 case e1000_ms_force_slave:
1152                         phy_data |= CR_1000T_MS_ENABLE;
1153                         phy_data &= ~(CR_1000T_MS_VALUE);
1154                         break;
1155                 case e1000_ms_auto:
1156                         phy_data &= ~CR_1000T_MS_ENABLE;
1157                 default:
1158                         break;
1159                 }
1160 #endif
1161
1162                 if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1163                                                   phy_data)))
1164                         return ret_val;
1165         } else {
1166                 /* Enable CRS on TX. This must be set for half-duplex operation. */
1167                 if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1168                                                  &phy_data)))
1169                         return ret_val;
1170
1171                 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1172
1173                 /* Options:
1174                  *   MDI/MDI-X = 0 (default)
1175                  *   0 - Auto for all speeds
1176                  *   1 - MDI mode
1177                  *   2 - MDI-X mode
1178                  *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1179                  */
1180 #if 0
1181                 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1182
1183                 switch (hw->mdix) {
1184                 case 1:
1185                         phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1186                         break;
1187                 case 2:
1188                         phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1189                         break;
1190                 case 3:
1191                         phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1192                         break;
1193                 case 0:
1194                 default:
1195 #endif
1196                         phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1197 #if 0
1198                         break;
1199                 }
1200 #endif
1201
1202                 /* Options:
1203                  *   disable_polarity_correction = 0 (default)
1204                  *       Automatic Correction for Reversed Cable Polarity
1205                  *   0 - Disabled
1206                  *   1 - Enabled
1207                  */
1208                 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1209                 if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1210                                                   phy_data)))
1211                         return ret_val;
1212
1213                 /* Force TX_CLK in the Extended PHY Specific Control Register
1214                  * to 25MHz clock.
1215                  */
1216                 if((ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1217                                                  &phy_data)))
1218                         return ret_val;
1219
1220                 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1221
1222 #ifdef LINUX_DRIVER
1223                 if (hw->phy_revision < M88E1011_I_REV_4) {
1224 #endif
1225                         /* Configure Master and Slave downshift values */
1226                         phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1227                                 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1228                         phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1229                                 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1230                         if((ret_val = e1000_write_phy_reg(hw,
1231                                                           M88E1000_EXT_PHY_SPEC_CTRL,
1232                                                           phy_data)))
1233                                 return ret_val;
1234                 }
1235         
1236                 /* SW Reset the PHY so all changes take effect */
1237                 if((ret_val = e1000_phy_reset(hw))) {
1238                         DEBUGOUT("Error Resetting the PHY\n");
1239                         return ret_val;
1240 #ifdef LINUX_DRIVER
1241                 }
1242 #endif
1243         }
1244         
1245         /* Options:
1246          *   autoneg = 1 (default)
1247          *      PHY will advertise value(s) parsed from
1248          *      autoneg_advertised and fc
1249          *   autoneg = 0
1250          *      PHY will be set to 10H, 10F, 100H, or 100F
1251          *      depending on value parsed from forced_speed_duplex.
1252          */
1253         
1254         /* Is autoneg enabled?  This is enabled by default or by software
1255          * override.  If so, call e1000_phy_setup_autoneg routine to parse the
1256          * autoneg_advertised and fc options. If autoneg is NOT enabled, then
1257          * the user should have provided a speed/duplex override.  If so, then
1258          * call e1000_phy_force_speed_duplex to parse and set this up.
1259          */
1260         /* Perform some bounds checking on the hw->autoneg_advertised
1261          * parameter.  If this variable is zero, then set it to the default.
1262          */
1263         hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1264         
1265         /* If autoneg_advertised is zero, we assume it was not defaulted
1266          * by the calling code so we set to advertise full capability.
1267          */
1268         if(hw->autoneg_advertised == 0)
1269                 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1270         
1271         DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1272         if((ret_val = e1000_phy_setup_autoneg(hw))) {
1273                 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1274                 return ret_val;
1275         }
1276         DEBUGOUT("Restarting Auto-Neg\n");
1277         
1278         /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1279          * the Auto Neg Restart bit in the PHY control register.
1280          */
1281         if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
1282                 return ret_val;
1283
1284         phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1285         if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
1286                 return ret_val;
1287
1288 #if 0   
1289         /* Does the user want to wait for Auto-Neg to complete here, or
1290          * check at a later time (for example, callback routine).
1291          */
1292         if(hw->wait_autoneg_complete) {
1293                 if((ret_val = e1000_wait_autoneg(hw))) {
1294                         DEBUGOUT("Error while waiting for autoneg to complete\n");
1295                         return ret_val;
1296                 }
1297         }
1298 #else
1299         /* If we do not wait for autonegotiation to complete I 
1300          * do not see a valid link status.
1301          */
1302         if((ret_val = e1000_wait_autoneg(hw))) {
1303                 DEBUGOUT("Error while waiting for autoneg to complete\n");
1304                 return ret_val;
1305         }
1306 #endif
1307         } /* !hw->phy_reset_disable */
1308         
1309         /* Check link status. Wait up to 100 microseconds for link to become
1310          * valid.
1311          */
1312         for(i = 0; i < 10; i++) {
1313                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1314                         return ret_val;
1315                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1316                         return ret_val;
1317
1318                 if(phy_data & MII_SR_LINK_STATUS) {
1319                         /* We have link, so we need to finish the config process:
1320                          *   1) Set up the MAC to the current PHY speed/duplex
1321                          *      if we are on 82543.  If we
1322                          *      are on newer silicon, we only need to configure
1323                          *      collision distance in the Transmit Control Register.
1324                          *   2) Set up flow control on the MAC to that established with
1325                          *      the link partner.
1326                          */
1327                         if(hw->mac_type >= e1000_82544) {
1328                                 e1000_config_collision_dist(hw);
1329                         } else {
1330                                 if((ret_val = e1000_config_mac_to_phy(hw))) {
1331                                         DEBUGOUT("Error configuring MAC to PHY settings\n");
1332                                         return ret_val;
1333                                 }
1334                         }
1335                         if((ret_val = e1000_config_fc_after_link_up(hw))) {
1336                                 DEBUGOUT("Error Configuring Flow Control\n");
1337                                 return ret_val;
1338                         }
1339 #if 0
1340                         if(hw->phy_type == e1000_phy_igp) {
1341                                 if((ret_val = e1000_config_dsp_after_link_change(hw, TRUE))) {
1342                                         DEBUGOUT("Error Configuring DSP after link up\n");
1343                                         return ret_val;
1344                                 }
1345                         }
1346 #endif
1347                         DEBUGOUT("Valid link established!!!\n");
1348                         return E1000_SUCCESS;
1349                 }
1350                 udelay(10);
1351         }
1352         
1353         DEBUGOUT("Unable to establish link!!!\n");
1354         return -E1000_ERR_NOLINK;
1355 }
1356
1357 /******************************************************************************
1358 * Configures PHY autoneg and flow control advertisement settings
1359 *
1360 * hw - Struct containing variables accessed by shared code
1361 ******************************************************************************/
1362 static int
1363 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1364 {
1365         int32_t ret_val;
1366         uint16_t mii_autoneg_adv_reg;
1367         uint16_t mii_1000t_ctrl_reg;
1368
1369         DEBUGFUNC("e1000_phy_setup_autoneg");
1370         
1371         /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1372         if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
1373                                          &mii_autoneg_adv_reg)))
1374                 return ret_val;
1375
1376         /* Read the MII 1000Base-T Control Register (Address 9). */
1377         if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg)))
1378                 return ret_val;
1379
1380         /* Need to parse both autoneg_advertised and fc and set up
1381          * the appropriate PHY registers.  First we will parse for
1382          * autoneg_advertised software override.  Since we can advertise
1383          * a plethora of combinations, we need to check each bit
1384          * individually.
1385          */
1386         
1387         /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1388          * Advertisement Register (Address 4) and the 1000 mb speed bits in
1389          * the  1000Base-T Control Register (Address 9).
1390          */
1391         mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1392         mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1393
1394         DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1395
1396         /* Do we want to advertise 10 Mb Half Duplex? */
1397         if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
1398                 DEBUGOUT("Advertise 10mb Half duplex\n");
1399                 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1400         }
1401
1402         /* Do we want to advertise 10 Mb Full Duplex? */
1403         if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
1404                 DEBUGOUT("Advertise 10mb Full duplex\n");
1405                 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1406         }
1407
1408         /* Do we want to advertise 100 Mb Half Duplex? */
1409         if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
1410                 DEBUGOUT("Advertise 100mb Half duplex\n");
1411                 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1412         }
1413
1414         /* Do we want to advertise 100 Mb Full Duplex? */
1415         if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
1416                 DEBUGOUT("Advertise 100mb Full duplex\n");
1417                 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1418         }
1419
1420         /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1421         if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1422                 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1423         }
1424
1425         /* Do we want to advertise 1000 Mb Full Duplex? */
1426         if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1427                 DEBUGOUT("Advertise 1000mb Full duplex\n");
1428                 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1429         }
1430
1431         /* Check for a software override of the flow control settings, and
1432          * setup the PHY advertisement registers accordingly.  If
1433          * auto-negotiation is enabled, then software will have to set the
1434          * "PAUSE" bits to the correct value in the Auto-Negotiation
1435          * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1436          *
1437          * The possible values of the "fc" parameter are:
1438          *      0:  Flow control is completely disabled
1439          *      1:  Rx flow control is enabled (we can receive pause frames
1440          *          but not send pause frames).
1441          *      2:  Tx flow control is enabled (we can send pause frames
1442          *          but we do not support receiving pause frames).
1443          *      3:  Both Rx and TX flow control (symmetric) are enabled.
1444          *  other:  No software override.  The flow control configuration
1445          *          in the EEPROM is used.
1446          */
1447         switch (hw->fc) {
1448         case e1000_fc_none: /* 0 */
1449                 /* Flow control (RX & TX) is completely disabled by a
1450                  * software over-ride.
1451                  */
1452                 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1453                 break;
1454         case e1000_fc_rx_pause: /* 1 */
1455                 /* RX Flow control is enabled, and TX Flow control is
1456                  * disabled, by a software over-ride.
1457                  */
1458                 /* Since there really isn't a way to advertise that we are
1459                  * capable of RX Pause ONLY, we will advertise that we
1460                  * support both symmetric and asymmetric RX PAUSE.  Later
1461                  * (in e1000_config_fc_after_link_up) we will disable the
1462                  *hw's ability to send PAUSE frames.
1463                  */
1464                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1465                 break;
1466         case e1000_fc_tx_pause: /* 2 */
1467                 /* TX Flow control is enabled, and RX Flow control is
1468                  * disabled, by a software over-ride.
1469                  */
1470                 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1471                 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1472                 break;
1473         case e1000_fc_full: /* 3 */
1474                 /* Flow control (both RX and TX) is enabled by a software
1475                  * over-ride.
1476                  */
1477                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1478                 break;
1479         default:
1480                 DEBUGOUT("Flow control param set incorrectly\n");
1481                 return -E1000_ERR_CONFIG;
1482         }
1483
1484         if((ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV,
1485                                mii_autoneg_adv_reg)))
1486                 return ret_val;
1487
1488         DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1489
1490         if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg)))
1491                 return ret_val;
1492
1493         return E1000_SUCCESS;
1494 }
1495
1496 /******************************************************************************
1497 * Sets the collision distance in the Transmit Control register
1498 *
1499 * hw - Struct containing variables accessed by shared code
1500 *
1501 * Link should have been established previously. Reads the speed and duplex
1502 * information from the Device Status register.
1503 ******************************************************************************/
1504 static void
1505 e1000_config_collision_dist(struct e1000_hw *hw)
1506 {
1507         uint32_t tctl;
1508
1509         tctl = E1000_READ_REG(hw, TCTL);
1510         
1511         tctl &= ~E1000_TCTL_COLD;
1512         tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1513         
1514         E1000_WRITE_REG(hw, TCTL, tctl);
1515         E1000_WRITE_FLUSH(hw);
1516 }
1517
1518 /******************************************************************************
1519 * Sets MAC speed and duplex settings to reflect the those in the PHY
1520 *
1521 * hw - Struct containing variables accessed by shared code
1522 * mii_reg - data to write to the MII control register
1523 *
1524 * The contents of the PHY register containing the needed information need to
1525 * be passed in.
1526 ******************************************************************************/
1527 static int
1528 e1000_config_mac_to_phy(struct e1000_hw *hw)
1529 {
1530         uint32_t ctrl;
1531         int32_t ret_val;
1532         uint16_t phy_data;
1533
1534         DEBUGFUNC("e1000_config_mac_to_phy");
1535
1536         /* Read the Device Control Register and set the bits to Force Speed
1537          * and Duplex.
1538          */
1539         ctrl = E1000_READ_REG(hw, CTRL);
1540         ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1541         ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1542
1543         /* Set up duplex in the Device Control and Transmit Control
1544          * registers depending on negotiated values.
1545          */
1546         if (hw->phy_type == e1000_phy_igp) {
1547                 if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
1548                                                  &phy_data)))
1549                         return ret_val;
1550
1551                 if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
1552                 else ctrl &= ~E1000_CTRL_FD;
1553
1554                 e1000_config_collision_dist(hw);
1555
1556                 /* Set up speed in the Device Control register depending on
1557                  * negotiated values.
1558                  */
1559                 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1560                    IGP01E1000_PSSR_SPEED_1000MBPS)
1561                         ctrl |= E1000_CTRL_SPD_1000;
1562                 else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
1563                         IGP01E1000_PSSR_SPEED_100MBPS)
1564                         ctrl |= E1000_CTRL_SPD_100;
1565         } else {
1566                 if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
1567                                                  &phy_data)))
1568                         return ret_val;
1569                 
1570                 if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
1571                 else ctrl &= ~E1000_CTRL_FD;
1572
1573                 e1000_config_collision_dist(hw);
1574
1575                 /* Set up speed in the Device Control register depending on
1576                  * negotiated values.
1577                  */
1578                 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1579                         ctrl |= E1000_CTRL_SPD_1000;
1580                 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1581                         ctrl |= E1000_CTRL_SPD_100;
1582         }
1583         /* Write the configured values back to the Device Control Reg. */
1584         E1000_WRITE_REG(hw, CTRL, ctrl);
1585         return E1000_SUCCESS;
1586 }
1587
1588 /******************************************************************************
1589  * Forces the MAC's flow control settings.
1590  * 
1591  * hw - Struct containing variables accessed by shared code
1592  *
1593  * Sets the TFCE and RFCE bits in the device control register to reflect
1594  * the adapter settings. TFCE and RFCE need to be explicitly set by
1595  * software when a Copper PHY is used because autonegotiation is managed
1596  * by the PHY rather than the MAC. Software must also configure these
1597  * bits when link is forced on a fiber connection.
1598  *****************************************************************************/
1599 static int
1600 e1000_force_mac_fc(struct e1000_hw *hw)
1601 {
1602         uint32_t ctrl;
1603         
1604         DEBUGFUNC("e1000_force_mac_fc");
1605         
1606         /* Get the current configuration of the Device Control Register */
1607         ctrl = E1000_READ_REG(hw, CTRL);
1608         
1609         /* Because we didn't get link via the internal auto-negotiation
1610          * mechanism (we either forced link or we got link via PHY
1611          * auto-neg), we have to manually enable/disable transmit an
1612          * receive flow control.
1613          *
1614          * The "Case" statement below enables/disable flow control
1615          * according to the "hw->fc" parameter.
1616          *
1617          * The possible values of the "fc" parameter are:
1618          *      0:  Flow control is completely disabled
1619          *      1:  Rx flow control is enabled (we can receive pause
1620          *          frames but not send pause frames).
1621          *      2:  Tx flow control is enabled (we can send pause frames
1622          *          frames but we do not receive pause frames).
1623          *      3:  Both Rx and TX flow control (symmetric) is enabled.
1624          *  other:  No other values should be possible at this point.
1625          */
1626         
1627         switch (hw->fc) {
1628         case e1000_fc_none:
1629                 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1630                 break;
1631         case e1000_fc_rx_pause:
1632                 ctrl &= (~E1000_CTRL_TFCE);
1633                 ctrl |= E1000_CTRL_RFCE;
1634                 break;
1635         case e1000_fc_tx_pause:
1636                 ctrl &= (~E1000_CTRL_RFCE);
1637                 ctrl |= E1000_CTRL_TFCE;
1638                 break;
1639         case e1000_fc_full:
1640                 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1641                 break;
1642         default:
1643                 DEBUGOUT("Flow control param set incorrectly\n");
1644                 return -E1000_ERR_CONFIG;
1645         }
1646         
1647         /* Disable TX Flow Control for 82542 (rev 2.0) */
1648         if(hw->mac_type == e1000_82542_rev2_0)
1649                 ctrl &= (~E1000_CTRL_TFCE);
1650         
1651         E1000_WRITE_REG(hw, CTRL, ctrl);
1652         return E1000_SUCCESS;
1653 }
1654
1655 /******************************************************************************
1656  * Configures flow control settings after link is established
1657  * 
1658  * hw - Struct containing variables accessed by shared code
1659  *
1660  * Should be called immediately after a valid link has been established.
1661  * Forces MAC flow control settings if link was forced. When in MII/GMII mode
1662  * and autonegotiation is enabled, the MAC flow control settings will be set
1663  * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
1664  * and RFCE bits will be automaticaly set to the negotiated flow control mode.
1665  *****************************************************************************/
1666 static int
1667 e1000_config_fc_after_link_up(struct e1000_hw *hw)
1668 {
1669         int32_t ret_val;
1670         uint16_t mii_status_reg;
1671         uint16_t mii_nway_adv_reg;
1672         uint16_t mii_nway_lp_ability_reg;
1673         uint16_t speed;
1674         uint16_t duplex;
1675         
1676         DEBUGFUNC("e1000_config_fc_after_link_up");
1677         
1678         /* Check for the case where we have fiber media and auto-neg failed
1679          * so we had to force link.  In this case, we need to force the
1680          * configuration of the MAC to match the "fc" parameter.
1681          */
1682         if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
1683            ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed))) { 
1684                 if((ret_val = e1000_force_mac_fc(hw))) {
1685                         DEBUGOUT("Error forcing flow control settings\n");
1686                         return ret_val;
1687                 }
1688         }
1689         
1690         /* Check for the case where we have copper media and auto-neg is
1691          * enabled.  In this case, we need to check and see if Auto-Neg
1692          * has completed, and if so, how the PHY and link partner has
1693          * flow control configured.
1694          */
1695         if(hw->media_type == e1000_media_type_copper) {
1696                 /* Read the MII Status Register and check to see if AutoNeg
1697                  * has completed.  We read this twice because this reg has
1698                  * some "sticky" (latched) bits.
1699                  */
1700                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1701                         return ret_val;
1702                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
1703                         return ret_val;
1704                 
1705                 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
1706                         /* The AutoNeg process has completed, so we now need to
1707                          * read both the Auto Negotiation Advertisement Register
1708                          * (Address 4) and the Auto_Negotiation Base Page Ability
1709                          * Register (Address 5) to determine how flow control was
1710                          * negotiated.
1711                          */
1712                         if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
1713                                                          &mii_nway_adv_reg)))
1714                                 return ret_val;
1715                         if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
1716                                                          &mii_nway_lp_ability_reg)))
1717                                 return ret_val;
1718
1719                         /* Two bits in the Auto Negotiation Advertisement Register
1720                          * (Address 4) and two bits in the Auto Negotiation Base
1721                          * Page Ability Register (Address 5) determine flow control
1722                          * for both the PHY and the link partner.  The following
1723                          * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1724                          * 1999, describes these PAUSE resolution bits and how flow
1725                          * control is determined based upon these settings.
1726                          * NOTE:  DC = Don't Care
1727                          *
1728                          *   LOCAL DEVICE  |   LINK PARTNER
1729                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1730                          *-------|---------|-------|---------|--------------------
1731                          *   0   |    0    |  DC   |   DC    | e1000_fc_none
1732                          *   0   |    1    |   0   |   DC    | e1000_fc_none
1733                          *   0   |    1    |   1   |    0    | e1000_fc_none
1734                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1735                          *   1   |    0    |   0   |   DC    | e1000_fc_none
1736                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
1737                          *   1   |    1    |   0   |    0    | e1000_fc_none
1738                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1739                          *
1740                          */
1741                         /* Are both PAUSE bits set to 1?  If so, this implies
1742                          * Symmetric Flow Control is enabled at both ends.  The
1743                          * ASM_DIR bits are irrelevant per the spec.
1744                          *
1745                          * For Symmetric Flow Control:
1746                          *
1747                          *   LOCAL DEVICE  |   LINK PARTNER
1748                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1749                          *-------|---------|-------|---------|--------------------
1750                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
1751                          *
1752                          */
1753                         if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1754                                 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1755                                 /* Now we need to check if the user selected RX ONLY
1756                                  * of pause frames.  In this case, we had to advertise
1757                                  * FULL flow control because we could not advertise RX
1758                                  * ONLY. Hence, we must now check to see if we need to
1759                                  * turn OFF  the TRANSMISSION of PAUSE frames.
1760                                  */
1761 #if 0
1762                                 if(hw->original_fc == e1000_fc_full) {
1763                                         hw->fc = e1000_fc_full;
1764 #else
1765                                 if(hw->fc == e1000_fc_full) {
1766 #endif
1767                                         DEBUGOUT("Flow Control = FULL.\r\n");
1768                                 } else {
1769                                         hw->fc = e1000_fc_rx_pause;
1770                                         DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1771                                 }
1772                         }
1773                         /* For receiving PAUSE frames ONLY.
1774                          *
1775                          *   LOCAL DEVICE  |   LINK PARTNER
1776                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1777                          *-------|---------|-------|---------|--------------------
1778                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1779                          *
1780                          */
1781                         else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1782                                 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1783                                 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1784                                 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1785                                 hw->fc = e1000_fc_tx_pause;
1786                                 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
1787                         }
1788                         /* For transmitting PAUSE frames ONLY.
1789                          *
1790                          *   LOCAL DEVICE  |   LINK PARTNER
1791                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1792                          *-------|---------|-------|---------|--------------------
1793                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1794                          *
1795                          */
1796                         else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1797                                 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1798                                 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1799                                 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1800                                 hw->fc = e1000_fc_rx_pause;
1801                                 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1802                         }
1803                         /* Per the IEEE spec, at this point flow control should be
1804                          * disabled.  However, we want to consider that we could
1805                          * be connected to a legacy switch that doesn't advertise
1806                          * desired flow control, but can be forced on the link
1807                          * partner.  So if we advertised no flow control, that is
1808                          * what we will resolve to.  If we advertised some kind of
1809                          * receive capability (Rx Pause Only or Full Flow Control)
1810                          * and the link partner advertised none, we will configure
1811                          * ourselves to enable Rx Flow Control only.  We can do
1812                          * this safely for two reasons:  If the link partner really
1813                          * didn't want flow control enabled, and we enable Rx, no
1814                          * harm done since we won't be receiving any PAUSE frames
1815                          * anyway.  If the intent on the link partner was to have
1816                          * flow control enabled, then by us enabling RX only, we
1817                          * can at least receive pause frames and process them.
1818                          * This is a good idea because in most cases, since we are
1819                          * predominantly a server NIC, more times than not we will
1820                          * be asked to delay transmission of packets than asking
1821                          * our link partner to pause transmission of frames.
1822                          */
1823 #if 0
1824                         else if(hw->original_fc == e1000_fc_none ||
1825                                 hw->original_fc == e1000_fc_tx_pause) {
1826 #else
1827                         else if(hw->fc == e1000_fc_none)
1828                                 DEBUGOUT("Flow Control = NONE.\r\n");
1829                         else if(hw->fc == e1000_fc_tx_pause) {
1830 #endif
1831                                 hw->fc = e1000_fc_none;
1832                                 DEBUGOUT("Flow Control = NONE.\r\n");
1833                         } else {
1834                                 hw->fc = e1000_fc_rx_pause;
1835                                 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
1836                         }
1837                         
1838                         /* Now we need to do one last check...  If we auto-
1839                          * negotiated to HALF DUPLEX, flow control should not be
1840                          * enabled per IEEE 802.3 spec.
1841                          */
1842                         e1000_get_speed_and_duplex(hw, &speed, &duplex);
1843                         
1844                         if(duplex == HALF_DUPLEX)
1845                                 hw->fc = e1000_fc_none;
1846                         
1847                         /* Now we call a subroutine to actually force the MAC
1848                          * controller to use the correct flow control settings.
1849                          */
1850                         if((ret_val = e1000_force_mac_fc(hw))) {
1851                                 DEBUGOUT("Error forcing flow control settings\n");
1852                                 return ret_val;
1853                         }
1854                 } else {
1855                         DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
1856                 }
1857         }
1858         return E1000_SUCCESS;
1859 }
1860
1861 /******************************************************************************
1862  * Checks to see if the link status of the hardware has changed.
1863  *
1864  * hw - Struct containing variables accessed by shared code
1865  *
1866  * Called by any function that needs to check the link status of the adapter.
1867  *****************************************************************************/
1868 static int
1869 e1000_check_for_link(struct e1000_hw *hw)
1870 {
1871         uint32_t rxcw;
1872         uint32_t ctrl;
1873         uint32_t status;
1874         uint32_t rctl;
1875         uint32_t signal = 0;
1876         int32_t ret_val;
1877         uint16_t phy_data;
1878         uint16_t lp_capability;
1879         
1880         DEBUGFUNC("e1000_check_for_link");
1881         
1882         /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 
1883          * set when the optics detect a signal. On older adapters, it will be 
1884          * cleared when there is a signal.  This applies to fiber media only.
1885          */
1886         if(hw->media_type == e1000_media_type_fiber)
1887                 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1888
1889         ctrl = E1000_READ_REG(hw, CTRL);
1890         status = E1000_READ_REG(hw, STATUS);
1891         rxcw = E1000_READ_REG(hw, RXCW);
1892         
1893         /* If we have a copper PHY then we only want to go out to the PHY
1894          * registers to see if Auto-Neg has completed and/or if our link
1895          * status has changed.  The get_link_status flag will be set if we
1896          * receive a Link Status Change interrupt or we have Rx Sequence
1897          * Errors.
1898          */
1899 #if 0
1900         if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
1901 #else
1902         if(hw->media_type == e1000_media_type_copper) {
1903 #endif
1904                 /* First we want to see if the MII Status Register reports
1905                  * link.  If so, then we want to get the current speed/duplex
1906                  * of the PHY.
1907                  * Read the register twice since the link bit is sticky.
1908                  */
1909                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1910                         return ret_val;
1911                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1912                         return ret_val;
1913                 
1914                 if(phy_data & MII_SR_LINK_STATUS) {
1915 #if 0
1916                         hw->get_link_status = FALSE;
1917 #endif
1918                 } else {
1919                         /* No link detected */
1920                         return -E1000_ERR_NOLINK;
1921                 }
1922
1923                 /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
1924                  * have Si on board that is 82544 or newer, Auto
1925                  * Speed Detection takes care of MAC speed/duplex
1926                  * configuration.  So we only need to configure Collision
1927                  * Distance in the MAC.  Otherwise, we need to force
1928                  * speed/duplex on the MAC to the current PHY speed/duplex
1929                  * settings.
1930                  */
1931                 if(hw->mac_type >= e1000_82544)
1932                         e1000_config_collision_dist(hw);
1933                 else {
1934                         if((ret_val = e1000_config_mac_to_phy(hw))) {
1935                                 DEBUGOUT("Error configuring MAC to PHY settings\n");
1936                                 return ret_val;
1937                         }
1938                 }
1939                 
1940                 /* Configure Flow Control now that Auto-Neg has completed. First, we 
1941                  * need to restore the desired flow control settings because we may
1942                  * have had to re-autoneg with a different link partner.
1943                  */
1944                 if((ret_val = e1000_config_fc_after_link_up(hw))) {
1945                         DEBUGOUT("Error configuring flow control\n");
1946                         return ret_val;
1947                 }
1948                 
1949                 /* At this point we know that we are on copper and we have
1950                  * auto-negotiated link.  These are conditions for checking the link
1951                  * parter capability register.  We use the link partner capability to
1952                  * determine if TBI Compatibility needs to be turned on or off.  If
1953                  * the link partner advertises any speed in addition to Gigabit, then
1954                  * we assume that they are GMII-based, and TBI compatibility is not
1955                  * needed. If no other speeds are advertised, we assume the link
1956                  * partner is TBI-based, and we turn on TBI Compatibility.
1957                  */
1958                 if(hw->tbi_compatibility_en) {
1959                         if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
1960                                                          &lp_capability)))
1961                                 return ret_val;
1962                         if(lp_capability & (NWAY_LPAR_10T_HD_CAPS |
1963                                 NWAY_LPAR_10T_FD_CAPS |
1964                                 NWAY_LPAR_100TX_HD_CAPS |
1965                                 NWAY_LPAR_100TX_FD_CAPS |
1966                                 NWAY_LPAR_100T4_CAPS)) {
1967                                 /* If our link partner advertises anything in addition to 
1968                                  * gigabit, we do not need to enable TBI compatibility.
1969                                  */
1970                                 if(hw->tbi_compatibility_on) {
1971                                         /* If we previously were in the mode, turn it off. */
1972                                         rctl = E1000_READ_REG(hw, RCTL);
1973                                         rctl &= ~E1000_RCTL_SBP;
1974                                         E1000_WRITE_REG(hw, RCTL, rctl);
1975                                         hw->tbi_compatibility_on = FALSE;
1976                                 }
1977                         } else {
1978                                 /* If TBI compatibility is was previously off, turn it on. For
1979                                  * compatibility with a TBI link partner, we will store bad
1980                                  * packets. Some frames have an additional byte on the end and
1981                                  * will look like CRC errors to to the hardware.
1982                                  */
1983                                 if(!hw->tbi_compatibility_on) {
1984                                         hw->tbi_compatibility_on = TRUE;
1985                                         rctl = E1000_READ_REG(hw, RCTL);
1986                                         rctl |= E1000_RCTL_SBP;
1987                                         E1000_WRITE_REG(hw, RCTL, rctl);
1988                                 }
1989                         }
1990                 }
1991         }
1992         /* If we don't have link (auto-negotiation failed or link partner cannot
1993          * auto-negotiate), the cable is plugged in (we have signal), and our
1994          * link partner is not trying to auto-negotiate with us (we are receiving
1995          * idles or data), we need to force link up. We also need to give
1996          * auto-negotiation time to complete, in case the cable was just plugged
1997          * in. The autoneg_failed flag does this.
1998          */
1999         else if((((hw->media_type == e1000_media_type_fiber) &&
2000                 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
2001                 (hw->media_type == e1000_media_type_internal_serdes)) &&
2002                 (!(status & E1000_STATUS_LU)) &&
2003                 (!(rxcw & E1000_RXCW_C))) {
2004                 if(hw->autoneg_failed == 0) {
2005                         hw->autoneg_failed = 1;
2006                         return 0;
2007                 }
2008                 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
2009                 
2010                 /* Disable auto-negotiation in the TXCW register */
2011                 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2012                 
2013                 /* Force link-up and also force full-duplex. */
2014                 ctrl = E1000_READ_REG(hw, CTRL);
2015                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2016                 E1000_WRITE_REG(hw, CTRL, ctrl);
2017                 
2018                 /* Configure Flow Control after forcing link up. */
2019                 if((ret_val = e1000_config_fc_after_link_up(hw))) {
2020                         DEBUGOUT("Error configuring flow control\n");
2021                         return ret_val;
2022                 }
2023         }
2024         /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2025          * auto-negotiation in the TXCW register and disable forced link in the
2026          * Device Control register in an attempt to auto-negotiate with our link
2027          * partner.
2028          */
2029         else if(((hw->media_type == e1000_media_type_fiber)  ||
2030                  (hw->media_type == e1000_media_type_internal_serdes)) &&
2031                 (ctrl & E1000_CTRL_SLU) &&
2032                 (rxcw & E1000_RXCW_C)) {
2033                 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
2034                 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2035                 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2036         }
2037 #if 0
2038         /* If we force link for non-auto-negotiation switch, check link status
2039          * based on MAC synchronization for internal serdes media type.
2040          */
2041         else if((hw->media_type == e1000_media_type_internal_serdes) &&
2042                         !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2043                 /* SYNCH bit and IV bit are sticky. */
2044                 udelay(10);
2045                 if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
2046                         if(!(rxcw & E1000_RXCW_IV)) {
2047                                 hw->serdes_link_down = FALSE;
2048                                 DEBUGOUT("SERDES: Link is up.\n");
2049                         }
2050                 } else {
2051                         hw->serdes_link_down = TRUE;
2052                         DEBUGOUT("SERDES: Link is down.\n");
2053                 }
2054         }
2055 #endif
2056         return E1000_SUCCESS;
2057 }
2058
2059 /******************************************************************************
2060  * Detects the current speed and duplex settings of the hardware.
2061  *
2062  * hw - Struct containing variables accessed by shared code
2063  * speed - Speed of the connection
2064  * duplex - Duplex setting of the connection
2065  *****************************************************************************/
2066 static void 
2067 e1000_get_speed_and_duplex(struct e1000_hw *hw,
2068                            uint16_t *speed,
2069                            uint16_t *duplex)
2070 {
2071         uint32_t status;
2072         
2073         DEBUGFUNC("e1000_get_speed_and_duplex");
2074         
2075         if(hw->mac_type >= e1000_82543) {
2076                 status = E1000_READ_REG(hw, STATUS);
2077                 if(status & E1000_STATUS_SPEED_1000) {
2078                         *speed = SPEED_1000;
2079                         DEBUGOUT("1000 Mbs, ");
2080                 } else if(status & E1000_STATUS_SPEED_100) {
2081                         *speed = SPEED_100;
2082                         DEBUGOUT("100 Mbs, ");
2083                 } else {
2084                         *speed = SPEED_10;
2085                         DEBUGOUT("10 Mbs, ");
2086                 }
2087                 
2088                 if(status & E1000_STATUS_FD) {
2089                         *duplex = FULL_DUPLEX;
2090                         DEBUGOUT("Full Duplex\r\n");
2091                 } else {
2092                         *duplex = HALF_DUPLEX;
2093                         DEBUGOUT(" Half Duplex\r\n");
2094                 }
2095         } else {
2096                 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
2097                 *speed = SPEED_1000;
2098                 *duplex = FULL_DUPLEX;
2099         }
2100 }
2101
2102 /******************************************************************************
2103 * Blocks until autoneg completes or times out (~4.5 seconds)
2104 *
2105 * hw - Struct containing variables accessed by shared code
2106 ******************************************************************************/
2107 static int
2108 e1000_wait_autoneg(struct e1000_hw *hw)
2109 {
2110         int32_t ret_val;
2111         uint16_t i;
2112         uint16_t phy_data;
2113         
2114         DEBUGFUNC("e1000_wait_autoneg");
2115         DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2116         
2117         /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2118         for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2119                 /* Read the MII Status Register and wait for Auto-Neg
2120                  * Complete bit to be set.
2121                  */
2122                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2123                         return ret_val;
2124                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2125                         return ret_val;
2126                 if(phy_data & MII_SR_AUTONEG_COMPLETE) {
2127                         DEBUGOUT("Auto-Neg complete.\n");
2128                         return E1000_SUCCESS;
2129                 }
2130                 mdelay(100);
2131         }
2132         DEBUGOUT("Auto-Neg timedout.\n");
2133         return -E1000_ERR_TIMEOUT;
2134 }
2135
2136 /******************************************************************************
2137 * Raises the Management Data Clock
2138 *
2139 * hw - Struct containing variables accessed by shared code
2140 * ctrl - Device control register's current value
2141 ******************************************************************************/
2142 static void
2143 e1000_raise_mdi_clk(struct e1000_hw *hw,
2144                     uint32_t *ctrl)
2145 {
2146         /* Raise the clock input to the Management Data Clock (by setting the MDC
2147          * bit), and then delay 10 microseconds.
2148          */
2149         E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
2150         E1000_WRITE_FLUSH(hw);
2151         udelay(10);
2152 }
2153
2154 /******************************************************************************
2155 * Lowers the Management Data Clock
2156 *
2157 * hw - Struct containing variables accessed by shared code
2158 * ctrl - Device control register's current value
2159 ******************************************************************************/
2160 static void
2161 e1000_lower_mdi_clk(struct e1000_hw *hw,
2162                     uint32_t *ctrl)
2163 {
2164         /* Lower the clock input to the Management Data Clock (by clearing the MDC
2165          * bit), and then delay 10 microseconds.
2166          */
2167         E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2168         E1000_WRITE_FLUSH(hw);
2169         udelay(10);
2170 }
2171
2172 /******************************************************************************
2173 * Shifts data bits out to the PHY
2174 *
2175 * hw - Struct containing variables accessed by shared code
2176 * data - Data to send out to the PHY
2177 * count - Number of bits to shift out
2178 *
2179 * Bits are shifted out in MSB to LSB order.
2180 ******************************************************************************/
2181 static void
2182 e1000_shift_out_mdi_bits(struct e1000_hw *hw,
2183                          uint32_t data,
2184                          uint16_t count)
2185 {
2186         uint32_t ctrl;
2187         uint32_t mask;
2188
2189         /* We need to shift "count" number of bits out to the PHY. So, the value
2190          * in the "data" parameter will be shifted out to the PHY one bit at a 
2191          * time. In order to do this, "data" must be broken down into bits.
2192          */
2193         mask = 0x01;
2194         mask <<= (count - 1);
2195         
2196         ctrl = E1000_READ_REG(hw, CTRL);
2197         
2198         /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2199         ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2200         
2201         while(mask) {
2202                 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2203                  * then raising and lowering the Management Data Clock. A "0" is
2204                  * shifted out to the PHY by setting the MDIO bit to "0" and then
2205                  * raising and lowering the clock.
2206                  */
2207                 if(data & mask) ctrl |= E1000_CTRL_MDIO;
2208                 else ctrl &= ~E1000_CTRL_MDIO;
2209                 
2210                 E1000_WRITE_REG(hw, CTRL, ctrl);
2211                 E1000_WRITE_FLUSH(hw);
2212                 
2213                 udelay(10);
2214
2215                 e1000_raise_mdi_clk(hw, &ctrl);
2216                 e1000_lower_mdi_clk(hw, &ctrl);
2217
2218                 mask = mask >> 1;
2219         }
2220 }
2221
2222 /******************************************************************************
2223 * Shifts data bits in from the PHY
2224 *
2225 * hw - Struct containing variables accessed by shared code
2226 *
2227 * Bits are shifted in in MSB to LSB order. 
2228 ******************************************************************************/
2229 static uint16_t
2230 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2231 {
2232         uint32_t ctrl;
2233         uint16_t data = 0;
2234         uint8_t i;
2235
2236         /* In order to read a register from the PHY, we need to shift in a total
2237          * of 18 bits from the PHY. The first two bit (turnaround) times are used
2238          * to avoid contention on the MDIO pin when a read operation is performed.
2239          * These two bits are ignored by us and thrown away. Bits are "shifted in"
2240          * by raising the input to the Management Data Clock (setting the MDC bit),
2241          * and then reading the value of the MDIO bit.
2242          */ 
2243         ctrl = E1000_READ_REG(hw, CTRL);
2244         
2245         /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2246         ctrl &= ~E1000_CTRL_MDIO_DIR;
2247         ctrl &= ~E1000_CTRL_MDIO;
2248         
2249         E1000_WRITE_REG(hw, CTRL, ctrl);
2250         E1000_WRITE_FLUSH(hw);
2251         
2252         /* Raise and Lower the clock before reading in the data. This accounts for
2253          * the turnaround bits. The first clock occurred when we clocked out the
2254          * last bit of the Register Address.
2255          */
2256         e1000_raise_mdi_clk(hw, &ctrl);
2257         e1000_lower_mdi_clk(hw, &ctrl);
2258         
2259         for(data = 0, i = 0; i < 16; i++) {
2260                 data = data << 1;
2261                 e1000_raise_mdi_clk(hw, &ctrl);
2262                 ctrl = E1000_READ_REG(hw, CTRL);
2263                 /* Check to see if we shifted in a "1". */
2264                 if(ctrl & E1000_CTRL_MDIO) data |= 1;
2265                 e1000_lower_mdi_clk(hw, &ctrl);
2266         }
2267         
2268         e1000_raise_mdi_clk(hw, &ctrl);
2269         e1000_lower_mdi_clk(hw, &ctrl);
2270         
2271         return data;
2272 }
2273
2274 /*****************************************************************************
2275 * Reads the value from a PHY register, if the value is on a specific non zero
2276 * page, sets the page first.
2277 *
2278 * hw - Struct containing variables accessed by shared code
2279 * reg_addr - address of the PHY register to read
2280 ******************************************************************************/
2281 static int
2282 e1000_read_phy_reg(struct e1000_hw *hw,
2283                    uint32_t reg_addr,
2284                    uint16_t *phy_data)
2285 {
2286         uint32_t ret_val;
2287
2288         DEBUGFUNC("e1000_read_phy_reg");
2289
2290         if(hw->phy_type == e1000_phy_igp &&
2291            (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2292                 if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2293                                                      (uint16_t)reg_addr)))
2294                         return ret_val;
2295         }
2296
2297         ret_val = e1000_read_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2298                                         phy_data);
2299
2300         return ret_val;
2301 }
2302
2303 static int
2304 e1000_read_phy_reg_ex(struct e1000_hw *hw,
2305                       uint32_t reg_addr,
2306                       uint16_t *phy_data)
2307 {
2308         uint32_t i;
2309         uint32_t mdic = 0;
2310         const uint32_t phy_addr = 1;
2311
2312         DEBUGFUNC("e1000_read_phy_reg_ex");
2313         
2314         if(reg_addr > MAX_PHY_REG_ADDRESS) {
2315                 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2316                 return -E1000_ERR_PARAM;
2317         }
2318         
2319         if(hw->mac_type > e1000_82543) {
2320                 /* Set up Op-code, Phy Address, and register address in the MDI
2321                  * Control register.  The MAC will take care of interfacing with the
2322                  * PHY to retrieve the desired data.
2323                  */
2324                 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2325                         (phy_addr << E1000_MDIC_PHY_SHIFT) | 
2326                         (E1000_MDIC_OP_READ));
2327                 
2328                 E1000_WRITE_REG(hw, MDIC, mdic);
2329
2330                 /* Poll the ready bit to see if the MDI read completed */
2331                 for(i = 0; i < 64; i++) {
2332                         udelay(50);
2333                         mdic = E1000_READ_REG(hw, MDIC);
2334                         if(mdic & E1000_MDIC_READY) break;
2335                 }
2336                 if(!(mdic & E1000_MDIC_READY)) {
2337                         DEBUGOUT("MDI Read did not complete\n");
2338                         return -E1000_ERR_PHY;
2339                 }
2340                 if(mdic & E1000_MDIC_ERROR) {
2341                         DEBUGOUT("MDI Error\n");
2342                         return -E1000_ERR_PHY;
2343                 }
2344                 *phy_data = (uint16_t) mdic;
2345         } else {
2346                 /* We must first send a preamble through the MDIO pin to signal the
2347                  * beginning of an MII instruction.  This is done by sending 32
2348                  * consecutive "1" bits.
2349                  */
2350                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2351                 
2352                 /* Now combine the next few fields that are required for a read
2353                  * operation.  We use this method instead of calling the
2354                  * e1000_shift_out_mdi_bits routine five different times. The format of
2355                  * a MII read instruction consists of a shift out of 14 bits and is
2356                  * defined as follows:
2357                  *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2358                  * followed by a shift in of 18 bits.  This first two bits shifted in
2359                  * are TurnAround bits used to avoid contention on the MDIO pin when a
2360                  * READ operation is performed.  These two bits are thrown away
2361                  * followed by a shift in of 16 bits which contains the desired data.
2362                  */
2363                 mdic = ((reg_addr) | (phy_addr << 5) | 
2364                         (PHY_OP_READ << 10) | (PHY_SOF << 12));
2365                 
2366                 e1000_shift_out_mdi_bits(hw, mdic, 14);
2367                 
2368                 /* Now that we've shifted out the read command to the MII, we need to
2369                  * "shift in" the 16-bit value (18 total bits) of the requested PHY
2370                  * register address.
2371                  */
2372                 *phy_data = e1000_shift_in_mdi_bits(hw);
2373         }
2374         return E1000_SUCCESS;
2375 }
2376
2377 /******************************************************************************
2378 * Writes a value to a PHY register
2379 *
2380 * hw - Struct containing variables accessed by shared code
2381 * reg_addr - address of the PHY register to write
2382 * data - data to write to the PHY
2383 ******************************************************************************/
2384 static int 
2385 e1000_write_phy_reg(struct e1000_hw *hw,
2386                     uint32_t reg_addr,
2387                     uint16_t phy_data)
2388 {
2389         uint32_t ret_val;
2390
2391         DEBUGFUNC("e1000_write_phy_reg");
2392
2393         if(hw->phy_type == e1000_phy_igp &&
2394            (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2395                 if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2396                                                      (uint16_t)reg_addr)))
2397                         return ret_val;
2398         }
2399
2400         ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2401                                          phy_data);
2402
2403         return ret_val;
2404 }
2405
2406 static int
2407 e1000_write_phy_reg_ex(struct e1000_hw *hw,
2408                        uint32_t reg_addr,
2409                        uint16_t phy_data)
2410 {
2411         uint32_t i;
2412         uint32_t mdic = 0;
2413         const uint32_t phy_addr = 1;
2414         
2415         DEBUGFUNC("e1000_write_phy_reg_ex");
2416         
2417         if(reg_addr > MAX_PHY_REG_ADDRESS) {
2418                 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2419                 return -E1000_ERR_PARAM;
2420         }
2421         
2422         if(hw->mac_type > e1000_82543) {
2423                 /* Set up Op-code, Phy Address, register address, and data intended
2424                  * for the PHY register in the MDI Control register.  The MAC will take
2425                  * care of interfacing with the PHY to send the desired data.
2426                  */
2427                 mdic = (((uint32_t) phy_data) |
2428                         (reg_addr << E1000_MDIC_REG_SHIFT) |
2429                         (phy_addr << E1000_MDIC_PHY_SHIFT) | 
2430                         (E1000_MDIC_OP_WRITE));
2431                 
2432                 E1000_WRITE_REG(hw, MDIC, mdic);
2433                 
2434                 /* Poll the ready bit to see if the MDI read completed */
2435                 for(i = 0; i < 640; i++) {
2436                         udelay(5);
2437                         mdic = E1000_READ_REG(hw, MDIC);
2438                         if(mdic & E1000_MDIC_READY) break;
2439                 }
2440                 if(!(mdic & E1000_MDIC_READY)) {
2441                         DEBUGOUT("MDI Write did not complete\n");
2442                         return -E1000_ERR_PHY;
2443                 }
2444         } else {
2445                 /* We'll need to use the SW defined pins to shift the write command
2446                  * out to the PHY. We first send a preamble to the PHY to signal the
2447                  * beginning of the MII instruction.  This is done by sending 32 
2448                  * consecutive "1" bits.
2449                  */
2450                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2451                 
2452                 /* Now combine the remaining required fields that will indicate a 
2453                  * write operation. We use this method instead of calling the
2454                  * e1000_shift_out_mdi_bits routine for each field in the command. The
2455                  * format of a MII write instruction is as follows:
2456                  * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2457                  */
2458                 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
2459                         (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
2460                 mdic <<= 16;
2461                 mdic |= (uint32_t) phy_data;
2462                 
2463                 e1000_shift_out_mdi_bits(hw, mdic, 32);
2464         }
2465
2466         return E1000_SUCCESS;
2467 }
2468
2469 /******************************************************************************
2470 * Returns the PHY to the power-on reset state
2471 *
2472 * hw - Struct containing variables accessed by shared code
2473 ******************************************************************************/
2474 static void
2475 e1000_phy_hw_reset(struct e1000_hw *hw)
2476 {
2477         uint32_t ctrl, ctrl_ext;
2478
2479         DEBUGFUNC("e1000_phy_hw_reset");
2480         
2481         DEBUGOUT("Resetting Phy...\n");
2482         
2483         if(hw->mac_type > e1000_82543) {
2484                 /* Read the device control register and assert the E1000_CTRL_PHY_RST
2485                  * bit. Then, take it out of reset.
2486                  */
2487                 ctrl = E1000_READ_REG(hw, CTRL);
2488                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
2489                 E1000_WRITE_FLUSH(hw);
2490                 mdelay(10);
2491                 E1000_WRITE_REG(hw, CTRL, ctrl);
2492                 E1000_WRITE_FLUSH(hw);
2493         } else {
2494                 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
2495                  * bit to put the PHY into reset. Then, take it out of reset.
2496                  */
2497                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
2498                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
2499                 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
2500                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2501                 E1000_WRITE_FLUSH(hw);
2502                 mdelay(10);
2503                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
2504                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
2505                 E1000_WRITE_FLUSH(hw);
2506         }
2507         udelay(150);
2508 }
2509
2510 /******************************************************************************
2511 * Resets the PHY
2512 *
2513 * hw - Struct containing variables accessed by shared code
2514 *
2515 * Sets bit 15 of the MII Control regiser
2516 ******************************************************************************/
2517 static int 
2518 e1000_phy_reset(struct e1000_hw *hw)
2519 {
2520         int32_t ret_val;
2521         uint16_t phy_data;
2522
2523         DEBUGFUNC("e1000_phy_reset");
2524
2525         if(hw->mac_type != e1000_82541_rev_2) {
2526                 if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
2527                         return ret_val;
2528                 
2529                 phy_data |= MII_CR_RESET;
2530                 if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
2531                         return ret_val;
2532                 
2533                 udelay(1);
2534         } else e1000_phy_hw_reset(hw);
2535
2536         if(hw->phy_type == e1000_phy_igp)
2537                 e1000_phy_init_script(hw);
2538
2539         return E1000_SUCCESS;
2540 }
2541
2542 /******************************************************************************
2543 * Probes the expected PHY address for known PHY IDs
2544 *
2545 * hw - Struct containing variables accessed by shared code
2546 ******************************************************************************/
2547 static int
2548 e1000_detect_gig_phy(struct e1000_hw *hw)
2549 {
2550         int32_t phy_init_status, ret_val;
2551         uint16_t phy_id_high, phy_id_low;
2552         boolean_t match = FALSE;
2553
2554         DEBUGFUNC("e1000_detect_gig_phy");
2555         
2556         /* Read the PHY ID Registers to identify which PHY is onboard. */
2557         if((ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high)))
2558                 return ret_val;
2559
2560         hw->phy_id = (uint32_t) (phy_id_high << 16);
2561         udelay(20);
2562         if((ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low)))
2563                 return ret_val;
2564         
2565         hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
2566 #ifdef LINUX_DRIVER
2567         hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
2568 #endif
2569         
2570         switch(hw->mac_type) {
2571         case e1000_82543:
2572                 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
2573                 break;
2574         case e1000_82544:
2575                 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
2576                 break;
2577         case e1000_82540:
2578         case e1000_82545:
2579         case e1000_82545_rev_3:
2580         case e1000_82546:
2581         case e1000_82546_rev_3:
2582                 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
2583                 break;
2584         case e1000_82541:
2585         case e1000_82541_rev_2:
2586         case e1000_82547:
2587         case e1000_82547_rev_2:
2588                 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
2589                 break;
2590         default:
2591                 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
2592                 return -E1000_ERR_CONFIG;
2593         }
2594         phy_init_status = e1000_set_phy_type(hw);
2595
2596         if ((match) && (phy_init_status == E1000_SUCCESS)) {
2597                 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
2598                 return E1000_SUCCESS;
2599         }
2600         DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
2601         return -E1000_ERR_PHY;
2602 }
2603
2604 /******************************************************************************
2605  * Sets up eeprom variables in the hw struct.  Must be called after mac_type
2606  * is configured.
2607  *
2608  * hw - Struct containing variables accessed by shared code
2609  *****************************************************************************/
2610 static void
2611 e1000_init_eeprom_params(struct e1000_hw *hw)
2612 {
2613         struct e1000_eeprom_info *eeprom = &hw->eeprom;
2614         uint32_t eecd = E1000_READ_REG(hw, EECD);
2615         uint16_t eeprom_size;
2616
2617         DEBUGFUNC("e1000_init_eeprom_params");
2618
2619         switch (hw->mac_type) {
2620         case e1000_82542_rev2_0:
2621         case e1000_82542_rev2_1:
2622         case e1000_82543:
2623         case e1000_82544:
2624                 eeprom->type = e1000_eeprom_microwire;
2625                 eeprom->word_size = 64;
2626                 eeprom->opcode_bits = 3;
2627                 eeprom->address_bits = 6;
2628                 eeprom->delay_usec = 50;
2629                 break;
2630         case e1000_82540:
2631         case e1000_82545:
2632         case e1000_82545_rev_3:
2633         case e1000_82546:
2634         case e1000_82546_rev_3:
2635                 eeprom->type = e1000_eeprom_microwire;
2636                 eeprom->opcode_bits = 3;
2637                 eeprom->delay_usec = 50;
2638                 if(eecd & E1000_EECD_SIZE) {
2639                         eeprom->word_size = 256;
2640                         eeprom->address_bits = 8;
2641                 } else {
2642                         eeprom->word_size = 64;
2643                         eeprom->address_bits = 6;
2644                 }
2645                 break;
2646         case e1000_82541:
2647         case e1000_82541_rev_2:
2648         case e1000_82547:
2649         case e1000_82547_rev_2:
2650                 if (eecd & E1000_EECD_TYPE) {
2651                         eeprom->type = e1000_eeprom_spi;
2652                         if (eecd & E1000_EECD_ADDR_BITS) {
2653                                 eeprom->page_size = 32;
2654                                 eeprom->address_bits = 16;
2655                         } else {
2656                                 eeprom->page_size = 8;
2657                                 eeprom->address_bits = 8;
2658                         }
2659                 } else {
2660                         eeprom->type = e1000_eeprom_microwire;
2661                         eeprom->opcode_bits = 3;
2662                         eeprom->delay_usec = 50;
2663                         if (eecd & E1000_EECD_ADDR_BITS) {
2664                                 eeprom->word_size = 256;
2665                                 eeprom->address_bits = 8;
2666                         } else {
2667                                 eeprom->word_size = 64;
2668                                 eeprom->address_bits = 6;
2669                         }
2670                 }
2671                 break;
2672         default:
2673                 eeprom->type = e1000_eeprom_spi;
2674                 if (eecd & E1000_EECD_ADDR_BITS) {
2675                         eeprom->page_size = 32;
2676                         eeprom->address_bits = 16;
2677                 } else {
2678                         eeprom->page_size = 8;
2679                         eeprom->address_bits = 8;
2680                 }
2681                 break;
2682         }
2683
2684         if (eeprom->type == e1000_eeprom_spi) {
2685                 eeprom->opcode_bits = 8;
2686                 eeprom->delay_usec = 1;
2687                 eeprom->word_size = 64;
2688                 if (e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) {
2689                         eeprom_size &= EEPROM_SIZE_MASK;
2690
2691                         switch (eeprom_size) {
2692                         case EEPROM_SIZE_16KB:
2693                                 eeprom->word_size = 8192;
2694                                 break;
2695                         case EEPROM_SIZE_8KB:
2696                                 eeprom->word_size = 4096;
2697                                 break;
2698                         case EEPROM_SIZE_4KB:
2699                                 eeprom->word_size = 2048;
2700                                 break;
2701                         case EEPROM_SIZE_2KB:
2702                                 eeprom->word_size = 1024;
2703                                 break;
2704                         case EEPROM_SIZE_1KB:
2705                                 eeprom->word_size = 512;
2706                                 break;
2707                         case EEPROM_SIZE_512B:
2708                                 eeprom->word_size = 256;
2709                                 break;
2710                         case EEPROM_SIZE_128B:
2711                         default:
2712                                 break;
2713                         }
2714                 }
2715         }
2716 }
2717
2718 /******************************************************************************
2719  * Raises the EEPROM's clock input.
2720  *
2721  * hw - Struct containing variables accessed by shared code
2722  * eecd - EECD's current value
2723  *****************************************************************************/
2724 static void
2725 e1000_raise_ee_clk(struct e1000_hw *hw,
2726                    uint32_t *eecd)
2727 {
2728         /* Raise the clock input to the EEPROM (by setting the SK bit), and then
2729          * wait <delay> microseconds.
2730          */
2731         *eecd = *eecd | E1000_EECD_SK;
2732         E1000_WRITE_REG(hw, EECD, *eecd);
2733         E1000_WRITE_FLUSH(hw);
2734         udelay(hw->eeprom.delay_usec);
2735 }
2736
2737 /******************************************************************************
2738  * Lowers the EEPROM's clock input.
2739  *
2740  * hw - Struct containing variables accessed by shared code 
2741  * eecd - EECD's current value
2742  *****************************************************************************/
2743 static void
2744 e1000_lower_ee_clk(struct e1000_hw *hw,
2745                    uint32_t *eecd)
2746 {
2747         /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 
2748          * wait 50 microseconds. 
2749          */
2750         *eecd = *eecd & ~E1000_EECD_SK;
2751         E1000_WRITE_REG(hw, EECD, *eecd);
2752         E1000_WRITE_FLUSH(hw);
2753         udelay(hw->eeprom.delay_usec);
2754 }
2755
2756 /******************************************************************************
2757  * Shift data bits out to the EEPROM.
2758  *
2759  * hw - Struct containing variables accessed by shared code
2760  * data - data to send to the EEPROM
2761  * count - number of bits to shift out
2762  *****************************************************************************/
2763 static void
2764 e1000_shift_out_ee_bits(struct e1000_hw *hw,
2765                         uint16_t data,
2766                         uint16_t count)
2767 {
2768         struct e1000_eeprom_info *eeprom = &hw->eeprom;
2769         uint32_t eecd;
2770         uint32_t mask;
2771         
2772         /* We need to shift "count" bits out to the EEPROM. So, value in the
2773          * "data" parameter will be shifted out to the EEPROM one bit at a time.
2774          * In order to do this, "data" must be broken down into bits. 
2775          */
2776         mask = 0x01 << (count - 1);
2777         eecd = E1000_READ_REG(hw, EECD);
2778         if (eeprom->type == e1000_eeprom_microwire) {
2779                 eecd &= ~E1000_EECD_DO;
2780         } else if (eeprom->type == e1000_eeprom_spi) {
2781                 eecd |= E1000_EECD_DO;
2782         }
2783         do {
2784                 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
2785                  * and then raising and then lowering the clock (the SK bit controls
2786                  * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
2787                  * by setting "DI" to "0" and then raising and then lowering the clock.
2788                  */
2789                 eecd &= ~E1000_EECD_DI;
2790                 
2791                 if(data & mask)
2792                         eecd |= E1000_EECD_DI;
2793                 
2794                 E1000_WRITE_REG(hw, EECD, eecd);
2795                 E1000_WRITE_FLUSH(hw);
2796                 
2797                 udelay(eeprom->delay_usec);
2798                 
2799                 e1000_raise_ee_clk(hw, &eecd);
2800                 e1000_lower_ee_clk(hw, &eecd);
2801                 
2802                 mask = mask >> 1;
2803                 
2804         } while(mask);
2805
2806         /* We leave the "DI" bit set to "0" when we leave this routine. */
2807         eecd &= ~E1000_EECD_DI;
2808         E1000_WRITE_REG(hw, EECD, eecd);
2809 }
2810
2811 /******************************************************************************
2812  * Shift data bits in from the EEPROM
2813  *
2814  * hw - Struct containing variables accessed by shared code
2815  *****************************************************************************/
2816 static uint16_t
2817 e1000_shift_in_ee_bits(struct e1000_hw *hw,
2818                        uint16_t count)
2819 {
2820         uint32_t eecd;
2821         uint32_t i;
2822         uint16_t data;
2823         
2824         /* In order to read a register from the EEPROM, we need to shift 'count' 
2825          * bits in from the EEPROM. Bits are "shifted in" by raising the clock
2826          * input to the EEPROM (setting the SK bit), and then reading the value of
2827          * the "DO" bit.  During this "shifting in" process the "DI" bit should
2828          * always be clear.
2829          */
2830         
2831         eecd = E1000_READ_REG(hw, EECD);
2832         
2833         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
2834         data = 0;
2835         
2836         for(i = 0; i < count; i++) {
2837                 data = data << 1;
2838                 e1000_raise_ee_clk(hw, &eecd);
2839                 
2840                 eecd = E1000_READ_REG(hw, EECD);
2841                 
2842                 eecd &= ~(E1000_EECD_DI);
2843                 if(eecd & E1000_EECD_DO)
2844                         data |= 1;
2845                 
2846                 e1000_lower_ee_clk(hw, &eecd);
2847         }
2848         
2849         return data;
2850 }
2851
2852 /******************************************************************************
2853  * Prepares EEPROM for access
2854  *
2855  * hw - Struct containing variables accessed by shared code
2856  *
2857  * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 
2858  * function should be called before issuing a command to the EEPROM.
2859  *****************************************************************************/
2860 static int32_t
2861 e1000_acquire_eeprom(struct e1000_hw *hw)
2862 {
2863         struct e1000_eeprom_info *eeprom = &hw->eeprom;
2864         uint32_t eecd, i=0;
2865
2866         eecd = E1000_READ_REG(hw, EECD);
2867
2868         /* Request EEPROM Access */
2869         if(hw->mac_type > e1000_82544) {
2870                 eecd |= E1000_EECD_REQ;
2871                 E1000_WRITE_REG(hw, EECD, eecd);
2872                 eecd = E1000_READ_REG(hw, EECD);
2873                 while((!(eecd & E1000_EECD_GNT)) &&
2874                       (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
2875                         i++;
2876                         udelay(5);
2877                         eecd = E1000_READ_REG(hw, EECD);
2878                 }
2879                 if(!(eecd & E1000_EECD_GNT)) {
2880                         eecd &= ~E1000_EECD_REQ;
2881                         E1000_WRITE_REG(hw, EECD, eecd);
2882                         DEBUGOUT("Could not acquire EEPROM grant\n");
2883                         return -E1000_ERR_EEPROM;
2884                 }
2885         }
2886
2887         /* Setup EEPROM for Read/Write */
2888
2889         if (eeprom->type == e1000_eeprom_microwire) {
2890                 /* Clear SK and DI */
2891                 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
2892                 E1000_WRITE_REG(hw, EECD, eecd);
2893
2894                 /* Set CS */
2895                 eecd |= E1000_EECD_CS;
2896                 E1000_WRITE_REG(hw, EECD, eecd);
2897         } else if (eeprom->type == e1000_eeprom_spi) {
2898                 /* Clear SK and CS */
2899                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
2900                 E1000_WRITE_REG(hw, EECD, eecd);
2901                 udelay(1);
2902         }
2903
2904         return E1000_SUCCESS;
2905 }
2906
2907 /******************************************************************************
2908  * Returns EEPROM to a "standby" state
2909  * 
2910  * hw - Struct containing variables accessed by shared code
2911  *****************************************************************************/
2912 static void
2913 e1000_standby_eeprom(struct e1000_hw *hw)
2914 {
2915         struct e1000_eeprom_info *eeprom = &hw->eeprom;
2916         uint32_t eecd;
2917         
2918         eecd = E1000_READ_REG(hw, EECD);
2919
2920         if(eeprom->type == e1000_eeprom_microwire) {
2921
2922                 /* Deselect EEPROM */
2923                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
2924                 E1000_WRITE_REG(hw, EECD, eecd);
2925                 E1000_WRITE_FLUSH(hw);
2926                 udelay(eeprom->delay_usec);
2927         
2928                 /* Clock high */
2929                 eecd |= E1000_EECD_SK;
2930                 E1000_WRITE_REG(hw, EECD, eecd);
2931                 E1000_WRITE_FLUSH(hw);
2932                 udelay(eeprom->delay_usec);
2933         
2934                 /* Select EEPROM */
2935                 eecd |= E1000_EECD_CS;
2936                 E1000_WRITE_REG(hw, EECD, eecd);
2937                 E1000_WRITE_FLUSH(hw);
2938                 udelay(eeprom->delay_usec);
2939
2940                 /* Clock low */
2941                 eecd &= ~E1000_EECD_SK;
2942                 E1000_WRITE_REG(hw, EECD, eecd);
2943                 E1000_WRITE_FLUSH(hw);
2944                 udelay(eeprom->delay_usec);
2945         } else if(eeprom->type == e1000_eeprom_spi) {
2946                 /* Toggle CS to flush commands */
2947                 eecd |= E1000_EECD_CS;
2948                 E1000_WRITE_REG(hw, EECD, eecd);
2949                 E1000_WRITE_FLUSH(hw);
2950                 udelay(eeprom->delay_usec);
2951                 eecd &= ~E1000_EECD_CS;
2952                 E1000_WRITE_REG(hw, EECD, eecd);
2953                 E1000_WRITE_FLUSH(hw);
2954                 udelay(eeprom->delay_usec);
2955         }
2956 }
2957
2958 /******************************************************************************
2959  * Terminates a command by inverting the EEPROM's chip select pin
2960  *
2961  * hw - Struct containing variables accessed by shared code
2962  *****************************************************************************/
2963 static void
2964 e1000_release_eeprom(struct e1000_hw *hw)
2965 {
2966         uint32_t eecd;
2967
2968         eecd = E1000_READ_REG(hw, EECD);
2969
2970         if (hw->eeprom.type == e1000_eeprom_spi) {
2971                 eecd |= E1000_EECD_CS;  /* Pull CS high */
2972                 eecd &= ~E1000_EECD_SK; /* Lower SCK */
2973
2974                 E1000_WRITE_REG(hw, EECD, eecd);
2975
2976                 udelay(hw->eeprom.delay_usec);
2977         } else if(hw->eeprom.type == e1000_eeprom_microwire) {
2978                 /* cleanup eeprom */
2979
2980                 /* CS on Microwire is active-high */
2981                 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
2982
2983                 E1000_WRITE_REG(hw, EECD, eecd);
2984
2985                 /* Rising edge of clock */
2986                 eecd |= E1000_EECD_SK;
2987                 E1000_WRITE_REG(hw, EECD, eecd);
2988                 E1000_WRITE_FLUSH(hw);
2989                 udelay(hw->eeprom.delay_usec);
2990
2991                 /* Falling edge of clock */
2992                 eecd &= ~E1000_EECD_SK;
2993                 E1000_WRITE_REG(hw, EECD, eecd);
2994                 E1000_WRITE_FLUSH(hw);
2995                 udelay(hw->eeprom.delay_usec);
2996         }
2997
2998         /* Stop requesting EEPROM access */
2999         if(hw->mac_type > e1000_82544) {
3000                 eecd &= ~E1000_EECD_REQ;
3001                 E1000_WRITE_REG(hw, EECD, eecd);
3002         }
3003 }
3004
3005 /******************************************************************************
3006  * Reads a 16 bit word from the EEPROM.
3007  *
3008  * hw - Struct containing variables accessed by shared code
3009  *****************************************************************************/
3010 static int32_t
3011 e1000_spi_eeprom_ready(struct e1000_hw *hw)
3012 {
3013         uint16_t retry_count = 0;
3014         uint8_t spi_stat_reg;
3015
3016         /* Read "Status Register" repeatedly until the LSB is cleared.  The
3017          * EEPROM will signal that the command has been completed by clearing
3018          * bit 0 of the internal status register.  If it's not cleared within
3019          * 5 milliseconds, then error out.
3020          */
3021         retry_count = 0;
3022         do {
3023                 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
3024                 hw->eeprom.opcode_bits);
3025                 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
3026                 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
3027                         break;
3028
3029                 udelay(5);
3030                 retry_count += 5;
3031
3032         } while(retry_count < EEPROM_MAX_RETRY_SPI);
3033
3034         /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
3035          * only 0-5mSec on 5V devices)
3036          */
3037         if(retry_count >= EEPROM_MAX_RETRY_SPI) {
3038                 DEBUGOUT("SPI EEPROM Status error\n");
3039                 return -E1000_ERR_EEPROM;
3040         }
3041
3042         return E1000_SUCCESS;
3043 }
3044
3045 /******************************************************************************
3046  * Reads a 16 bit word from the EEPROM.
3047  *
3048  * hw - Struct containing variables accessed by shared code
3049  * offset - offset of  word in the EEPROM to read
3050  * data - word read from the EEPROM
3051  * words - number of words to read
3052  *****************************************************************************/
3053 static int
3054 e1000_read_eeprom(struct e1000_hw *hw,
3055                   uint16_t offset,
3056                   uint16_t words,
3057                   uint16_t *data)
3058 {
3059         struct e1000_eeprom_info *eeprom = &hw->eeprom;
3060         uint32_t i = 0;
3061         
3062         DEBUGFUNC("e1000_read_eeprom");
3063
3064         /* A check for invalid values:  offset too large, too many words, and not
3065          * enough words.
3066          */
3067         if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
3068            (words == 0)) {
3069                 DEBUGOUT("\"words\" parameter out of bounds\n");
3070                 return -E1000_ERR_EEPROM;
3071         }
3072
3073         /*  Prepare the EEPROM for reading  */
3074         if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
3075                 return -E1000_ERR_EEPROM;
3076
3077         if(eeprom->type == e1000_eeprom_spi) {
3078                 uint16_t word_in;
3079                 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
3080
3081                 if(e1000_spi_eeprom_ready(hw)) {
3082                         e1000_release_eeprom(hw);
3083                         return -E1000_ERR_EEPROM;
3084                 }
3085
3086                 e1000_standby_eeprom(hw);
3087
3088                 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
3089                 if((eeprom->address_bits == 8) && (offset >= 128))
3090                         read_opcode |= EEPROM_A8_OPCODE_SPI;
3091
3092                 /* Send the READ command (opcode + addr)  */
3093                 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
3094                 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
3095
3096                 /* Read the data.  The address of the eeprom internally increments with
3097                  * each byte (spi) being read, saving on the overhead of eeprom setup
3098                  * and tear-down.  The address counter will roll over if reading beyond
3099                  * the size of the eeprom, thus allowing the entire memory to be read
3100                  * starting from any offset. */
3101                 for (i = 0; i < words; i++) {
3102                         word_in = e1000_shift_in_ee_bits(hw, 16);
3103                         data[i] = (word_in >> 8) | (word_in << 8);
3104                 }
3105         } else if(eeprom->type == e1000_eeprom_microwire) {
3106                 for (i = 0; i < words; i++) {
3107                         /*  Send the READ command (opcode + addr)  */
3108                         e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
3109                                                 eeprom->opcode_bits);
3110                         e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
3111                                                 eeprom->address_bits);
3112
3113                         /* Read the data.  For microwire, each word requires the overhead
3114                          * of eeprom setup and tear-down. */
3115                         data[i] = e1000_shift_in_ee_bits(hw, 16);
3116                         e1000_standby_eeprom(hw);
3117                 }
3118         }
3119
3120         /* End this read operation */
3121         e1000_release_eeprom(hw);
3122
3123         return E1000_SUCCESS;
3124 }
3125
3126 /******************************************************************************
3127  * Verifies that the EEPROM has a valid checksum
3128  * 
3129  * hw - Struct containing variables accessed by shared code
3130  *
3131  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
3132  * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
3133  * valid.
3134  *****************************************************************************/
3135 static int
3136 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
3137 {
3138         uint16_t checksum = 0;
3139         uint16_t i, eeprom_data;
3140
3141         DEBUGFUNC("e1000_validate_eeprom_checksum");
3142
3143         for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
3144                 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
3145                         DEBUGOUT("EEPROM Read Error\n");
3146                         return -E1000_ERR_EEPROM;
3147                 }
3148                 checksum += eeprom_data;
3149         }
3150         
3151         if(checksum == (uint16_t) EEPROM_SUM)
3152                 return E1000_SUCCESS;
3153         else {
3154                 DEBUGOUT("EEPROM Checksum Invalid\n");    
3155                 return -E1000_ERR_EEPROM;
3156         }
3157 }
3158
3159 /******************************************************************************
3160  * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
3161  * second function of dual function devices
3162  *
3163  * hw - Struct containing variables accessed by shared code
3164  *****************************************************************************/
3165 static int 
3166 e1000_read_mac_addr(struct e1000_hw *hw)
3167 {
3168         uint16_t offset;
3169         uint16_t eeprom_data;
3170         int i;
3171
3172         DEBUGFUNC("e1000_read_mac_addr");
3173
3174         for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
3175                 offset = i >> 1;
3176                 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
3177                         DEBUGOUT("EEPROM Read Error\n");
3178                         return -E1000_ERR_EEPROM;
3179                 }
3180                 hw->mac_addr[i] = eeprom_data & 0xff;
3181                 hw->mac_addr[i+1] = (eeprom_data >> 8) & 0xff;
3182         }
3183         if(((hw->mac_type == e1000_82546) || (hw->mac_type == e1000_82546_rev_3)) &&
3184                 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1))
3185                 /* Invert the last bit if this is the second device */
3186                 hw->mac_addr[5] ^= 1;
3187         return E1000_SUCCESS;
3188 }
3189
3190 /******************************************************************************
3191  * Initializes receive address filters.
3192  *
3193  * hw - Struct containing variables accessed by shared code 
3194  *
3195  * Places the MAC address in receive address register 0 and clears the rest
3196  * of the receive addresss registers. Clears the multicast table. Assumes
3197  * the receiver is in reset when the routine is called.
3198  *****************************************************************************/
3199 static void
3200 e1000_init_rx_addrs(struct e1000_hw *hw)
3201 {
3202         uint32_t i;
3203         uint32_t addr_low;
3204         uint32_t addr_high;
3205         
3206         DEBUGFUNC("e1000_init_rx_addrs");
3207         
3208         /* Setup the receive address. */
3209         DEBUGOUT("Programming MAC Address into RAR[0]\n");
3210         addr_low = (hw->mac_addr[0] |
3211                 (hw->mac_addr[1] << 8) |
3212                 (hw->mac_addr[2] << 16) | (hw->mac_addr[3] << 24));
3213         
3214         addr_high = (hw->mac_addr[4] |
3215                 (hw->mac_addr[5] << 8) | E1000_RAH_AV);
3216         
3217         E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
3218         E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
3219         
3220         /* Zero out the other 15 receive addresses. */
3221         DEBUGOUT("Clearing RAR[1-15]\n");
3222         for(i = 1; i < E1000_RAR_ENTRIES; i++) {
3223                 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
3224                 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
3225         }
3226 }
3227
3228 /******************************************************************************
3229  * Clears the VLAN filer table
3230  *
3231  * hw - Struct containing variables accessed by shared code
3232  *****************************************************************************/
3233 static void
3234 e1000_clear_vfta(struct e1000_hw *hw)
3235 {
3236         uint32_t offset;
3237     
3238         for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
3239                 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
3240 }
3241
3242 /******************************************************************************
3243 * Writes a value to one of the devices registers using port I/O (as opposed to
3244 * memory mapped I/O). Only 82544 and newer devices support port I/O. *
3245 * hw - Struct containing variables accessed by shared code
3246 * offset - offset to write to * value - value to write
3247 *****************************************************************************/
3248 static void
3249 e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value)
3250 {
3251         uint32_t io_addr = hw->io_base;
3252         uint32_t io_data = hw->io_base + 4;
3253         e1000_io_write(hw, io_addr, offset);
3254         e1000_io_write(hw, io_data, value);
3255 }
3256
3257
3258 /******************************************************************************
3259  * Functions from e1000_main.c of the linux driver
3260  ******************************************************************************/
3261
3262 /**
3263  * e1000_reset - Reset the adapter
3264  */
3265
3266 static int
3267 e1000_reset(struct e1000_hw *hw)
3268 {
3269         uint32_t pba;
3270         /* Repartition Pba for greater than 9k mtu
3271          * To take effect CTRL.RST is required.
3272          */
3273
3274         if(hw->mac_type < e1000_82547) {
3275                 pba = E1000_PBA_48K;
3276         } else {
3277                 pba = E1000_PBA_30K;
3278         }
3279         E1000_WRITE_REG(hw, PBA, pba);
3280
3281         /* flow control settings */
3282 #if 0
3283         hw->fc_high_water = FC_DEFAULT_HI_THRESH;
3284         hw->fc_low_water = FC_DEFAULT_LO_THRESH;
3285         hw->fc_pause_time = FC_DEFAULT_TX_TIMER;
3286         hw->fc_send_xon = 1;
3287         hw->fc = hw->original_fc;
3288 #endif
3289         
3290         e1000_reset_hw(hw);
3291         if(hw->mac_type >= e1000_82544)
3292                 E1000_WRITE_REG(hw, WUC, 0);
3293         return e1000_init_hw(hw);
3294 }
3295
3296 /**
3297  * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
3298  * @adapter: board private structure to initialize
3299  *
3300  * e1000_sw_init initializes the Adapter private data structure.
3301  * Fields are initialized based on PCI device information and
3302  * OS network device settings (MTU size).
3303  **/
3304
3305 static int 
3306 e1000_sw_init(struct pci_device *pdev, struct e1000_hw *hw)
3307 {
3308         int result;
3309
3310         /* PCI config space info */
3311         pci_read_config_word(pdev, PCI_VENDOR_ID, &hw->vendor_id);
3312         pci_read_config_word(pdev, PCI_DEVICE_ID, &hw->device_id);
3313         pci_read_config_byte(pdev, PCI_REVISION, &hw->revision_id);
3314 #if 0
3315         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID,
3316                              &hw->subsystem_vendor_id);
3317         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
3318 #endif
3319
3320         pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
3321
3322         /* identify the MAC */
3323
3324         result = e1000_set_mac_type(hw);
3325         if (result) {
3326                 E1000_ERR("Unknown MAC Type\n");
3327                 return result;
3328         }
3329
3330         /* initialize eeprom parameters */
3331
3332         e1000_init_eeprom_params(hw);
3333
3334 #if 0
3335         if((hw->mac_type == e1000_82541) ||
3336            (hw->mac_type == e1000_82547) ||
3337            (hw->mac_type == e1000_82541_rev_2) ||
3338            (hw->mac_type == e1000_82547_rev_2))
3339                 hw->phy_init_script = 1;
3340 #endif
3341
3342         e1000_set_media_type(hw);
3343
3344 #if 0
3345         if(hw->mac_type < e1000_82543)
3346                 hw->report_tx_early = 0;
3347         else
3348                 hw->report_tx_early = 1;
3349
3350         hw->wait_autoneg_complete = FALSE;
3351 #endif
3352         hw->tbi_compatibility_en = TRUE;
3353 #if 0
3354         hw->adaptive_ifs = TRUE;
3355
3356         /* Copper options */
3357
3358         if(hw->media_type == e1000_media_type_copper) {
3359                 hw->mdix = AUTO_ALL_MODES;
3360                 hw->disable_polarity_correction = FALSE;
3361                 hw->master_slave = E1000_MASTER_SLAVE;
3362         }
3363 #endif
3364         return E1000_SUCCESS;
3365 }
3366
3367 #if 0
3368 static uint32_t
3369 e1000_io_read(struct e1000_hw *hw __unused, uint32_t port)
3370 {
3371         return inl(port);
3372 }
3373 #endif
3374
3375 static void
3376 e1000_io_write(struct e1000_hw *hw __unused, uint32_t port, uint32_t value)
3377 {
3378         outl(value, port);
3379 }
3380
3381
3382 /******************************************************************************
3383  * Functions not present in the linux driver
3384  ******************************************************************************/
3385
3386 static void fill_rx (void)
3387 {
3388         struct e1000_rx_desc *rd;
3389         rx_last = rx_tail;
3390         rd = rx_base + rx_tail;
3391         rx_tail = (rx_tail + 1) % 8;
3392         memset (rd, 0, 16);
3393         rd->buffer_addr = virt_to_bus(&packet);
3394         E1000_WRITE_REG (&hw, RDT, rx_tail);
3395 }
3396
3397 static void init_descriptor (void)
3398 {
3399         unsigned long ptr;
3400         unsigned long tctl;
3401
3402         ptr = virt_to_phys(tx_pool);
3403         if (ptr & 0xf)
3404                 ptr = (ptr + 0x10) & (~0xf);
3405
3406         tx_base = phys_to_virt(ptr);
3407
3408         E1000_WRITE_REG (&hw, TDBAL, virt_to_bus(tx_base));
3409         E1000_WRITE_REG (&hw, TDBAH, 0);
3410         E1000_WRITE_REG (&hw, TDLEN, 128);
3411
3412         /* Setup the HW Tx Head and Tail descriptor pointers */
3413
3414         E1000_WRITE_REG (&hw, TDH, 0);
3415         E1000_WRITE_REG (&hw, TDT, 0);
3416         tx_tail = 0;
3417
3418         /* Program the Transmit Control Register */
3419
3420 #ifdef LINUX_DRIVER_TCTL
3421         tctl = E1000_READ_REG(&hw, TCTL);
3422
3423         tctl &= ~E1000_TCTL_CT;
3424         tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
3425                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3426 #else
3427         tctl = E1000_TCTL_PSP | E1000_TCTL_EN |
3428                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) | 
3429                 (E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT);
3430 #endif
3431
3432         E1000_WRITE_REG (&hw, TCTL, tctl);
3433
3434         e1000_config_collision_dist(&hw);
3435
3436
3437         rx_tail = 0;
3438         /* disable receive */
3439         E1000_WRITE_REG (&hw, RCTL, 0);
3440         ptr = virt_to_phys(rx_pool);
3441         if (ptr & 0xf)
3442                 ptr = (ptr + 0x10) & (~0xf);
3443         rx_base = phys_to_virt(ptr);
3444
3445         /* Setup the Base and Length of the Rx Descriptor Ring */
3446
3447         E1000_WRITE_REG (&hw, RDBAL, virt_to_bus(rx_base));
3448         E1000_WRITE_REG (&hw, RDBAH, 0);
3449
3450         E1000_WRITE_REG (&hw, RDLEN, 128);
3451
3452         /* Setup the HW Rx Head and Tail Descriptor Pointers */
3453         E1000_WRITE_REG (&hw, RDH, 0);
3454         E1000_WRITE_REG (&hw, RDT, 0);
3455
3456         E1000_WRITE_REG (&hw, RCTL, 
3457                 E1000_RCTL_EN | 
3458                 E1000_RCTL_BAM | 
3459                 E1000_RCTL_SZ_2048 | 
3460                 E1000_RCTL_MPE);
3461         fill_rx();
3462 }
3463
3464
3465
3466 /**************************************************************************
3467 POLL - Wait for a frame
3468 ***************************************************************************/
3469 static int
3470 e1000_poll (struct nic *nic, int retrieve)
3471 {
3472         /* return true if there's an ethernet packet ready to read */
3473         /* nic->packet should contain data on return */
3474         /* nic->packetlen should contain length of data */
3475         struct e1000_rx_desc *rd;
3476         uint32_t icr;
3477
3478         rd = rx_base + rx_last;
3479         if (!rd->status & E1000_RXD_STAT_DD)
3480                 return 0;
3481
3482         if ( ! retrieve ) return 1;
3483
3484         //      printf("recv: packet %! -> %! len=%d \n", packet+6, packet,rd->Length);
3485         memcpy (nic->packet, packet, rd->length);
3486         nic->packetlen = rd->length;
3487         fill_rx ();
3488
3489         /* Acknowledge interrupt. */
3490         icr = E1000_READ_REG(&hw, ICR);
3491
3492         return 1;
3493 }
3494
3495 /**************************************************************************
3496 TRANSMIT - Transmit a frame
3497 ***************************************************************************/
3498 static void
3499 e1000_transmit (struct nic *nic, const char *d, /* Destination */
3500                     unsigned int type,  /* Type */
3501                     unsigned int size,  /* size */
3502                     const char *p)      /* Packet */
3503 {
3504         /* send the packet to destination */
3505         struct eth_hdr {
3506                 unsigned char dst_addr[ETH_ALEN];
3507                 unsigned char src_addr[ETH_ALEN];
3508                 unsigned short type;
3509         } hdr;
3510         struct e1000_tx_desc *txhd;     /* header */
3511         struct e1000_tx_desc *txp;      /* payload */
3512         DEBUGFUNC("send");
3513
3514         memcpy (&hdr.dst_addr, d, ETH_ALEN);
3515         memcpy (&hdr.src_addr, nic->node_addr, ETH_ALEN);
3516
3517         hdr.type = htons (type);
3518         txhd = tx_base + tx_tail;
3519         tx_tail = (tx_tail + 1) % 8;
3520         txp = tx_base + tx_tail;
3521         tx_tail = (tx_tail + 1) % 8;
3522
3523         txhd->buffer_addr = virt_to_bus (&hdr);
3524         txhd->lower.data = sizeof (hdr);
3525         txhd->upper.data = 0;
3526
3527         txp->buffer_addr = virt_to_bus(p);
3528         txp->lower.data = E1000_TXD_CMD_RPS | E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS | size;
3529         txp->upper.data = 0;
3530
3531         E1000_WRITE_REG (&hw, TDT, tx_tail);
3532         while (!(txp->upper.data & E1000_TXD_STAT_DD)) {
3533                 udelay(10);     /* give the nic a chance to write to the register */
3534       &nbs