tg3 driver updates from Ryan Jackson
[etherboot.git] / src / drivers / net / tg3.c
1 /* $Id$
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002 Jeff Garzik (jgarzik@mandrakesoft.com)
6  * Copyright (C) 2003 Eric Biederman (ebiederman@lnxi.com)  [etherboot port]
7  */
8
9 /* 11-13-2003   timlegge        Fix Issue with NetGear GA302T 
10  * 11-18-2003   ebiederm        Generalize NetGear Fix to what the code was supposed to be.
11  * 01-06-2005   Alf (Frederic Olivie) Add Dell bcm 5751 (0x1677) support
12  * 04-15-2005   Martin Vogt Add Fujitsu Siemens Computer (FSC) 0x1734 bcm 5751 0x105d support
13  */
14
15 #include "etherboot.h"
16 #include "nic.h"
17 #include "pci.h"
18 #include "timer.h"
19 #include "string.h"
20 #include "tg3.h"
21
22 #define SUPPORT_COPPER_PHY  1
23 #define SUPPORT_FIBER_PHY   1
24 #define SUPPORT_LINK_REPORT 1
25 #define SUPPORT_PARTNO_STR  1
26 #define SUPPORT_PHY_STR     1
27
28 struct tg3 tg3;
29
30 /* Dummy defines for error handling */
31 #define EBUSY  1
32 #define ENODEV 2
33 #define EINVAL 3
34 #define ENOMEM 4
35
36
37 /* These numbers seem to be hard coded in the NIC firmware somehow.
38  * You can't change the ring sizes, but you can change where you place
39  * them in the NIC onboard memory.
40  */
41 #define TG3_RX_RING_SIZE                512
42 #define TG3_DEF_RX_RING_PENDING         20      /* RX_RING_PENDING seems to be o.k. at 20 and 200 */
43 #define TG3_RX_RCB_RING_SIZE    1024
44
45 /*      (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ? \
46          512 : 1024) */
47 #define TG3_TX_RING_SIZE                512
48 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
49
50 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_RING_SIZE)
51 #define TG3_RX_RCB_RING_BYTES   (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_RCB_RING_SIZE)
52
53 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * TG3_TX_RING_SIZE)
54 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
55 #define PREV_TX(N)              (((N) - 1) & (TG3_TX_RING_SIZE - 1))
56
57 #define RX_PKT_BUF_SZ           (1536 + 2 + 64)
58
59
60 static struct bss {
61         struct tg3_rx_buffer_desc rx_std[TG3_RX_RING_SIZE];
62         struct tg3_rx_buffer_desc rx_rcb[TG3_RX_RCB_RING_SIZE];
63         struct tg3_tx_buffer_desc tx_ring[TG3_TX_RING_SIZE];
64         struct tg3_hw_status      hw_status;
65         struct tg3_hw_stats       hw_stats;
66         unsigned char             rx_bufs[TG3_DEF_RX_RING_PENDING][RX_PKT_BUF_SZ];
67 } tg3_bss;
68
69 /**
70  * pci_save_state - save the PCI configuration space of a device before suspending
71  * @dev: - PCI device that we're dealing with
72  * @buffer: - buffer to hold config space context
73  *
74  * @buffer must be large enough to hold the entire PCI 2.2 config space 
75  * (>= 64 bytes).
76  */
77 static int pci_save_state(struct pci_device *dev, uint32_t *buffer)
78 {
79         int i;
80         for (i = 0; i < 16; i++)
81                 pci_read_config_dword(dev, i * 4,&buffer[i]);
82         return 0;
83 }
84
85 /** 
86  * pci_restore_state - Restore the saved state of a PCI device
87  * @dev: - PCI device that we're dealing with
88  * @buffer: - saved PCI config space
89  *
90  */
91 static int pci_restore_state(struct pci_device *dev, uint32_t *buffer)
92 {
93         int i;
94
95         for (i = 0; i < 16; i++)
96                 pci_write_config_dword(dev,i * 4, buffer[i]);
97         return 0;
98 }
99
100 static void tg3_write_indirect_reg32(uint32_t off, uint32_t val)
101 {
102         pci_write_config_dword(tg3.pdev, TG3PCI_REG_BASE_ADDR, off);
103         pci_write_config_dword(tg3.pdev, TG3PCI_REG_DATA, val);
104 }
105
106 #define tw32(reg,val)           tg3_write_indirect_reg32((reg),(val))
107 #define tw32_mailbox(reg, val)  writel(((val) & 0xffffffff), tg3.regs + (reg))
108 #define tw16(reg,val)           writew(((val) & 0xffff), tg3.regs + (reg))
109 #define tw8(reg,val)            writeb(((val) & 0xff), tg3.regs + (reg))
110 #define tr32(reg)               readl(tg3.regs + (reg))
111 #define tr16(reg)               readw(tg3.regs + (reg))
112 #define tr8(reg)                readb(tg3.regs + (reg))
113
114 static void tw32_carefully(uint32_t reg, uint32_t val)
115 {
116         tw32(reg, val);
117         tr32(reg);
118         udelay(100);
119 }
120
121 static void tw32_mailbox2(uint32_t reg, uint32_t val)
122 {
123         tw32_mailbox(reg, val);
124         tr32(reg);
125 }
126
127 static void tg3_write_mem(uint32_t off, uint32_t val)
128 {
129         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
130         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_DATA, val);
131
132         /* Always leave this as zero. */
133         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
134 }
135
136 static void tg3_read_mem(uint32_t off, uint32_t *val)
137 {
138         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
139         pci_read_config_dword(tg3.pdev, TG3PCI_MEM_WIN_DATA, val);
140
141         /* Always leave this as zero. */
142         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
143 }
144
145 static void tg3_disable_ints(struct tg3 *tp)
146 {
147         tw32(TG3PCI_MISC_HOST_CTRL,
148              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
149         tw32_mailbox2(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
150 }
151
152 static void tg3_switch_clocks(struct tg3 *tp)
153 {
154         uint32_t orig_clock_ctrl, clock_ctrl;
155
156         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
157
158         orig_clock_ctrl = clock_ctrl;
159         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | CLOCK_CTRL_CLKRUN_OENABLE | 0x1f);
160         tp->pci_clock_ctrl = clock_ctrl;
161         
162         if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) &&
163             (!((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
164                && (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) &&
165                 (orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE)!=0) {
166                 tw32_carefully(TG3PCI_CLOCK_CTRL, 
167                         clock_ctrl | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
168                 tw32_carefully(TG3PCI_CLOCK_CTRL, 
169                         clock_ctrl | (CLOCK_CTRL_ALTCLK));
170         }
171         tw32_carefully(TG3PCI_CLOCK_CTRL, clock_ctrl);
172 }
173
174 #define PHY_BUSY_LOOPS  5000
175
176 static int tg3_readphy(struct tg3 *tp, int reg, uint32_t *val)
177 {
178         uint32_t frame_val;
179         int loops, ret;
180
181         tw32_carefully(MAC_MI_MODE, tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL);
182
183         *val = 0xffffffff;
184
185         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
186                       MI_COM_PHY_ADDR_MASK);
187         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
188                       MI_COM_REG_ADDR_MASK);
189         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
190         
191         tw32_carefully(MAC_MI_COM, frame_val);
192
193         loops = PHY_BUSY_LOOPS;
194         while (loops-- > 0) {
195                 udelay(10);
196                 frame_val = tr32(MAC_MI_COM);
197
198                 if ((frame_val & MI_COM_BUSY) == 0) {
199                         udelay(5);
200                         frame_val = tr32(MAC_MI_COM);
201                         break;
202                 }
203         }
204
205         ret = -EBUSY;
206         if (loops > 0) {
207                 *val = frame_val & MI_COM_DATA_MASK;
208                 ret = 0;
209         }
210
211         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
212
213         return ret;
214 }
215
216 static int tg3_writephy(struct tg3 *tp, int reg, uint32_t val)
217 {
218         uint32_t frame_val;
219         int loops, ret;
220
221         tw32_carefully(MAC_MI_MODE, tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL);
222
223         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
224                       MI_COM_PHY_ADDR_MASK);
225         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
226                       MI_COM_REG_ADDR_MASK);
227         frame_val |= (val & MI_COM_DATA_MASK);
228         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
229         
230         tw32_carefully(MAC_MI_COM, frame_val);
231
232         loops = PHY_BUSY_LOOPS;
233         while (loops-- > 0) {
234                 udelay(10);
235                 frame_val = tr32(MAC_MI_COM);
236                 if ((frame_val & MI_COM_BUSY) == 0) {
237                         udelay(5);
238                         frame_val = tr32(MAC_MI_COM);
239                         break;
240                 }
241         }
242
243         ret = -EBUSY;
244         if (loops > 0)
245                 ret = 0;
246
247         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
248
249         return ret;
250 }
251
252 static int tg3_writedsp(struct tg3 *tp, uint16_t addr, uint16_t val)
253 {
254         int err;
255         err  = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, addr);
256         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
257         return err;
258 }
259
260
261 static void tg3_phy_set_wirespeed(struct tg3 *tp)
262 {
263         uint32_t val;
264
265         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
266                 return;
267
268         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007);
269         tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
270         tg3_writephy(tp, MII_TG3_AUX_CTRL, (val | (1 << 15) | (1 << 4)));
271 }
272
273 static int tg3_bmcr_reset(struct tg3 *tp)
274 {
275         uint32_t phy_control;
276         int limit, err;
277
278         /* OK, reset it, and poll the BMCR_RESET bit until it
279          * clears or we time out.
280          */
281         phy_control = BMCR_RESET;
282         err = tg3_writephy(tp, MII_BMCR, phy_control);
283         if (err != 0)
284                 return -EBUSY;
285
286         limit = 5000;
287         while (limit--) {
288                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
289                 if (err != 0)
290                         return -EBUSY;
291
292                 if ((phy_control & BMCR_RESET) == 0) {
293                         udelay(40);
294                         break;
295                 }
296                 udelay(10);
297         }
298         if (limit <= 0)
299                 return -EBUSY;
300
301         return 0;
302 }
303
304 static int tg3_wait_macro_done(struct tg3 *tp)
305 {
306         int limit = 100;
307
308         while (limit--) {
309                 uint32_t tmp32;
310
311                 tg3_readphy(tp, 0x16, &tmp32);
312                 if ((tmp32 & 0x1000) == 0)
313                         break;
314         }
315         if (limit <= 0)
316                 return -EBUSY;
317
318         return 0;
319 }
320
321 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
322 {
323         static const uint32_t test_pat[4][6] = {
324         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
325         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
326         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
327         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
328         };
329         int chan;
330
331         for (chan = 0; chan < 4; chan++) {
332                 int i;
333
334                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
335                         (chan * 0x2000) | 0x0200);
336                 tg3_writephy(tp, 0x16, 0x0002);
337
338                 for (i = 0; i < 6; i++)
339                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
340                                 test_pat[chan][i]);
341
342                 tg3_writephy(tp, 0x16, 0x0202);
343                 if (tg3_wait_macro_done(tp)) {
344                         *resetp = 1;
345                         return -EBUSY;
346                 }
347
348                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
349                              (chan * 0x2000) | 0x0200);
350                 tg3_writephy(tp, 0x16, 0x0082);
351                 if (tg3_wait_macro_done(tp)) {
352                         *resetp = 1;
353                         return -EBUSY;
354                 }
355
356                 tg3_writephy(tp, 0x16, 0x0802);
357                 if (tg3_wait_macro_done(tp)) {
358                         *resetp = 1;
359                         return -EBUSY;
360                 }
361
362                 for (i = 0; i < 6; i += 2) {
363                         uint32_t low, high;
364
365                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low);
366                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high);
367                         if (tg3_wait_macro_done(tp)) {
368                                 *resetp = 1;
369                                 return -EBUSY;
370                         }
371                         low &= 0x7fff;
372                         high &= 0x000f;
373                         if (low != test_pat[chan][i] ||
374                             high != test_pat[chan][i+1]) {
375                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
376                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
377                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
378
379                                 return -EBUSY;
380                         }
381                 }
382         }
383
384         return 0;
385 }
386
387 static int tg3_phy_reset_chanpat(struct tg3 *tp)
388 {
389         int chan;
390
391         for (chan = 0; chan < 4; chan++) {
392                 int i;
393
394                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
395                              (chan * 0x2000) | 0x0200);
396                 tg3_writephy(tp, 0x16, 0x0002);
397                 for (i = 0; i < 6; i++)
398                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
399                 tg3_writephy(tp, 0x16, 0x0202);
400                 if (tg3_wait_macro_done(tp))
401                         return -EBUSY;
402         }
403
404         return 0;
405 }
406
407 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
408 {
409         uint32_t reg32, phy9_orig;
410         int retries, do_phy_reset, err;
411
412         retries = 10;
413         do_phy_reset = 1;
414         do {
415                 if (do_phy_reset) {
416                         err = tg3_bmcr_reset(tp);
417                         if (err)
418                                 return err;
419                         do_phy_reset = 0;
420                 }
421                 
422                 /* Disable transmitter and interrupt.  */
423                 tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);
424                 reg32 |= 0x3000;
425                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
426
427                 /* Set full-duplex, 1000 mbps.  */
428                 tg3_writephy(tp, MII_BMCR,
429                         BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
430
431                 /* Set to master mode.  */
432                 tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig);
433                 tg3_writephy(tp, MII_TG3_CTRL,
434                         (MII_TG3_CTRL_AS_MASTER |
435                                 MII_TG3_CTRL_ENABLE_AS_MASTER));
436
437                 /* Enable SM_DSP_CLOCK and 6dB.  */
438                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
439
440                 /* Block the PHY control access.  */
441                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
442                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
443
444                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
445                 if (!err)
446                         break;
447         } while (--retries);
448
449         err = tg3_phy_reset_chanpat(tp);
450         if (err)
451                 return err;
452
453         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
454         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
455
456         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
457         tg3_writephy(tp, 0x16, 0x0000);
458
459         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
460
461         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
462
463         tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);
464         reg32 &= ~0x3000;
465         tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
466
467         return err;
468 }
469
470 /* This will reset the tigon3 PHY if there is no valid
471  * link.
472  */
473 static int tg3_phy_reset(struct tg3 *tp)
474 {
475         uint32_t phy_status;
476         int err;
477
478         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
479         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
480         if (err != 0)
481                 return -EBUSY;
482
483         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
484                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
485                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
486                 err = tg3_phy_reset_5703_4_5(tp);
487                 if (err)
488                         return err;
489                 goto out;
490         }
491         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
492           // Taken from Broadcom's source code
493           tg3_writephy(tp, 0x18, 0x0c00);
494           tg3_writephy(tp, 0x17, 0x000a);
495           tg3_writephy(tp, 0x15, 0x310b);
496           tg3_writephy(tp, 0x17, 0x201f);
497           tg3_writephy(tp, 0x15, 0x9506);
498           tg3_writephy(tp, 0x17, 0x401f);
499           tg3_writephy(tp, 0x15, 0x14e2);
500           tg3_writephy(tp, 0x18, 0x0400);
501         }
502         err = tg3_bmcr_reset(tp);
503         if (err)
504                 return err;
505  out:
506         tg3_phy_set_wirespeed(tp);
507         return 0;
508 }
509
510 static void tg3_set_power_state_0(struct tg3 *tp)
511 {
512         uint16_t power_control;
513         int pm = tp->pm_cap;
514
515         /* Make sure register accesses (indirect or otherwise)
516          * will function correctly.
517          */
518         pci_write_config_dword(tp->pdev,  TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
519
520         pci_read_config_word(tp->pdev, pm + PCI_PM_CTRL, &power_control);
521
522         power_control |= PCI_PM_CTRL_PME_STATUS;
523         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
524         power_control |= 0;
525         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
526
527         tw32_carefully(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
528
529         return;
530 }
531
532
533 #if SUPPORT_LINK_REPORT
534 static void tg3_link_report(struct tg3 *tp)
535 {
536         if (!tp->carrier_ok) {
537                 printf("Link is down.\n");
538         } else {
539                 printf("Link is up at %d Mbps, %s duplex. %s %s %s\n",
540                         (tp->link_config.active_speed == SPEED_1000 ?
541                                1000 :
542                         (tp->link_config.active_speed == SPEED_100 ?
543                                 100 : 10)),
544                         (tp->link_config.active_duplex == DUPLEX_FULL ?  
545                                 "full" : "half"),
546                         (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "TX" : "",
547                         (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "RX" : "",
548                         (tp->tg3_flags & (TG3_FLAG_TX_PAUSE |TG3_FLAG_RX_PAUSE)) ? "flow control" : "");
549         }
550 }
551 #else
552 #define tg3_link_report(tp)
553 #endif
554
555 static void tg3_setup_flow_control(struct tg3 *tp, uint32_t local_adv, uint32_t remote_adv)
556 {
557         uint32_t new_tg3_flags = 0;
558
559         if (local_adv & ADVERTISE_PAUSE_CAP) {
560                 if (local_adv & ADVERTISE_PAUSE_ASYM) {
561                         if (remote_adv & LPA_PAUSE_CAP)
562                                 new_tg3_flags |=
563                                         (TG3_FLAG_RX_PAUSE |
564                                          TG3_FLAG_TX_PAUSE);
565                         else if (remote_adv & LPA_PAUSE_ASYM)
566                                 new_tg3_flags |=
567                                         (TG3_FLAG_RX_PAUSE);
568                 } else {
569                         if (remote_adv & LPA_PAUSE_CAP)
570                                 new_tg3_flags |=
571                                         (TG3_FLAG_RX_PAUSE |
572                                          TG3_FLAG_TX_PAUSE);
573                 }
574         } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
575                 if ((remote_adv & LPA_PAUSE_CAP) &&
576                     (remote_adv & LPA_PAUSE_ASYM))
577                         new_tg3_flags |= TG3_FLAG_TX_PAUSE;
578         }
579
580         tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
581         tp->tg3_flags |= new_tg3_flags;
582
583         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
584                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
585         else
586                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
587
588         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
589                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
590         else
591                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
592 }
593
594 #if SUPPORT_COPPER_PHY
595 static void tg3_aux_stat_to_speed_duplex(
596         struct tg3 *tp __unused, uint32_t val, uint8_t *speed, uint8_t *duplex)
597 {
598         static const uint8_t map[] = {
599                 [0] = (SPEED_INVALID << 2) | DUPLEX_INVALID,
600                 [MII_TG3_AUX_STAT_10HALF >> 8]   = (SPEED_10 << 2) | DUPLEX_HALF,
601                 [MII_TG3_AUX_STAT_10FULL >> 8]   = (SPEED_10 << 2) | DUPLEX_FULL,
602                 [MII_TG3_AUX_STAT_100HALF >> 8]  = (SPEED_100 << 2) | DUPLEX_HALF,
603                 [MII_TG3_AUX_STAT_100_4 >> 8] = (SPEED_INVALID << 2) | DUPLEX_INVALID,
604                 [MII_TG3_AUX_STAT_100FULL >> 8]  = (SPEED_100 << 2) | DUPLEX_FULL,
605                 [MII_TG3_AUX_STAT_1000HALF >> 8] = (SPEED_1000 << 2) | DUPLEX_HALF,
606                 [MII_TG3_AUX_STAT_1000FULL >> 8] = (SPEED_1000 << 2) | DUPLEX_FULL,
607         };
608         uint8_t result;
609         result = map[(val & MII_TG3_AUX_STAT_SPDMASK) >> 8];
610         *speed = result >> 2;
611         *duplex = result & 3;
612 }
613
614 static int tg3_phy_copper_begin(struct tg3 *tp)
615 {
616         uint32_t new_adv;
617
618         tp->link_config.advertising =
619                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
620                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
621                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
622                         ADVERTISED_Autoneg | ADVERTISED_MII);
623         
624         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) {
625                 tp->link_config.advertising &=
626                         ~(ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
627         }
628         
629         new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
630         if (tp->link_config.advertising & ADVERTISED_10baseT_Half) {
631                 new_adv |= ADVERTISE_10HALF;
632         }
633         if (tp->link_config.advertising & ADVERTISED_10baseT_Full) {
634                 new_adv |= ADVERTISE_10FULL;
635         }
636         if (tp->link_config.advertising & ADVERTISED_100baseT_Half) {
637                 new_adv |= ADVERTISE_100HALF;
638         }
639         if (tp->link_config.advertising & ADVERTISED_100baseT_Full) {
640                 new_adv |= ADVERTISE_100FULL;
641         }
642         tg3_writephy(tp, MII_ADVERTISE, new_adv);
643         
644         if (tp->link_config.advertising &
645                 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
646                 new_adv = 0;
647                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) {
648                         new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
649                 }
650                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) {
651                         new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
652                 }
653                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
654                         (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
655                                 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) {
656                         new_adv |= (MII_TG3_CTRL_AS_MASTER |
657                                 MII_TG3_CTRL_ENABLE_AS_MASTER);
658                 }
659                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
660         } else {
661                 tg3_writephy(tp, MII_TG3_CTRL, 0);
662         }
663
664         tg3_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
665
666         return 0;
667 }
668
669 static int tg3_init_5401phy_dsp(struct tg3 *tp)
670 {
671         int err;
672
673         /* Turn off tap power management. */
674         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c20);
675         
676         err |= tg3_writedsp(tp, 0x0012, 0x1804);
677         err |= tg3_writedsp(tp, 0x0013, 0x1204);
678         err |= tg3_writedsp(tp, 0x8006, 0x0132);
679         err |= tg3_writedsp(tp, 0x8006, 0x0232);
680         err |= tg3_writedsp(tp, 0x201f, 0x0a20);
681
682         udelay(40);
683
684         return err;
685 }
686
687 static int tg3_setup_copper_phy(struct tg3 *tp)
688 {
689         int current_link_up;
690         uint32_t bmsr, dummy;
691         int i, err;
692
693         tw32_carefully(MAC_STATUS,
694                 (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED
695                  | MAC_STATUS_LNKSTATE_CHANGED));
696
697         tp->mi_mode = MAC_MI_MODE_BASE;
698         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
699
700         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
701
702         /* Some third-party PHYs need to be reset on link going
703          * down.
704          */
705         if (    (       (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
706                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
707                         (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)) &&
708                 (tp->carrier_ok)) {
709                 tg3_readphy(tp, MII_BMSR, &bmsr);
710                 tg3_readphy(tp, MII_BMSR, &bmsr);
711                 if (!(bmsr & BMSR_LSTATUS))
712                         tg3_phy_reset(tp);
713         }
714
715         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
716                 tg3_readphy(tp, MII_BMSR, &bmsr);
717                 tg3_readphy(tp, MII_BMSR, &bmsr);
718
719                 if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
720                         bmsr = 0;
721
722                 if (!(bmsr & BMSR_LSTATUS)) {
723                         err = tg3_init_5401phy_dsp(tp);
724                         if (err)
725                                 return err;
726
727                         tg3_readphy(tp, MII_BMSR, &bmsr);
728                         for (i = 0; i < 1000; i++) {
729                                 udelay(10);
730                                 tg3_readphy(tp, MII_BMSR, &bmsr);
731                                 if (bmsr & BMSR_LSTATUS) {
732                                         udelay(40);
733                                         break;
734                                 }
735                         }
736
737                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
738                             !(bmsr & BMSR_LSTATUS) &&
739                             tp->link_config.active_speed == SPEED_1000) {
740                                 err = tg3_phy_reset(tp);
741                                 if (!err)
742                                         err = tg3_init_5401phy_dsp(tp);
743                                 if (err)
744                                         return err;
745                         }
746                 }
747         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
748                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
749                 /* 5701 {A0,B0} CRC bug workaround */
750                 tg3_writephy(tp, 0x15, 0x0a75);
751                 tg3_writephy(tp, 0x1c, 0x8c68);
752                 tg3_writephy(tp, 0x1c, 0x8d68);
753                 tg3_writephy(tp, 0x1c, 0x8c68);
754         }
755
756         /* Clear pending interrupts... */
757         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
758         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
759
760         tg3_writephy(tp, MII_TG3_IMASK, ~0);
761
762         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
763             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
764                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
765                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
766                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
767                 else
768                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
769         }
770
771         current_link_up = 0;
772
773         tg3_readphy(tp, MII_BMSR, &bmsr);
774         tg3_readphy(tp, MII_BMSR, &bmsr);
775
776         if (bmsr & BMSR_LSTATUS) {
777                 uint32_t aux_stat, bmcr;
778
779                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
780                 for (i = 0; i < 2000; i++) {
781                         udelay(10);
782                         tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
783                         if (aux_stat)
784                                 break;
785                 }
786
787                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
788                         &tp->link_config.active_speed,
789                         &tp->link_config.active_duplex);
790                 tg3_readphy(tp, MII_BMCR, &bmcr);
791                 tg3_readphy(tp, MII_BMCR, &bmcr);
792                 if (bmcr & BMCR_ANENABLE) {
793                         uint32_t gig_ctrl;
794                         
795                         current_link_up = 1;
796                         
797                         /* Force autoneg restart if we are exiting
798                          * low power mode.
799                          */
800                         tg3_readphy(tp, MII_TG3_CTRL, &gig_ctrl);
801                         if (!(gig_ctrl & (MII_TG3_CTRL_ADV_1000_HALF |
802                                       MII_TG3_CTRL_ADV_1000_FULL))) {
803                                 current_link_up = 0;
804                         }
805                 } else {
806                         current_link_up = 0;
807                 }
808         }
809
810         if (current_link_up == 1 &&
811                 (tp->link_config.active_duplex == DUPLEX_FULL)) {
812                 uint32_t local_adv, remote_adv;
813
814                 tg3_readphy(tp, MII_ADVERTISE, &local_adv);
815                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
816
817                 tg3_readphy(tp, MII_LPA, &remote_adv);
818                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
819
820                 /* If we are not advertising full pause capability,
821                  * something is wrong.  Bring the link down and reconfigure.
822                  */
823                 if (local_adv != ADVERTISE_PAUSE_CAP) {
824                         current_link_up = 0;
825                 } else {
826                         tg3_setup_flow_control(tp, local_adv, remote_adv);
827                 }
828         }
829
830         if (current_link_up == 0) {
831                 uint32_t tmp;
832
833                 tg3_phy_copper_begin(tp);
834
835                 tg3_readphy(tp, MII_BMSR, &tmp);
836                 tg3_readphy(tp, MII_BMSR, &tmp);
837                 if (tmp & BMSR_LSTATUS)
838                         current_link_up = 1;
839         }
840
841         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
842         if (current_link_up == 1) {
843                 if (tp->link_config.active_speed == SPEED_100 ||
844                     tp->link_config.active_speed == SPEED_10)
845                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
846                 else
847                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
848         } else
849                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
850
851         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
852         if (tp->link_config.active_duplex == DUPLEX_HALF)
853                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
854
855         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
856         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
857                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
858                     (current_link_up == 1 &&
859                      tp->link_config.active_speed == SPEED_10))
860                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
861         } else {
862                 if (current_link_up == 1)
863                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
864                 tw32(MAC_LED_CTRL, LED_CTRL_MODE_PHY_1);
865         }
866
867         /* ??? Without this setting Netgear GA302T PHY does not
868          * ??? send/receive packets...
869          * With this other PHYs cannot bring up the link
870          */
871         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
872                 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
873                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
874                 tw32_carefully(MAC_MI_MODE, tp->mi_mode);
875         }
876
877         tw32_carefully(MAC_MODE, tp->mac_mode);
878
879         /* Link change polled. */
880         tw32_carefully(MAC_EVENT, 0);
881
882         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
883             current_link_up == 1 &&
884             tp->link_config.active_speed == SPEED_1000 &&
885             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
886              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
887                 udelay(120);
888                 tw32_carefully(MAC_STATUS,
889                         (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED));
890                 tg3_write_mem(
891                               NIC_SRAM_FIRMWARE_MBOX,
892                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
893         }
894
895         if (current_link_up != tp->carrier_ok) {
896                 tp->carrier_ok = current_link_up;
897                 tg3_link_report(tp);
898         }
899
900         return 0;
901 }
902 #else
903 #define tg3_setup_copper_phy(TP) (-EINVAL)
904 #endif /* SUPPORT_COPPER_PHY */
905
906 #if SUPPORT_FIBER_PHY
907 struct tg3_fiber_aneginfo {
908         int state;
909 #define ANEG_STATE_UNKNOWN              0
910 #define ANEG_STATE_AN_ENABLE            1
911 #define ANEG_STATE_RESTART_INIT         2
912 #define ANEG_STATE_RESTART              3
913 #define ANEG_STATE_DISABLE_LINK_OK      4
914 #define ANEG_STATE_ABILITY_DETECT_INIT  5
915 #define ANEG_STATE_ABILITY_DETECT       6
916 #define ANEG_STATE_ACK_DETECT_INIT      7
917 #define ANEG_STATE_ACK_DETECT           8
918 #define ANEG_STATE_COMPLETE_ACK_INIT    9
919 #define ANEG_STATE_COMPLETE_ACK         10
920 #define ANEG_STATE_IDLE_DETECT_INIT     11
921 #define ANEG_STATE_IDLE_DETECT          12
922 #define ANEG_STATE_LINK_OK              13
923 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
924 #define ANEG_STATE_NEXT_PAGE_WAIT       15
925
926         uint32_t flags;
927 #define MR_AN_ENABLE            0x00000001
928 #define MR_RESTART_AN           0x00000002
929 #define MR_AN_COMPLETE          0x00000004
930 #define MR_PAGE_RX              0x00000008
931 #define MR_NP_LOADED            0x00000010
932 #define MR_TOGGLE_TX            0x00000020
933 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
934 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
935 #define MR_LP_ADV_SYM_PAUSE     0x00000100
936 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
937 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
938 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
939 #define MR_LP_ADV_NEXT_PAGE     0x00001000
940 #define MR_TOGGLE_RX            0x00002000
941 #define MR_NP_RX                0x00004000
942
943 #define MR_LINK_OK              0x80000000
944
945         unsigned long link_time, cur_time;
946
947         uint32_t ability_match_cfg;
948         int ability_match_count;
949
950         char ability_match, idle_match, ack_match;
951
952         uint32_t txconfig, rxconfig;
953 #define ANEG_CFG_NP             0x00000080
954 #define ANEG_CFG_ACK            0x00000040
955 #define ANEG_CFG_RF2            0x00000020
956 #define ANEG_CFG_RF1            0x00000010
957 #define ANEG_CFG_PS2            0x00000001
958 #define ANEG_CFG_PS1            0x00008000
959 #define ANEG_CFG_HD             0x00004000
960 #define ANEG_CFG_FD             0x00002000
961 #define ANEG_CFG_INVAL          0x00001f06
962
963 };
964 #define ANEG_OK         0
965 #define ANEG_DONE       1
966 #define ANEG_TIMER_ENAB 2
967 #define ANEG_FAILED     -1
968
969 #define ANEG_STATE_SETTLE_TIME  10000
970
971 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
972                                    struct tg3_fiber_aneginfo *ap)
973 {
974         unsigned long delta;
975         uint32_t rx_cfg_reg;
976         int ret;
977
978         if (ap->state == ANEG_STATE_UNKNOWN) {
979                 ap->rxconfig = 0;
980                 ap->link_time = 0;
981                 ap->cur_time = 0;
982                 ap->ability_match_cfg = 0;
983                 ap->ability_match_count = 0;
984                 ap->ability_match = 0;
985                 ap->idle_match = 0;
986                 ap->ack_match = 0;
987         }
988         ap->cur_time++;
989
990         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
991                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
992
993                 if (rx_cfg_reg != ap->ability_match_cfg) {
994                         ap->ability_match_cfg = rx_cfg_reg;
995                         ap->ability_match = 0;
996                         ap->ability_match_count = 0;
997                 } else {
998                         if (++ap->ability_match_count > 1) {
999                                 ap->ability_match = 1;
1000                                 ap->ability_match_cfg = rx_cfg_reg;
1001                         }
1002                 }
1003                 if (rx_cfg_reg & ANEG_CFG_ACK)
1004                         ap->ack_match = 1;
1005                 else
1006                         ap->ack_match = 0;
1007
1008                 ap->idle_match = 0;
1009         } else {
1010                 ap->idle_match = 1;
1011                 ap->ability_match_cfg = 0;
1012                 ap->ability_match_count = 0;
1013                 ap->ability_match = 0;
1014                 ap->ack_match = 0;
1015
1016                 rx_cfg_reg = 0;
1017         }
1018
1019         ap->rxconfig = rx_cfg_reg;
1020         ret = ANEG_OK;
1021
1022         switch(ap->state) {
1023         case ANEG_STATE_UNKNOWN:
1024                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
1025                         ap->state = ANEG_STATE_AN_ENABLE;
1026
1027                 /* fallthru */
1028         case ANEG_STATE_AN_ENABLE:
1029                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
1030                 if (ap->flags & MR_AN_ENABLE) {
1031                         ap->link_time = 0;
1032                         ap->cur_time = 0;
1033                         ap->ability_match_cfg = 0;
1034                         ap->ability_match_count = 0;
1035                         ap->ability_match = 0;
1036                         ap->idle_match = 0;
1037                         ap->ack_match = 0;
1038
1039                         ap->state = ANEG_STATE_RESTART_INIT;
1040                 } else {
1041                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
1042                 }
1043                 break;
1044
1045         case ANEG_STATE_RESTART_INIT:
1046                 ap->link_time = ap->cur_time;
1047                 ap->flags &= ~(MR_NP_LOADED);
1048                 ap->txconfig = 0;
1049                 tw32(MAC_TX_AUTO_NEG, 0);
1050                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1051                 tw32_carefully(MAC_MODE, tp->mac_mode);
1052
1053                 ret = ANEG_TIMER_ENAB;
1054                 ap->state = ANEG_STATE_RESTART;
1055
1056                 /* fallthru */
1057         case ANEG_STATE_RESTART:
1058                 delta = ap->cur_time - ap->link_time;
1059                 if (delta > ANEG_STATE_SETTLE_TIME) {
1060                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
1061                 } else {
1062                         ret = ANEG_TIMER_ENAB;
1063                 }
1064                 break;
1065
1066         case ANEG_STATE_DISABLE_LINK_OK:
1067                 ret = ANEG_DONE;
1068                 break;
1069
1070         case ANEG_STATE_ABILITY_DETECT_INIT:
1071                 ap->flags &= ~(MR_TOGGLE_TX);
1072                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
1073                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1074                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1075                 tw32_carefully(MAC_MODE, tp->mac_mode);
1076
1077                 ap->state = ANEG_STATE_ABILITY_DETECT;
1078                 break;
1079
1080         case ANEG_STATE_ABILITY_DETECT:
1081                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
1082                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
1083                 }
1084                 break;
1085
1086         case ANEG_STATE_ACK_DETECT_INIT:
1087                 ap->txconfig |= ANEG_CFG_ACK;
1088                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1089                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1090                 tw32_carefully(MAC_MODE, tp->mac_mode);
1091
1092                 ap->state = ANEG_STATE_ACK_DETECT;
1093
1094                 /* fallthru */
1095         case ANEG_STATE_ACK_DETECT:
1096                 if (ap->ack_match != 0) {
1097                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
1098                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
1099                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
1100                         } else {
1101                                 ap->state = ANEG_STATE_AN_ENABLE;
1102                         }
1103                 } else if (ap->ability_match != 0 &&
1104                            ap->rxconfig == 0) {
1105                         ap->state = ANEG_STATE_AN_ENABLE;
1106                 }
1107                 break;
1108
1109         case ANEG_STATE_COMPLETE_ACK_INIT:
1110                 if (ap->rxconfig & ANEG_CFG_INVAL) {
1111                         ret = ANEG_FAILED;
1112                         break;
1113                 }
1114                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
1115                                MR_LP_ADV_HALF_DUPLEX |
1116                                MR_LP_ADV_SYM_PAUSE |
1117                                MR_LP_ADV_ASYM_PAUSE |
1118                                MR_LP_ADV_REMOTE_FAULT1 |
1119                                MR_LP_ADV_REMOTE_FAULT2 |
1120                                MR_LP_ADV_NEXT_PAGE |
1121                                MR_TOGGLE_RX |
1122                                MR_NP_RX);
1123                 if (ap->rxconfig & ANEG_CFG_FD)
1124                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
1125                 if (ap->rxconfig & ANEG_CFG_HD)
1126                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
1127                 if (ap->rxconfig & ANEG_CFG_PS1)
1128                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
1129                 if (ap->rxconfig & ANEG_CFG_PS2)
1130                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
1131                 if (ap->rxconfig & ANEG_CFG_RF1)
1132                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
1133                 if (ap->rxconfig & ANEG_CFG_RF2)
1134                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
1135                 if (ap->rxconfig & ANEG_CFG_NP)
1136                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
1137
1138                 ap->link_time = ap->cur_time;
1139
1140                 ap->flags ^= (MR_TOGGLE_TX);
1141                 if (ap->rxconfig & 0x0008)
1142                         ap->flags |= MR_TOGGLE_RX;
1143                 if (ap->rxconfig & ANEG_CFG_NP)
1144                         ap->flags |= MR_NP_RX;
1145                 ap->flags |= MR_PAGE_RX;
1146
1147                 ap->state = ANEG_STATE_COMPLETE_ACK;
1148                 ret = ANEG_TIMER_ENAB;
1149                 break;
1150
1151         case ANEG_STATE_COMPLETE_ACK:
1152                 if (ap->ability_match != 0 &&
1153                     ap->rxconfig == 0) {
1154                         ap->state = ANEG_STATE_AN_ENABLE;
1155                         break;
1156                 }
1157                 delta = ap->cur_time - ap->link_time;
1158                 if (delta > ANEG_STATE_SETTLE_TIME) {
1159                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
1160                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
1161                         } else {
1162                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
1163                                     !(ap->flags & MR_NP_RX)) {
1164                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
1165                                 } else {
1166                                         ret = ANEG_FAILED;
1167                                 }
1168                         }
1169                 }
1170                 break;
1171
1172         case ANEG_STATE_IDLE_DETECT_INIT:
1173                 ap->link_time = ap->cur_time;
1174                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
1175                 tw32_carefully(MAC_MODE, tp->mac_mode);
1176
1177                 ap->state = ANEG_STATE_IDLE_DETECT;
1178                 ret = ANEG_TIMER_ENAB;
1179                 break;
1180
1181         case ANEG_STATE_IDLE_DETECT:
1182                 if (ap->ability_match != 0 &&
1183                     ap->rxconfig == 0) {
1184                         ap->state = ANEG_STATE_AN_ENABLE;
1185                         break;
1186                 }
1187                 delta = ap->cur_time - ap->link_time;
1188                 if (delta > ANEG_STATE_SETTLE_TIME) {
1189                         /* XXX another gem from the Broadcom driver :( */
1190                         ap->state = ANEG_STATE_LINK_OK;
1191                 }
1192                 break;
1193
1194         case ANEG_STATE_LINK_OK:
1195                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
1196                 ret = ANEG_DONE;
1197                 break;
1198
1199         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
1200                 /* ??? unimplemented */
1201                 break;
1202
1203         case ANEG_STATE_NEXT_PAGE_WAIT:
1204                 /* ??? unimplemented */
1205                 break;
1206
1207         default:
1208                 ret = ANEG_FAILED;
1209                 break;
1210         };
1211
1212         return ret;
1213 }
1214
1215 static int tg3_setup_fiber_phy(struct tg3 *tp)
1216 {
1217         uint32_t orig_pause_cfg;
1218         uint16_t orig_active_speed;
1219         uint8_t orig_active_duplex;
1220         int current_link_up;
1221         int i;
1222
1223         orig_pause_cfg =
1224                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
1225                                   TG3_FLAG_TX_PAUSE));
1226         orig_active_speed = tp->link_config.active_speed;
1227         orig_active_duplex = tp->link_config.active_duplex;
1228
1229         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
1230         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
1231         tw32_carefully(MAC_MODE, tp->mac_mode);
1232
1233         /* Reset when initting first time or we have a link. */
1234         if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) ||
1235             (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED)) {
1236                 /* Set PLL lock range. */
1237                 tg3_writephy(tp, 0x16, 0x8007);
1238
1239                 /* SW reset */
1240                 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
1241
1242                 /* Wait for reset to complete. */
1243                 mdelay(5);
1244
1245                 /* Config mode; select PMA/Ch 1 regs. */
1246                 tg3_writephy(tp, 0x10, 0x8411);
1247
1248                 /* Enable auto-lock and comdet, select txclk for tx. */
1249                 tg3_writephy(tp, 0x11, 0x0a10);
1250
1251                 tg3_writephy(tp, 0x18, 0x00a0);
1252                 tg3_writephy(tp, 0x16, 0x41ff);
1253
1254                 /* Assert and deassert POR. */
1255                 tg3_writephy(tp, 0x13, 0x0400);
1256                 udelay(40);
1257                 tg3_writephy(tp, 0x13, 0x0000);
1258
1259                 tg3_writephy(tp, 0x11, 0x0a50);
1260                 udelay(40);
1261                 tg3_writephy(tp, 0x11, 0x0a10);
1262
1263                 /* Wait for signal to stabilize */
1264                 mdelay(150);
1265
1266                 /* Deselect the channel register so we can read the PHYID
1267                  * later.
1268                  */
1269                 tg3_writephy(tp, 0x10, 0x8011);
1270         }
1271
1272         /* Disable link change interrupt.  */
1273         tw32_carefully(MAC_EVENT, 0);
1274
1275         current_link_up = 0;
1276         if (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) {
1277                 if (!(tp->tg3_flags & TG3_FLAG_GOT_SERDES_FLOWCTL)) {
1278                         struct tg3_fiber_aneginfo aninfo;
1279                         int status = ANEG_FAILED;
1280                         unsigned int tick;
1281                         uint32_t tmp;
1282
1283                         memset(&aninfo, 0, sizeof(aninfo));
1284                         aninfo.flags |= (MR_AN_ENABLE);
1285
1286                         tw32(MAC_TX_AUTO_NEG, 0);
1287
1288                         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
1289                         tw32_carefully(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
1290
1291                         tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
1292
1293                         aninfo.state = ANEG_STATE_UNKNOWN;
1294                         aninfo.cur_time = 0;
1295                         tick = 0;
1296                         while (++tick < 195000) {
1297                                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
1298                                 if (status == ANEG_DONE ||
1299                                     status == ANEG_FAILED)
1300                                         break;
1301
1302                                 udelay(1);
1303                         }
1304
1305                         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
1306                         tw32_carefully(MAC_MODE, tp->mac_mode);
1307
1308                         if (status == ANEG_DONE &&
1309                             (aninfo.flags &
1310                              (MR_AN_COMPLETE | MR_LINK_OK |
1311                               MR_LP_ADV_FULL_DUPLEX))) {
1312                                 uint32_t local_adv, remote_adv;
1313
1314                                 local_adv = ADVERTISE_PAUSE_CAP;
1315                                 remote_adv = 0;
1316                                 if (aninfo.flags & MR_LP_ADV_SYM_PAUSE)
1317                                         remote_adv |= LPA_PAUSE_CAP;
1318                                 if (aninfo.flags & MR_LP_ADV_ASYM_PAUSE)
1319                                         remote_adv |= LPA_PAUSE_ASYM;
1320
1321                                 tg3_setup_flow_control(tp, local_adv, remote_adv);
1322
1323                                 tp->tg3_flags |=
1324                                         TG3_FLAG_GOT_SERDES_FLOWCTL;
1325                                 current_link_up = 1;
1326                         }
1327                         for (i = 0; i < 60; i++) {
1328                                 udelay(20);
1329                                 tw32_carefully(MAC_STATUS,
1330                                         (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED));
1331                                 if ((tr32(MAC_STATUS) &
1332                                      (MAC_STATUS_SYNC_CHANGED |
1333                                       MAC_STATUS_CFG_CHANGED)) == 0)
1334                                         break;
1335                         }
1336                         if (current_link_up == 0 &&
1337                             (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED)) {
1338                                 current_link_up = 1;
1339                         }
1340                 } else {
1341                         /* Forcing 1000FD link up. */
1342                         current_link_up = 1;
1343                 }
1344         }
1345
1346         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1347         tw32_carefully(MAC_MODE, tp->mac_mode);
1348
1349         tp->hw_status->status =
1350                 (SD_STATUS_UPDATED |
1351                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
1352
1353         for (i = 0; i < 100; i++) {
1354                 udelay(20);
1355                 tw32_carefully(MAC_STATUS,
1356                         (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED));
1357                 if ((tr32(MAC_STATUS) &
1358                      (MAC_STATUS_SYNC_CHANGED |
1359                       MAC_STATUS_CFG_CHANGED)) == 0)
1360                         break;
1361         }
1362
1363         if ((tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) == 0)
1364                 current_link_up = 0;
1365
1366         if (current_link_up == 1) {
1367                 tp->link_config.active_speed = SPEED_1000;
1368                 tp->link_config.active_duplex = DUPLEX_FULL;
1369                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
1370                                     LED_CTRL_LNKLED_OVERRIDE |
1371                                     LED_CTRL_1000MBPS_ON));
1372         } else {
1373                 tp->link_config.active_speed = SPEED_INVALID;
1374                 tp->link_config.active_duplex = DUPLEX_INVALID;
1375                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
1376                                     LED_CTRL_LNKLED_OVERRIDE |
1377                                     LED_CTRL_TRAFFIC_OVERRIDE));
1378         }
1379
1380         if (current_link_up != tp->carrier_ok) {
1381                 tp->carrier_ok = current_link_up;
1382                 tg3_link_report(tp);
1383         } else {
1384                 uint32_t now_pause_cfg =
1385                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
1386                                          TG3_FLAG_TX_PAUSE);
1387                 if (orig_pause_cfg != now_pause_cfg ||
1388                     orig_active_speed != tp->link_config.active_speed ||
1389                     orig_active_duplex != tp->link_config.active_duplex)
1390                         tg3_link_report(tp);
1391         }
1392
1393         if ((tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) == 0) {
1394                 tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_LINK_POLARITY);
1395                 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
1396                         tw32_carefully(MAC_MODE, tp->mac_mode);
1397                 }
1398         }
1399
1400         return 0;
1401 }
1402 #else
1403 #define tg3_setup_fiber_phy(TP) (-EINVAL)
1404 #endif /* SUPPORT_FIBER_PHY */
1405
1406 static int tg3_setup_phy(struct tg3 *tp)
1407 {
1408         int err;
1409
1410         if (tp->phy_id == PHY_ID_SERDES) {
1411                 err = tg3_setup_fiber_phy(tp);
1412         } else {
1413                 err = tg3_setup_copper_phy(tp);
1414         }
1415
1416         if (tp->link_config.active_speed == SPEED_1000 &&
1417             tp->link_config.active_duplex == DUPLEX_HALF)
1418                 tw32(MAC_TX_LENGTHS,
1419                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1420                       (6 << TX_LENGTHS_IPG_SHIFT) |
1421                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1422         else
1423                 tw32(MAC_TX_LENGTHS,
1424                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1425                       (6 << TX_LENGTHS_IPG_SHIFT) |
1426                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1427
1428         return err;
1429 }
1430
1431
1432 #define MAX_WAIT_CNT 1000
1433
1434 /* To stop a block, clear the enable bit and poll till it
1435  * clears.  
1436  */
1437 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, uint32_t enable_bit)
1438 {
1439         unsigned int i;
1440         uint32_t val;
1441
1442         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
1443             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1444                 switch(ofs) {
1445                 case RCVLSC_MODE:
1446                 case DMAC_MODE:
1447                 case MBFREE_MODE:
1448                 case BUFMGR_MODE:
1449                 case MEMARB_MODE:
1450                         /* We can't enable/disable these bits of the
1451                          * 5705/5750, just say success.
1452                          */
1453                         return 0;
1454                 default:
1455                         break;
1456                 }
1457         }
1458         val = tr32(ofs);
1459         val &= ~enable_bit;
1460         tw32(ofs, val);
1461         tr32(ofs);
1462
1463         for (i = 0; i < MAX_WAIT_CNT; i++) {
1464                 udelay(100);
1465                 val = tr32(ofs);
1466                 if ((val & enable_bit) == 0)
1467                         break;
1468         }
1469
1470         if (i == MAX_WAIT_CNT) {
1471                 printf("tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
1472                        ofs, enable_bit);
1473                 return -ENODEV;
1474         }
1475
1476         return 0;
1477 }
1478
1479 static int tg3_abort_hw(struct tg3 *tp)
1480 {
1481         int i, err;
1482
1483         tg3_disable_ints(tp);
1484
1485         tp->rx_mode &= ~RX_MODE_ENABLE;
1486         tw32_carefully(MAC_RX_MODE, tp->rx_mode);
1487
1488         err  = tg3_stop_block(tp, RCVBDI_MODE,   RCVBDI_MODE_ENABLE);
1489         err |= tg3_stop_block(tp, RCVLPC_MODE,   RCVLPC_MODE_ENABLE);
1490         err |= tg3_stop_block(tp, RCVLSC_MODE,   RCVLSC_MODE_ENABLE);
1491         err |= tg3_stop_block(tp, RCVDBDI_MODE,  RCVDBDI_MODE_ENABLE);
1492         err |= tg3_stop_block(tp, RCVDCC_MODE,   RCVDCC_MODE_ENABLE);
1493         err |= tg3_stop_block(tp, RCVCC_MODE,    RCVCC_MODE_ENABLE);
1494
1495         err |= tg3_stop_block(tp, SNDBDS_MODE,   SNDBDS_MODE_ENABLE);
1496         err |= tg3_stop_block(tp, SNDBDI_MODE,   SNDBDI_MODE_ENABLE);
1497         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1498         err |= tg3_stop_block(tp, RDMAC_MODE,    RDMAC_MODE_ENABLE);
1499         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
1500         err |= tg3_stop_block(tp, SNDBDC_MODE,   SNDBDC_MODE_ENABLE);
1501         if (err)
1502                 goto out;
1503
1504         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
1505         tw32_carefully(MAC_MODE, tp->mac_mode);
1506
1507         tp->tx_mode &= ~TX_MODE_ENABLE;
1508         tw32_carefully(MAC_TX_MODE, tp->tx_mode);
1509
1510         for (i = 0; i < MAX_WAIT_CNT; i++) {
1511                 udelay(100);
1512                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
1513                         break;
1514         }
1515         if (i >= MAX_WAIT_CNT) {
1516                 printf("tg3_abort_hw timed out TX_MODE_ENABLE will not clear MAC_TX_MODE=%x\n",
1517                         tr32(MAC_TX_MODE));
1518                 return -ENODEV;
1519         }
1520
1521         err  = tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE);
1522         err |= tg3_stop_block(tp, WDMAC_MODE,  WDMAC_MODE_ENABLE);
1523         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE);
1524
1525         tw32(FTQ_RESET, 0xffffffff);
1526         tw32(FTQ_RESET, 0x00000000);
1527
1528         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE);
1529         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE);
1530         if (err)
1531                 goto out;
1532
1533         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
1534
1535 out:
1536         return err;
1537 }
1538
1539 static void tg3_chip_reset(struct tg3 *tp)
1540 {
1541         uint32_t val;
1542
1543         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_5704)) {
1544                 /* Force NVRAM to settle.
1545                  * This deals with a chip bug which can result in EEPROM
1546                  * corruption.
1547                  */
1548                 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
1549                         int i;
1550         
1551                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
1552                         for (i = 0; i < 100000; i++) {
1553                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
1554                                         break;
1555                                 udelay(10);
1556                         }
1557                 }
1558         }
1559         /* In Etherboot we don't need to worry about the 5701
1560          * REG_WRITE_BUG because we do all register writes indirectly.
1561          */
1562
1563         // Alf: here patched
1564         /* do the reset */
1565         val = GRC_MISC_CFG_CORECLK_RESET;
1566         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
1567             || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1568                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
1569         }
1570
1571         // Alf : Please VALIDATE THIS.
1572         // It is necessary in my case (5751) to prevent a reboot, but
1573         // I have no idea about a side effect on any other version.
1574         // It appears to be what's done in tigon3.c from Broadcom
1575         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
1576           tw32(GRC_MISC_CFG, 0x20000000) ;
1577           val |= 0x20000000 ;
1578         }
1579
1580         tw32(GRC_MISC_CFG, val);
1581
1582         /* Flush PCI posted writes.  The normal MMIO registers
1583          * are inaccessible at this time so this is the only
1584          * way to make this reliably.  I tried to use indirect
1585          * register read/write but this upset some 5701 variants.
1586          */
1587         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
1588
1589         udelay(120);
1590
1591         /* Re-enable indirect register accesses. */
1592         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
1593                                tp->misc_host_ctrl);
1594
1595         /* Set MAX PCI retry to zero. */
1596         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
1597         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
1598             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
1599                 val |= PCISTATE_RETRY_SAME_DMA;
1600         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
1601
1602         pci_restore_state(tp->pdev, tp->pci_cfg_state);
1603
1604         /* Make sure PCI-X relaxed ordering bit is clear. */
1605         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
1606         val &= ~PCIX_CAPS_RELAXED_ORDERING;
1607         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
1608
1609         tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
1610
1611         if (((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0) &&
1612                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
1613                 tp->pci_clock_ctrl |=
1614                         (CLOCK_CTRL_FORCE_CLKRUN | CLOCK_CTRL_CLKRUN_OENABLE);
1615                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
1616         }
1617
1618         tw32(TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
1619 }
1620
1621 static void tg3_stop_fw(struct tg3 *tp)
1622 {
1623         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
1624                 uint32_t val;
1625                 int i;
1626
1627                 tg3_write_mem(NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1628                 val = tr32(GRC_RX_CPU_EVENT);
1629                 val |= (1 << 14);
1630                 tw32(GRC_RX_CPU_EVENT, val);
1631
1632                 /* Wait for RX cpu to ACK the event.  */
1633                 for (i = 0; i < 100; i++) {
1634                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
1635                                 break;
1636                         udelay(1);
1637                 }
1638         }
1639 }
1640
1641 static int tg3_restart_fw(struct tg3 *tp, uint32_t state)
1642 {
1643         uint32_t val;
1644         int i;
1645         
1646         tg3_write_mem(NIC_SRAM_FIRMWARE_MBOX, 
1647                 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1648         /* Wait for firmware initialization to complete. */
1649         for (i = 0; i < 100000; i++) {
1650                 tg3_read_mem(NIC_SRAM_FIRMWARE_MBOX, &val);
1651                 if (val == (uint32_t) ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1652                         break;
1653                 udelay(10);
1654         }
1655         if (i >= 100000 &&
1656                     !(tp->tg3_flags2 & TG3_FLG2_SUN_5704)) {
1657                 printf("Firmware will not restart magic=%x\n",
1658                         val);
1659                 return -ENODEV;
1660         }
1661         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1662           state = DRV_STATE_SUSPEND;
1663         }
1664
1665         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
1666             (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)) {
1667           // Enable PCIE bug fix
1668           tg3_read_mem(0x7c00, &val);
1669           tg3_write_mem(0x7c00, val | 0x02000000);
1670         }
1671         tg3_write_mem(NIC_SRAM_FW_DRV_STATE_MBOX, state);
1672         return 0;
1673 }
1674
1675 static int tg3_halt(struct tg3 *tp)
1676 {
1677         tg3_stop_fw(tp);
1678         tg3_abort_hw(tp);
1679         tg3_chip_reset(tp);
1680         return tg3_restart_fw(tp, DRV_STATE_UNLOAD);
1681 }
1682
1683 static void __tg3_set_mac_addr(struct tg3 *tp)
1684 {
1685         uint32_t addr_high, addr_low;
1686         int i;
1687
1688         addr_high = ((tp->nic->node_addr[0] << 8) |
1689                      tp->nic->node_addr[1]);
1690         addr_low = ((tp->nic->node_addr[2] << 24) |
1691                     (tp->nic->node_addr[3] << 16) |
1692                     (tp->nic->node_addr[4] <<  8) |
1693                     (tp->nic->node_addr[5] <<  0));
1694         for (i = 0; i < 4; i++) {
1695                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
1696                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
1697         }
1698
1699         if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
1700                 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
1701                 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705)) {
1702                 for(i = 0; i < 12; i++) {
1703                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
1704                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
1705                 }
1706         }
1707         addr_high = (tp->nic->node_addr[0] +
1708                      tp->nic->node_addr[1] +
1709                      tp->nic->node_addr[2] +
1710                      tp->nic->node_addr[3] +
1711                      tp->nic->node_addr[4] +
1712                      tp->nic->node_addr[5]) &
1713                 TX_BACKOFF_SEED_MASK;
1714         tw32(MAC_TX_BACKOFF_SEED, addr_high);
1715 }
1716
1717 static void tg3_set_bdinfo(struct tg3 *tp, uint32_t bdinfo_addr,
1718                            dma_addr_t mapping, uint32_t maxlen_flags,
1719                            uint32_t nic_addr)
1720 {
1721         tg3_write_mem((bdinfo_addr +
1722                        TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
1723                       ((uint64_t) mapping >> 32));
1724         tg3_write_mem((bdinfo_addr +
1725                        TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
1726                       ((uint64_t) mapping & 0xffffffff));
1727         tg3_write_mem((bdinfo_addr +
1728                        TG3_BDINFO_MAXLEN_FLAGS),
1729                        maxlen_flags);
1730         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1731                 tg3_write_mem((bdinfo_addr + TG3_BDINFO_NIC_ADDR), nic_addr);
1732         }
1733 }
1734
1735
1736 static void tg3_init_rings(struct tg3 *tp)
1737 {
1738         unsigned i;
1739
1740         /* Zero out the tg3 variables */
1741         memset(&tg3_bss, 0, sizeof(tg3_bss));
1742         tp->rx_std    = &tg3_bss.rx_std[0];
1743         tp->rx_rcb    = &tg3_bss.rx_rcb[0];
1744         tp->tx_ring   = &tg3_bss.tx_ring[0];
1745         tp->hw_status = &tg3_bss.hw_status;
1746         tp->hw_stats  = &tg3_bss.hw_stats;
1747         tp->mac_mode  = 0;
1748
1749
1750         /* Initialize tx/rx rings for packet processing.
1751          *
1752          * The chip has been shut down and the driver detached from
1753          * the networking, so no interrupts or new tx packets will
1754          * end up in the driver.
1755          */
1756
1757         /* Initialize invariants of the rings, we only set this
1758          * stuff once.  This works because the card does not
1759          * write into the rx buffer posting rings.
1760          */
1761         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
1762                 struct tg3_rx_buffer_desc *rxd;
1763
1764                 rxd = &tp->rx_std[i];
1765                 rxd->idx_len = (RX_PKT_BUF_SZ - 2 - 64) << RXD_LEN_SHIFT;
1766                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
1767                 rxd->opaque = (RXD_OPAQUE_RING_STD | (i << RXD_OPAQUE_INDEX_SHIFT));
1768
1769                 /* Note where the receive buffer for the ring is placed */
1770                 rxd->addr_hi = 0;
1771                 rxd->addr_lo = virt_to_bus(
1772                         &tg3_bss.rx_bufs[i%TG3_DEF_RX_RING_PENDING][2]);
1773         }
1774 }
1775
1776 #define TG3_WRITE_SETTINGS(TABLE) \
1777 do { \
1778         const uint32_t *_table, *_end; \
1779         _table = TABLE; \
1780         _end = _table + sizeof(TABLE)/sizeof(TABLE[0]);  \
1781         for(; _table < _end; _table += 2) { \
1782                 tw32(_table[0], _table[1]); \
1783         } \
1784 } while(0)
1785
1786
1787 /* initialize/reset the tg3 */
1788 static int tg3_setup_hw(struct tg3 *tp)
1789 {
1790         uint32_t val, rdmac_mode;
1791         int i, err, limit;
1792
1793         /* Simply don't support setups with extremly buggy firmware in etherboot */
1794         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
1795                 printf("Error 5701_A0 firmware bug detected\n");
1796                 return -EINVAL;
1797         }
1798
1799         tg3_disable_ints(tp);
1800
1801         /* Originally this was all in tg3_init_hw */
1802
1803         /* Force the chip into D0. */
1804         tg3_set_power_state_0(tp);
1805
1806         tg3_switch_clocks(tp);
1807
1808         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
1809
1810         // This should go somewhere else
1811 #define T3_PCIE_CAPABILITY_ID_REG           0xD0
1812 #define T3_PCIE_CAPABILITY_ID               0x10
1813 #define T3_PCIE_CAPABILITY_REG              0xD2
1814
1815         /* Originally this was all in tg3_reset_hw */
1816
1817         tg3_stop_fw(tp);
1818
1819         /* No need to call tg3_abort_hw here, it is called before tg3_setup_hw. */
1820
1821         tg3_chip_reset(tp);
1822
1823         tw32(GRC_MODE, tp->grc_mode);  /* Redundant? */
1824
1825         err = tg3_restart_fw(tp, DRV_STATE_START);
1826         if (err)
1827                 return err;
1828
1829         if (tp->phy_id == PHY_ID_SERDES) {
1830                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
1831         }
1832         tw32_carefully(MAC_MODE, tp->mac_mode);
1833
1834
1835         /* This works around an issue with Athlon chipsets on
1836          * B3 tigon3 silicon.  This bit has no effect on any
1837          * other revision.
1838          * Alf: Except 5750 ! (which reboots)
1839          */
1840
1841         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
1842           tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
1843         tw32_carefully(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
1844
1845         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
1846             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
1847                 val = tr32(TG3PCI_PCISTATE);
1848                 val |= PCISTATE_RETRY_SAME_DMA;
1849                 tw32(TG3PCI_PCISTATE, val);
1850         }
1851
1852         /* Descriptor ring init may make accesses to the
1853          * NIC SRAM area to setup the TX descriptors, so we
1854          * can only do this after the hardware has been
1855          * successfully reset.
1856          */
1857         tg3_init_rings(tp);
1858
1859         /* Clear statistics/status block in chip */
1860         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1861                 for (i = NIC_SRAM_STATS_BLK;
1862                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
1863                      i += sizeof(uint32_t)) {
1864                         tg3_write_mem(i, 0);
1865                         udelay(40);
1866                 }
1867         }
1868
1869         /* This value is determined during the probe time DMA
1870          * engine test, tg3_setup_dma.
1871          */
1872         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
1873
1874         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
1875                           GRC_MODE_4X_NIC_SEND_RINGS |
1876                           GRC_MODE_NO_TX_PHDR_CSUM |
1877                           GRC_MODE_NO_RX_PHDR_CSUM);
1878         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
1879         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1880         tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
1881
1882         tw32(GRC_MODE,
1883                 tp->grc_mode | 
1884                 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
1885
1886         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
1887         tw32(GRC_MISC_CFG,
1888              (65 << GRC_MISC_CFG_PRESCALAR_SHIFT));
1889
1890         /* Initialize MBUF/DESC pool. */
1891         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1892                 /* Do nothing. */
1893         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1894                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
1895                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
1896                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
1897                 else
1898                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
1899                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
1900                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
1901         }
1902         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)) {
1903                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
1904                      tp->bufmgr_config.mbuf_read_dma_low_water);
1905                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
1906                      tp->bufmgr_config.mbuf_mac_rx_low_water);
1907                 tw32(BUFMGR_MB_HIGH_WATER,
1908                      tp->bufmgr_config.mbuf_high_water);
1909         } else {
1910                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
1911                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
1912                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
1913                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
1914                 tw32(BUFMGR_MB_HIGH_WATER,
1915                      tp->bufmgr_config.mbuf_high_water_jumbo);
1916         }
1917         tw32(BUFMGR_DMA_LOW_WATER,
1918              tp->bufmgr_config.dma_low_water);
1919         tw32(BUFMGR_DMA_HIGH_WATER,
1920              tp->bufmgr_config.dma_high_water);
1921
1922         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
1923         for (i = 0; i < 2000; i++) {
1924                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
1925                         break;
1926                 udelay(10);
1927         }
1928         if (i >= 2000) {
1929                 printf("tg3_setup_hw cannot enable BUFMGR\n");
1930                 return -ENODEV;
1931         }
1932
1933         tw32(FTQ_RESET, 0xffffffff);
1934         tw32(FTQ_RESET, 0x00000000);
1935         for (i = 0; i < 2000; i++) {
1936                 if (tr32(FTQ_RESET) == 0x00000000)
1937                         break;
1938                 udelay(10);
1939         }
1940         if (i >= 2000) {
1941                 printf("tg3_setup_hw cannot reset FTQ\n");
1942                 return -ENODEV;
1943         }
1944
1945         /* Initialize TG3_BDINFO's at:
1946          *  RCVDBDI_STD_BD:     standard eth size rx ring
1947          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
1948          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
1949          *
1950          * like so:
1951          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
1952          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
1953          *                              ring attribute flags
1954          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
1955          *
1956          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
1957          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
1958          *
1959          * ??? No space allocated for mini receive ring? :(
1960          *
1961          * The size of each ring is fixed in the firmware, but the location is
1962          * configurable.
1963          */
1964         {
1965                 static const uint32_t table_all[] = {
1966                         /* Setup replenish thresholds. */
1967                         RCVBDI_STD_THRESH, TG3_DEF_RX_RING_PENDING / 8,
1968
1969                         /* Etherboot lives below 4GB */
1970                         RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, 0,
1971                         RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, NIC_SRAM_RX_BUFFER_DESC,
1972                 };
1973                 static const uint32_t table_not_5705[] = {
1974                         /* Buffer maximum length */
1975                         RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT,
1976                         
1977                         /* Disable the mini frame rx ring */
1978                         RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,      BDINFO_FLAGS_DISABLED,
1979                         
1980                         /* Disable the jumbo frame rx ring */
1981                         RCVBDI_JUMBO_THRESH, 0,
1982                         RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, BDINFO_FLAGS_DISABLED,
1983                         
1984                         
1985                 };
1986                 TG3_WRITE_SETTINGS(table_all);
1987                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, 
1988                         virt_to_bus(tp->rx_std));
1989                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
1990                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
1991                         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
1992                                 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
1993                 } else {
1994                         TG3_WRITE_SETTINGS(table_not_5705);
1995                 }
1996         }
1997
1998         
1999         /* There is only one send ring on 5705, no need to explicitly
2000          * disable the others.
2001          */
2002         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
2003             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
2004                 /* Clear out send RCB ring in SRAM. */
2005                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
2006                         tg3_write_mem(i + TG3_BDINFO_MAXLEN_FLAGS, BDINFO_FLAGS_DISABLED);
2007         }
2008
2009         tp->tx_prod = 0;
2010         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
2011         tw32_mailbox2(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
2012
2013         tg3_set_bdinfo(tp,
2014                 NIC_SRAM_SEND_RCB,
2015                 virt_to_bus(tp->tx_ring),
2016                 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
2017                 NIC_SRAM_TX_BUFFER_DESC);
2018
2019         /* There is only one receive return ring on 5705, no need to explicitly
2020          * disable the others.
2021          */
2022         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
2023                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK; i += TG3_BDINFO_SIZE) {
2024                         tg3_write_mem(i + TG3_BDINFO_MAXLEN_FLAGS,
2025                                 BDINFO_FLAGS_DISABLED);
2026                 }
2027         }
2028
2029         tp->rx_rcb_ptr = 0;
2030         tw32_mailbox2(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
2031
2032         tg3_set_bdinfo(tp,
2033                 NIC_SRAM_RCV_RET_RCB,
2034                 virt_to_bus(tp->rx_rcb),
2035                 (TG3_RX_RCB_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
2036                 0);
2037
2038         tp->rx_std_ptr = TG3_DEF_RX_RING_PENDING;
2039         tw32_mailbox2(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
2040                      tp->rx_std_ptr);
2041
2042         tw32_mailbox2(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW, 0);
2043
2044         /* Initialize MAC address and backoff seed. */
2045         __tg3_set_mac_addr(tp);
2046
2047         /* Calculate RDMAC_MODE setting early, we need it to determine
2048          * the RCVLPC_STATE_ENABLE mask.
2049          */
2050         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
2051                 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
2052                 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
2053                 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
2054                 RDMAC_MODE_LNGREAD_ENAB);
2055         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
2056                 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
2057         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
2058             tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
2059             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
2060                         if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
2061                                 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
2062                                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
2063                         }
2064         }
2065
2066         /* Setup host coalescing engine. */
2067         tw32(HOSTCC_MODE, 0);
2068         for (i = 0; i < 2000; i++) {
2069                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
2070                         break;
2071                 udelay(10);
2072         }
2073
2074         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
2075                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
2076         tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
2077
2078         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
2079         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
2080                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
2081                                        GRC_LCLCTRL_GPIO_OUTPUT1);
2082         tw32_carefully(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
2083
2084         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
2085         tr32(MAILBOX_INTERRUPT_0);
2086
2087         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 ||
2088             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
2089                 tw32_carefully(DMAC_MODE, DMAC_MODE_ENABLE);
2090         }
2091
2092         val = ( WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
2093                 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
2094                 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
2095                 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
2096                 WDMAC_MODE_LNGREAD_ENAB);
2097         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
2098              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
2099              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
2100                 if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
2101                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) /* &&
2102                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)*/) {
2103                         val |= WDMAC_MODE_RX_ACCEL;
2104                 }
2105         }
2106         tw32_carefully(WDMAC_MODE, val);
2107
2108         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
2109                 val = tr32(TG3PCI_X_CAPS);
2110                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
2111                         val &= PCIX_CAPS_BURST_MASK;
2112                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
2113                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2114                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
2115                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
2116                         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
2117                                 val |= (tp->split_mode_max_reqs <<
2118                                         PCIX_CAPS_SPLIT_SHIFT);
2119                 }
2120                 tw32(TG3PCI_X_CAPS, val);
2121         }
2122
2123         tw32_carefully(RDMAC_MODE, rdmac_mode);
2124         {
2125                 static const uint32_t table_all[] = {
2126                         /* MTU + ethernet header + FCS + optional VLAN tag */
2127                         MAC_RX_MTU_SIZE, ETH_MAX_MTU + ETH_HLEN + 8,
2128                         
2129                         /* The slot time is changed by tg3_setup_phy if we
2130                          * run at gigabit with half duplex.
2131                          */
2132                         MAC_TX_LENGTHS, 
2133                         (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2134                         (6 << TX_LENGTHS_IPG_SHIFT) |
2135                         (32 << TX_LENGTHS_SLOT_TIME_SHIFT),
2136                         
2137                         /* Receive rules. */
2138                         MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS,
2139                         RCVLPC_CONFIG, 0x0181,
2140                         
2141                         /* Receive/send statistics. */
2142                         RCVLPC_STATS_ENABLE, 0xffffff,
2143                         RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE,
2144                         SNDDATAI_STATSENAB, 0xffffff,
2145                         SNDDATAI_STATSCTRL, (SNDDATAI_SCTRL_ENABLE |SNDDATAI_SCTRL_FASTUPD),
2146                         
2147                         /* Host coalescing engine */
2148                         HOSTCC_RXCOL_TICKS, 0,
2149                         HOSTCC_TXCOL_TICKS, LOW_TXCOL_TICKS,
2150                         HOSTCC_RXMAX_FRAMES, 1,
2151                         HOSTCC_TXMAX_FRAMES, LOW_RXMAX_FRAMES,
2152                         HOSTCC_RXCOAL_MAXF_INT, 1,
2153                         HOSTCC_TXCOAL_MAXF_INT, 0,
2154                         
2155                         /* Status/statistics block address. */
2156                         /* Etherboot lives below 4GB, so HIGH == 0 */
2157                         HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, 0,
2158
2159                         /* No need to enable 32byte coalesce mode. */
2160                         HOSTCC_MODE, HOSTCC_MODE_ENABLE | 0,
2161                         
2162                         RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE,
2163                         RCVLPC_MODE, RCVLPC_MODE_ENABLE,
2164                         
2165                         RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE,
2166
2167                         SNDDATAC_MODE, SNDDATAC_MODE_ENABLE,
2168                         SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE,
2169                         RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB,
2170                         RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ,
2171                         SNDDATAI_MODE, SNDDATAI_MODE_ENABLE,
2172                         SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE,
2173                         SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE,
2174                         
2175                         /* Accept all multicast frames. */
2176                         MAC_HASH_REG_0, 0xffffffff,
2177                         MAC_HASH_REG_1, 0xffffffff,
2178                         MAC_HASH_REG_2, 0xffffffff,
2179                         MAC_HASH_REG_3, 0xffffffff,
2180                 };
2181                 static const uint32_t table_not_5705[] = {
2182                         /* Host coalescing engine */
2183                         HOSTCC_RXCOAL_TICK_INT, 0,
2184                         HOSTCC_TXCOAL_TICK_INT, 0,
2185
2186                         /* Status/statistics block address. */
2187                         /* Etherboot lives below 4GB, so HIGH == 0 */
2188                         HOSTCC_STAT_COAL_TICKS, DEFAULT_STAT_COAL_TICKS,
2189                         HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, 0,
2190                         HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK,
2191                         HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK,
2192
2193                         RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE,
2194
2195                         MBFREE_MODE, MBFREE_MODE_ENABLE,
2196                 };
2197                 TG3_WRITE_SETTINGS(table_all);
2198                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
2199                         virt_to_bus(tp->hw_stats));
2200                 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
2201                         virt_to_bus(tp->hw_status));
2202                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
2203                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
2204                         TG3_WRITE_SETTINGS(table_not_5705);
2205                 }
2206         }
2207
2208         tp->tx_mode = TX_MODE_ENABLE;
2209         tw32_carefully(MAC_TX_MODE, tp->tx_mode);
2210
2211         tp->rx_mode = RX_MODE_ENABLE;
2212         tw32_carefully(MAC_RX_MODE, tp->rx_mode);
2213
2214         tp->mi_mode = MAC_MI_MODE_BASE;
2215         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
2216
2217         tw32(MAC_LED_CTRL, tp->led_ctrl);
2218
2219         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2220         if (tp->phy_id == PHY_ID_SERDES) {
2221                 tw32_carefully(MAC_RX_MODE, RX_MODE_RESET);
2222         }
2223         tp->rx_mode |= RX_MODE_KEEP_VLAN_TAG; /* drop tagged vlan packets */
2224         tw32_carefully(MAC_RX_MODE, tp->rx_mode);
2225
2226         if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
2227                 tw32(MAC_SERDES_CFG, 0x616000);
2228
2229         /* Prevent chip from dropping frames when flow control
2230          * is enabled.
2231          */
2232         tw32(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
2233         tr32(MAC_LOW_WMARK_MAX_RX_FRAME);
2234
2235         err = tg3_setup_phy(tp);
2236
2237         /* Ignore CRC stats */
2238
2239         /* Initialize receive rules. */
2240         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
2241         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
2242         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
2243         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
2244
2245         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
2246             || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750))
2247                 limit = 8;
2248         else
2249                 limit = 16;
2250         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
2251                 limit -= 4;
2252         switch (limit) {
2253         case 16:        tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
2254         case 15:        tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
2255         case 14:        tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
2256         case 13:        tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
2257         case 12:        tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
2258         case 11:        tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
2259         case 10:        tw32(MAC_RCV_RULE_9,  0);  tw32(MAC_RCV_VALUE_9,  0);
2260         case 9:         tw32(MAC_RCV_RULE_8,  0);  tw32(MAC_RCV_VALUE_8,  0);
2261         case 8:         tw32(MAC_RCV_RULE_7,  0);  tw32(MAC_RCV_VALUE_7,  0);
2262         case 7:         tw32(MAC_RCV_RULE_6,  0);  tw32(MAC_RCV_VALUE_6,  0);
2263         case 6:         tw32(MAC_RCV_RULE_5,  0);  tw32(MAC_RCV_VALUE_5,  0);
2264         case 5:         tw32(MAC_RCV_RULE_4,  0);  tw32(MAC_RCV_VALUE_4,  0);
2265         case 4:         /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
2266         case 3:         /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
2267         case 2:
2268         case 1:
2269         default:
2270                 break;
2271         };
2272
2273         return err;
2274 }
2275
2276
2277
2278 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
2279 static void tg3_nvram_init(struct tg3 *tp)
2280 {
2281         tw32(GRC_EEPROM_ADDR,
2282              (EEPROM_ADDR_FSM_RESET |
2283               (EEPROM_DEFAULT_CLOCK_PERIOD <<
2284                EEPROM_ADDR_CLKPERD_SHIFT)));
2285
2286         mdelay(1);
2287
2288         /* Enable seeprom accesses. */
2289         tw32_carefully(GRC_LOCAL_CTRL,
2290                 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
2291
2292         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2293             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2294                 uint32_t nvcfg1;
2295                 
2296                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
2297                         u32 nvaccess = tr32(NVRAM_ACCESS);
2298
2299                         tw32_carefully(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2300                 }
2301
2302                 nvcfg1 = tr32(NVRAM_CFG1);
2303
2304                 tp->tg3_flags |= TG3_FLAG_NVRAM;
2305                 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
2306                         if (nvcfg1 & NVRAM_CFG1_BUFFERED_MODE)
2307                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
2308                 } else {
2309                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
2310                         tw32(NVRAM_CFG1, nvcfg1);
2311                 }
2312
2313                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
2314                         u32 nvaccess = tr32(NVRAM_ACCESS);
2315
2316                         tw32_carefully(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2317                 }
2318
2319
2320         } else {
2321                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
2322         }
2323 }
2324
2325
2326 static int tg3_nvram_read_using_eeprom(
2327         struct tg3 *tp __unused, uint32_t offset, uint32_t *val)
2328 {
2329         uint32_t tmp;
2330         int i;
2331
2332         if (offset > EEPROM_ADDR_ADDR_MASK ||
2333                 (offset % 4) != 0) {
2334                 return -EINVAL;
2335         }
2336
2337         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2338                                         EEPROM_ADDR_DEVID_MASK |
2339                                         EEPROM_ADDR_READ);
2340         tw32(GRC_EEPROM_ADDR,
2341              tmp |
2342              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2343              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2344               EEPROM_ADDR_ADDR_MASK) |
2345              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2346
2347         for (i = 0; i < 10000; i++) {
2348                 tmp = tr32(GRC_EEPROM_ADDR);
2349
2350                 if (tmp & EEPROM_ADDR_COMPLETE)
2351                         break;
2352                 udelay(100);
2353         }
2354         if (!(tmp & EEPROM_ADDR_COMPLETE)) {
2355                 return -EBUSY;
2356         }
2357
2358         *val = tr32(GRC_EEPROM_DATA);
2359         return 0;
2360 }
2361
2362 static int tg3_nvram_read(struct tg3 *tp, uint32_t offset, uint32_t *val)
2363 {
2364         int i;
2365
2366         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2367                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2368
2369         if (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED)
2370                 offset = ((offset / NVRAM_BUFFERED_PAGE_SIZE) <<
2371                           NVRAM_BUFFERED_PAGE_POS) +
2372                         (offset % NVRAM_BUFFERED_PAGE_SIZE);
2373
2374         if (offset > NVRAM_ADDR_MSK)
2375                 return -EINVAL;
2376
2377         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2378         for (i = 0; i < 1000; i++) {
2379                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2380                         break;
2381                 udelay(20);
2382         }
2383
2384         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
2385                 u32 nvaccess = tr32(NVRAM_ACCESS);
2386
2387                 tw32_carefully(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2388         }
2389
2390         tw32(NVRAM_ADDR, offset);
2391         tw32(NVRAM_CMD,
2392              NVRAM_CMD_RD | NVRAM_CMD_GO |
2393              NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2394
2395         /* Wait for done bit to clear then set again. */
2396         for (i = 0; i < 1000; i++) {
2397                 udelay(10);
2398                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2399                         udelay(10);
2400                         *val = bswap_32(tr32(NVRAM_RDDATA));
2401                         break;
2402                 }
2403         }
2404
2405         tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2406
2407         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
2408                 u32 nvaccess = tr32(NVRAM_ACCESS);
2409
2410                 tw32_carefully(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2411         }
2412
2413         if (i >= 1000) {
2414                 return -EBUSY;
2415         }
2416
2417         return 0;
2418 }
2419
2420 struct subsys_tbl_ent {
2421         uint16_t subsys_vendor, subsys_devid;
2422         uint32_t phy_id;
2423 };
2424
2425 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
2426         /* Broadcom boards. */
2427         { 0x14e4, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
2428         { 0x14e4, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
2429         { 0x14e4, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
2430         { 0x14e4, 0x0003, PHY_ID_SERDES  }, /* BCM95700A9 */
2431         { 0x14e4, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
2432         { 0x14e4, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
2433         { 0x14e4, 0x0007, PHY_ID_SERDES  }, /* BCM95701A7 */
2434         { 0x14e4, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
2435         { 0x14e4, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
2436         { 0x14e4, 0x0009, PHY_ID_BCM5701 }, /* BCM95703Ax1 */
2437         { 0x14e4, 0x8009, PHY_ID_BCM5701 }, /* BCM95703Ax2 */
2438
2439         /* 3com boards. */
2440         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
2441         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
2442         /* { PCI_VENDOR_ID_3COM, 0x1002, PHY_ID_XXX },     3C996CT */
2443         /* { PCI_VENDOR_ID_3COM, 0x1003, PHY_ID_XXX },     3C997T */
2444         { PCI_VENDOR_ID_3COM, 0x1004, PHY_ID_SERDES  }, /* 3C996SX */
2445         /* { PCI_VENDOR_ID_3COM, 0x1005, PHY_ID_XXX },     3C997SZ */
2446         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
2447         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
2448
2449         /* DELL boards. */
2450         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
2451         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
2452         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
2453         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
2454         { PCI_VENDOR_ID_DELL, 0x0179, PHY_ID_BCM5751 }, /* EtherXpress */
2455         
2456         /* Fujitsu Siemens Computer */
2457         { PCI_VENDOR_ID_FSC, 0x105d, PHY_ID_BCM5751 }, /* Futro C200 */ 
2458
2459         /* Compaq boards. */
2460         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
2461         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
2462         { PCI_VENDOR_ID_COMPAQ, 0x007d, PHY_ID_SERDES  }, /* CHANGELING */
2463         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
2464         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }  /* NC7780_2 */
2465 };
2466
2467 static int tg3_phy_probe(struct tg3 *tp)
2468 {
2469         uint32_t eeprom_phy_id, hw_phy_id_1, hw_phy_id_2;
2470         uint32_t hw_phy_id, hw_phy_id_masked;
2471         uint32_t val;
2472         unsigned i;
2473         int eeprom_signature_found, err;
2474
2475         tp->phy_id = PHY_ID_INVALID;
2476
2477         for (i = 0; i < sizeof(subsys_id_to_phy_id)/sizeof(subsys_id_to_phy_id[0]); i++) {
2478                 if ((subsys_id_to_phy_id[i].subsys_vendor == tp->subsystem_vendor) &&
2479                         (subsys_id_to_phy_id[i].subsys_devid == tp->subsystem_device)) {
2480                         tp->phy_id = subsys_id_to_phy_id[i].phy_id;
2481                         break;
2482                 }
2483         }
2484
2485         eeprom_phy_id = PHY_ID_INVALID;
2486         eeprom_signature_found = 0;
2487         tg3_read_mem(NIC_SRAM_DATA_SIG, &val);
2488         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
2489                 uint32_t nic_cfg, led_cfg;
2490
2491                 tg3_read_mem(NIC_SRAM_DATA_CFG, &nic_cfg);
2492                 tp->nic_sram_data_cfg = nic_cfg;
2493
2494                 eeprom_signature_found = 1;
2495
2496                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
2497                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) {
2498                         eeprom_phy_id = PHY_ID_SERDES;
2499                 } else {
2500                         uint32_t nic_phy_id;
2501
2502                         tg3_read_mem(NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
2503                         if (nic_phy_id != 0) {
2504                                 uint32_t id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
2505                                 uint32_t id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
2506
2507                                 eeprom_phy_id  = (id1 >> 16) << 10;
2508                                 eeprom_phy_id |= (id2 & 0xfc00) << 16;
2509                                 eeprom_phy_id |= (id2 & 0x03ff) <<  0;
2510                         }
2511                 }
2512
2513                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
2514                         tg3_read_mem(NIC_SRAM_DATA_CFG_2, &led_cfg);
2515                         led_cfg &= (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
2516                                     SHASTA_EXT_LED_MODE_MASK);
2517                 } else
2518                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
2519
2520                 switch (led_cfg) {
2521                 default:
2522                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
2523                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
2524                         break;
2525
2526                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
2527                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
2528                         break;
2529
2530                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
2531                         tp->led_ctrl = LED_CTRL_MODE_MAC;
2532                         break;
2533
2534                 case SHASTA_EXT_LED_SHARED:
2535                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
2536                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
2537                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
2538                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
2539                                                  LED_CTRL_MODE_PHY_2);
2540                         break;
2541
2542                 case SHASTA_EXT_LED_MAC:
2543                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
2544                         break;
2545
2546                 case SHASTA_EXT_LED_COMBO:
2547                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
2548                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
2549                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
2550                                                  LED_CTRL_MODE_PHY_2);
2551                         break;
2552
2553                 };
2554
2555                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2556                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
2557                     tp->subsystem_vendor == PCI_VENDOR_ID_DELL)
2558                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
2559
2560 /*
2561                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
2562                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
2563                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) &&
2564                         (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP)) {
2565                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
2566                 }
2567 */
2568
2569                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
2570                         (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
2571                         (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP))
2572                                 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
2573
2574                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
2575                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
2576                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
2577                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
2578                 }
2579                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
2580                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
2581         }
2582
2583         /* Reading the PHY ID register can conflict with ASF
2584          * firwmare access to the PHY hardware.
2585          */
2586         err = 0;
2587         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
2588                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
2589         } else {
2590                 /* Now read the physical PHY_ID from the chip and verify
2591                  * that it is sane.  If it doesn't look good, we fall back
2592                  * to either the hard-coded table based PHY_ID and failing
2593                  * that the value found in the eeprom area.
2594                  */
2595                 err  = tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
2596                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
2597
2598                 if(err)
2599                         printf("ERROR: Error tg3_readphy\n");
2600
2601                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
2602                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
2603                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
2604
2605                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
2606         }
2607
2608         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
2609                 tp->phy_id = hw_phy_id;
2610         } else {
2611                 /* phy_id currently holds the value found in the
2612                  * subsys_id_to_phy_id[] table or PHY_ID_INVALID
2613                  * if a match was not found there.
2614                  */
2615                 if (tp->phy_id == PHY_ID_INVALID) {
2616                         if (!eeprom_signature_found ||
2617                             !KNOWN_PHY_ID(eeprom_phy_id & PHY_ID_MASK))
2618                                 return -ENODEV;
2619                         tp->phy_id = eeprom_phy_id;
2620                 }
2621         }
2622
2623         err = tg3_phy_reset(tp);
2624         if (err) {
2625                 printf("ERROR:  Error on return from tg3_phy_reset\n");
2626                 return err;
2627         }
2628
2629         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2630             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2631                 uint32_t mii_tg3_ctrl;
2632                 
2633                 /* These chips, when reset, only advertise 10Mb
2634                  * capabilities.  Fix that.
2635                  */
2636                 err  = tg3_writephy(tp, MII_ADVERTISE,
2637                                     (ADVERTISE_CSMA |
2638                                      ADVERTISE_PAUSE_CAP |
2639                                      ADVERTISE_10HALF |
2640                                      ADVERTISE_10FULL |
2641                                      ADVERTISE_100HALF |
2642                                      ADVERTISE_100FULL));
2643                 
2644                 if(err)
2645                         printf("ERROR: Error tg3_writephy\n");
2646
2647                 mii_tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
2648                                 MII_TG3_CTRL_ADV_1000_FULL |
2649                                 MII_TG3_CTRL_AS_MASTER |
2650                                 MII_TG3_CTRL_ENABLE_AS_MASTER);
2651                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2652                         mii_tg3_ctrl = 0;
2653
2654                 err |= tg3_writephy(tp, MII_TG3_CTRL, mii_tg3_ctrl);
2655                 err |= tg3_writephy(tp, MII_BMCR,
2656                                     (BMCR_ANRESTART | BMCR_ANENABLE));
2657                 if(err)
2658                         printf("ERROR: Error tg3_writephy\n");
2659         }
2660
2661         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
2662                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2663                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2664                 tg3_writedsp(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
2665         }
2666
2667         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2668                 tg3_writephy(tp, 0x1c, 0x8d68);
2669                 tg3_writephy(tp, 0x1c, 0x8d68);
2670         }
2671
2672         /* Enable Ethernet@WireSpeed */
2673         tg3_phy_set_wirespeed(tp);
2674
2675         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
2676                 err = tg3_init_5401phy_dsp(tp);
2677                 if(err)
2678                         printf("ERROR: Error return from tg3_init_5401phy_dsp\n");
2679         }
2680
2681         if (!eeprom_signature_found)
2682                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
2683
2684         if (tp->phy_id == PHY_ID_SERDES)
2685                 tp->link_config.advertising =
2686                         (ADVERTISED_1000baseT_Half |
2687                          ADVERTISED_1000baseT_Full |
2688                          ADVERTISED_Autoneg |
2689                          ADVERTISED_FIBRE);
2690         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2691                 tp->link_config.advertising &=
2692                         ~(ADVERTISED_1000baseT_Half |
2693                           ADVERTISED_1000baseT_Full);
2694
2695         return err;
2696 }
2697
2698 #if SUPPORT_PARTNO_STR
2699 static void tg3_read_partno(struct tg3 *tp)
2700 {
2701         unsigned char vpd_data[256];
2702         int i;
2703
2704         for (i = 0; i < 256; i += 4) {
2705                 uint32_t tmp;
2706
2707                 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
2708                         goto out_not_found;
2709
2710                 vpd_data[i + 0] = ((tmp >>  0) & 0xff);
2711                 vpd_data[i + 1] = ((tmp >>  8) & 0xff);
2712                 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
2713                 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
2714         }
2715
2716         /* Now parse and find the part number. */
2717         for (i = 0; i < 256; ) {
2718                 unsigned char val = vpd_data[i];
2719                 int block_end;
2720
2721                 if (val == 0x82 || val == 0x91) {
2722                         i = (i + 3 +
2723                              (vpd_data[i + 1] +
2724                               (vpd_data[i + 2] << 8)));
2725                         continue;
2726                 }
2727
2728                 if (val != 0x90)
2729                         goto out_not_found;
2730
2731                 block_end = (i + 3 +
2732                              (vpd_data[i + 1] +
2733                               (vpd_data[i + 2] << 8)));
2734                 i += 3;
2735                 while (i < block_end) {
2736                         if (vpd_data[i + 0] == 'P' &&
2737                             vpd_data[i + 1] == 'N') {
2738                                 int partno_len = vpd_data[i + 2];
2739
2740                                 if (partno_len > 24)
2741                                         goto out_not_found;
2742
2743                                 memcpy(tp->board_part_number,
2744                                        &vpd_data[i + 3],
2745                                        partno_len);
2746
2747                                 /* Success. */
2748                                 return;
2749                         }
2750                 }
2751
2752                 /* Part number not found. */
2753                 goto out_not_found;
2754         }
2755
2756 out_not_found:
2757         memcpy(tp->board_part_number, "none", sizeof("none"));
2758 }
2759 #else
2760 #define tg3_read_partno(TP) ((TP)->board_part_number[0] = '\0')
2761 #endif
2762
2763 static int tg3_get_invariants(struct tg3 *tp)
2764 {
2765         uint32_t misc_ctrl_reg;
2766         uint32_t pci_state_reg, grc_misc_cfg;
2767         uint16_t pci_cmd;
2768         uint8_t  pci_latency;
2769         uint32_t val ;
2770         int err;
2771
2772         /* Read the subsystem vendor and device ids */
2773         pci_read_config_word(tp->pdev, PCI_SUBSYSTEM_VENDOR_ID, &tp->subsystem_vendor);
2774         pci_read_config_word(tp->pdev, PCI_SUBSYSTEM_ID, &tp->subsystem_device);
2775
2776         /* The sun_5704 code needs infrastructure etherboot does have
2777          * ignore it for now.
2778          */
2779
2780         /* If we have an AMD 762 or Intel ICH/ICH0 chipset, write
2781          * reordering to the mailbox registers done by the host
2782          * controller can cause major troubles.  We read back from
2783          * every mailbox register write to force the writes to be
2784          * posted to the chip in order.
2785          *
2786          * TG3_FLAG_MBOX_WRITE_REORDER has been forced on.
2787          */
2788
2789         /* Force memory write invalidate off.  If we leave it on,
2790          * then on 5700_BX chips we have to enable a workaround.
2791          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundry
2792          * to match the cacheline size.  The Broadcom driver have this
2793          * workaround but turns MWI off all the times so never uses
2794          * it.  This seems to suggest that the workaround is insufficient.
2795          */
2796         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
2797         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
2798         /* Also, force SERR#/PERR# in PCI command. */
2799         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
2800         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
2801
2802         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
2803          * has the register indirect write enable bit set before
2804          * we try to access any of the MMIO registers.  It is also
2805          * critical that the PCI-X hw workaround situation is decided
2806          * before that as well.
2807          */
2808         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, &misc_ctrl_reg);
2809
2810         tp->pci_chip_rev_id = (misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT);
2811
2812         /* Initialize misc host control in PCI block. */
2813         tp->misc_host_ctrl |= (misc_ctrl_reg &
2814                                MISC_HOST_CTRL_CHIPREV);
2815         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
2816                                tp->misc_host_ctrl);
2817
2818         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, &pci_latency);
2819         if (pci_latency < 64) {
2820                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, 64);
2821         }
2822
2823         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &pci_state_reg);
2824
2825         /* If this is a 5700 BX chipset, and we are in PCI-X
2826          * mode, enable register write workaround.
2827          *
2828          * The workaround is to use indirect register accesses
2829          * for all chip writes not to mailbox registers.
2830          *
2831          * In etherboot to simplify things we just always use this work around.
2832          */
2833         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
2834                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
2835         }
2836         /* Back to back register writes can cause problems on the 5701,
2837          * the workaround is to read back all reg writes except those to
2838          * mailbox regs.
2839          * In etherboot we always use indirect register accesses so
2840          * we don't see this.
2841          */
2842
2843         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
2844                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
2845         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
2846                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
2847
2848         /* Chip-specific fixup from Broadcom driver */
2849         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
2850             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
2851                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
2852                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
2853         }
2854
2855         /* determine if it is PCIE system */
2856         // Alf : I have no idea what this is about...
2857         // But it's definitely usefull
2858         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
2859           val = tr32(TG3PCI_MSI_CAP_ID) ;
2860           if (((val >> 8) & 0xff) == T3_PCIE_CAPABILITY_ID_REG) {
2861             val = tr32(T3_PCIE_CAPABILITY_ID_REG) ;
2862             if ((val & 0xff) == T3_PCIE_CAPABILITY_ID) {
2863               tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS ;
2864             }
2865           }
2866         }
2867
2868         /* Force the chip into D0. */
2869         tg3_set_power_state_0(tp);
2870
2871         /* Etherboot does not ask the tg3 to do checksums */
2872         /* Etherboot does not ask the tg3 to do jumbo frames */
2873         /* Ehterboot does not ask the tg3 to use WakeOnLan. */
2874
2875         /* A few boards don't want Ethernet@WireSpeed phy feature */
2876         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
2877             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
2878                 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2879                         (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
2880                         (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1))) {
2881                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
2882         }
2883
2884         /* Avoid tagged irq status etherboot does not use irqs */
2885
2886         /* Only 5701 and later support tagged irq status mode.
2887          * Also, 5788 chips cannot use tagged irq status.
2888          *
2889          * However, since etherboot does not use irqs avoid tagged irqs
2890          * status  because the interrupt condition is more difficult to
2891          * fully clear in that mode.
2892          */
2893         
2894         /* Since some 5700_AX && 5700_BX have problems with 32BYTE
2895          * coalesce_mode, and the rest work fine anything set.
2896          * Don't enable HOST_CC_MODE_32BYTE in etherboot.
2897          */
2898
2899         /* Initialize MAC MI mode, polling disabled. */
2900         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
2901
2902         /* Initialize data/descriptor byte/word swapping. */
2903         tw32(GRC_MODE, tp->grc_mode);
2904
2905         tg3_switch_clocks(tp);
2906
2907         /* Clear this out for sanity. */
2908         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
2909
2910         /* Etherboot does not need to check if the PCIX_TARGET_HWBUG
2911          * is needed.  It always uses it.
2912          */
2913         
2914         udelay(50);
2915         tg3_nvram_init(tp);
2916
2917         /* The TX descriptors will reside in main memory.
2918          */
2919
2920         /* See which board we are using.
2921          */
2922         grc_misc_cfg = tr32(GRC_MISC_CFG);
2923         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
2924
2925         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
2926             grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
2927                 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
2928                 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
2929         }
2930
2931         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
2932             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
2933              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
2934                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
2935
2936 #define PCI_DEVICE_ID_TIGON3_5901       0x170d
2937 #define PCI_DEVICE_ID_TIGON3_5901_2     0x170e
2938
2939         /* these are limited to 10/100 only */
2940         if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) &&
2941                     ((grc_misc_cfg == 0x8000) || (grc_misc_cfg == 0x4000))) ||
2942                 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2943                         (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM) &&
2944                         ((tp->pdev->dev_id == PCI_DEVICE_ID_TIGON3_5901) ||
2945                                 (tp->pdev->dev_id == PCI_DEVICE_ID_TIGON3_5901_2)))) {
2946                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
2947         }
2948
2949         err = tg3_phy_probe(tp);
2950         if (err) {
2951                 printf("phy probe failed, err %d\n", err);
2952         }
2953
2954         tg3_read_partno(tp);
2955
2956
2957         /* 5700 BX chips need to have their TX producer index mailboxes
2958          * written twice to workaround a bug.
2959          * In etherboot we do this unconditionally to simplify things.
2960          */
2961
2962         /* 5700 chips can get confused if TX buffers straddle the
2963          * 4GB address boundary in some cases.
2964          * 
2965          * In etherboot we can ignore the problem as etherboot lives below 4GB.
2966          */
2967
2968         /* In etherboot wake-on-lan is unconditionally disabled */
2969         return err;
2970 }
2971
2972 static int  tg3_get_device_address(struct tg3 *tp)
2973 {
2974         struct nic *nic = tp->nic;
2975         uint32_t hi, lo, mac_offset;
2976
2977         if (PCI_FUNC(tp->pdev->devfn) == 0)
2978                 mac_offset = 0x7c;
2979         else
2980                 mac_offset = 0xcc;
2981
2982         /* First try to get it from MAC address mailbox. */
2983         tg3_read_mem(NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
2984         if ((hi >> 16) == 0x484b) {
2985                 nic->node_addr[0] = (hi >>  8) & 0xff;
2986                 nic->node_addr[1] = (hi >>  0) & 0xff;
2987
2988                 tg3_read_mem(NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
2989                 nic->node_addr[2] = (lo >> 24) & 0xff;
2990                 nic->node_addr[3] = (lo >> 16) & 0xff;
2991                 nic->node_addr[4] = (lo >>  8) & 0xff;
2992                 nic->node_addr[5] = (lo >>  0) & 0xff;
2993         }
2994         /* Next, try NVRAM. */
2995         else if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
2996                  !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
2997                 nic->node_addr[0] = ((hi >> 16) & 0xff);
2998                 nic->node_addr[1] = ((hi >> 24) & 0xff);
2999                 nic->node_addr[2] = ((lo >>  0) & 0xff);
3000                 nic->node_addr[3] = ((lo >>  8) & 0xff);
3001                 nic->node_addr[4] = ((lo >> 16) & 0xff);
3002                 nic->node_addr[5] = ((lo >> 24) & 0xff);
3003         }
3004         /* Finally just fetch it out of the MAC control regs. */
3005         else {
3006                 hi = tr32(MAC_ADDR_0_HIGH);
3007                 lo = tr32(MAC_ADDR_0_LOW);
3008
3009                 nic->node_addr[5] = lo & 0xff;
3010                 nic->node_addr[4] = (lo >> 8) & 0xff;
3011                 nic->node_addr[3] = (lo >> 16) & 0xff;
3012                 nic->node_addr[2] = (lo >> 24) & 0xff;
3013                 nic->node_addr[1] = hi & 0xff;
3014                 nic->node_addr[0] = (hi >> 8) & 0xff;
3015         }
3016
3017         return 0;
3018 }
3019
3020
3021 static int tg3_setup_dma(struct tg3 *tp)
3022 {
3023         tw32(TG3PCI_CLOCK_CTRL, 0);
3024
3025         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) == 0) {
3026                 tp->dma_rwctrl =
3027                         (0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
3028                         (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
3029                         (0x7 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
3030                         (0x7 << DMA_RWCTRL_READ_WATER_SHIFT) |
3031                         (0x0f << DMA_RWCTRL_MIN_DMA_SHIFT);
3032                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
3033                         tp->dma_rwctrl &= ~(DMA_RWCTRL_MIN_DMA << DMA_RWCTRL_MIN_DMA_SHIFT);
3034                 }
3035         } else {
3036                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
3037                         tp->dma_rwctrl =
3038                                 (0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
3039                                 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
3040                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
3041                                 (0x7 << DMA_RWCTRL_READ_WATER_SHIFT) |
3042                                 (0x00 << DMA_RWCTRL_MIN_DMA_SHIFT);
3043                 else
3044                         tp->dma_rwctrl =
3045                                 (0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
3046                                 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
3047                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
3048                                 (0x3 << DMA_RWCTRL_READ_WATER_SHIFT) |
3049                                 (0x0f << DMA_RWCTRL_MIN_DMA_SHIFT);
3050
3051                 /* Wheee, some more chip bugs... */
3052                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
3053                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)) {
3054                         uint32_t ccval = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
3055
3056                         if ((ccval == 0x6) || (ccval == 0x7)) {
3057                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
3058                         }
3059                 }
3060         }
3061
3062         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
3063                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)) {
3064                 tp->dma_rwctrl &= ~(DMA_RWCTRL_MIN_DMA << DMA_RWCTRL_MIN_DMA_SHIFT);
3065         }
3066
3067         /*
3068           Alf : Tried that, but it does not work. Should be this way though :-(
3069         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
3070           tp->dma_rwctrl |= 0x001f0000;
3071         }
3072         */
3073         tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
3074
3075         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
3076
3077         return 0;
3078 }
3079
3080 static void tg3_init_link_config(struct tg3 *tp)
3081 {
3082         tp->link_config.advertising =
3083                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
3084                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
3085                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
3086                  ADVERTISED_Autoneg | ADVERTISED_MII);
3087         tp->carrier_ok = 0;
3088         tp->link_config.active_speed = SPEED_INVALID;
3089         tp->link_config.active_duplex = DUPLEX_INVALID;
3090 }
3091
3092
3093 #if SUPPORT_PHY_STR
3094 static const char * tg3_phy_string(struct tg3 *tp)
3095 {
3096         switch (tp->phy_id & PHY_ID_MASK) {
3097         case PHY_ID_BCM5400:    return "5400";
3098         case PHY_ID_BCM5401:    return "5401";
3099         case PHY_ID_BCM5411:    return "5411";
3100         case PHY_ID_BCM5701:    return "5701";
3101         case PHY_ID_BCM5703:    return "5703";
3102         case PHY_ID_BCM5704:    return "5704";
3103         case PHY_ID_BCM5705:    return "5705";
3104         case PHY_ID_BCM5750:    return "5750";
3105         case PHY_ID_BCM5751:    return "5751"; 
3106         case PHY_ID_BCM8002:    return "8002/serdes";
3107         case PHY_ID_SERDES:     return "serdes";
3108         default:                return "unknown";
3109         };
3110 }
3111 #else
3112 #define tg3_phy_string(TP) "?"
3113 #endif
3114
3115
3116 static void tg3_poll_link(struct tg3 *tp)
3117 {
3118         uint32_t mac_stat;
3119
3120         mac_stat = tr32(MAC_STATUS);
3121         if (tp->phy_id == PHY_ID_SERDES) {
3122                 if (tp->carrier_ok?
3123                         (mac_stat & MAC_STATUS_LNKSTATE_CHANGED):
3124                         (mac_stat & MAC_STATUS_PCS_SYNCED)) {
3125                         tw32_carefully(MAC_MODE, tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK);
3126                         tw32_carefully(MAC_MODE, tp->mac_mode);
3127
3128                         tg3_setup_phy(tp);
3129                 }
3130         }
3131         else {
3132                 if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) {
3133                         tg3_setup_phy(tp);
3134                 }
3135         }
3136 }
3137
3138 /**************************************************************************
3139 POLL - Wait for a frame
3140 ***************************************************************************/
3141 static void tg3_ack_irqs(struct tg3 *tp)
3142 {
3143         if (tp->hw_status->status & SD_STATUS_UPDATED) {
3144                 /*
3145                  * writing any value to intr-mbox-0 clears PCI INTA# and
3146                  * chip-internal interrupt pending events.
3147                  * writing non-zero to intr-mbox-0 additional tells the
3148                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3149                  * event coalescing.
3150                  */
3151                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 
3152                         0x00000001);
3153                 /*
3154                  * Flush PCI write.  This also guarantees that our
3155                  * status block has been flushed to host memory.
3156                  */
3157                 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
3158                 tp->hw_status->status &= ~SD_STATUS_UPDATED;
3159         }
3160 }
3161
3162 static int tg3_poll(struct nic *nic, int retrieve)
3163 {
3164         /* return true if there's an ethernet packet ready to read */
3165         /* nic->packet should contain data on return */
3166         /* nic->packetlen should contain length of data */
3167
3168         struct tg3 *tp = &tg3;
3169         int result;
3170
3171         result = 0;
3172
3173         if ( (tp->hw_status->idx[0].rx_producer != tp->rx_rcb_ptr) && !retrieve ) 
3174           return 1;
3175
3176         tg3_ack_irqs(tp);
3177
3178         if (tp->hw_status->idx[0].rx_producer != tp->rx_rcb_ptr) {
3179                 struct tg3_rx_buffer_desc *desc;
3180                 unsigned int len;
3181                 desc = &tp->rx_rcb[tp->rx_rcb_ptr];
3182                 if ((desc->opaque & RXD_OPAQUE_RING_MASK) == RXD_OPAQUE_RING_STD) {
3183                         len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3184                         
3185                         nic->packetlen = len;
3186                         memcpy(nic->packet, bus_to_virt(desc->addr_lo), len);
3187                         result = 1;
3188                 }
3189                 tp->rx_rcb_ptr = (tp->rx_rcb_ptr + 1) % TG3_RX_RCB_RING_SIZE;
3190                 
3191                 /* ACK the status ring */
3192                 tw32_mailbox2(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, tp->rx_rcb_ptr);
3193
3194                 /* Refill RX ring. */
3195                 if (result) {
3196                         tp->rx_std_ptr = (tp->rx_std_ptr + 1) % TG3_RX_RING_SIZE;
3197                         tw32_mailbox2(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW, tp->rx_std_ptr);
3198                 }
3199         }
3200         tg3_poll_link(tp);
3201         return result;
3202 }
3203
3204 /**************************************************************************
3205 TRANSMIT - Transmit a frame
3206 ***************************************************************************/
3207 #if 0
3208 static void tg3_set_txd(struct tg3 *tp, int entry,
3209         dma_addr_t mapping, int len, uint32_t flags,
3210         uint32_t mss_and_is_end)
3211 {
3212         struct tg3_tx_buffer_desc *txd =  &tp->tx_ring[entry];
3213         int is_end = (mss_and_is_end & 0x1);
3214         if (is_end) {
3215                 flags |= TXD_FLAG_END;
3216         }
3217
3218         txd->addr_hi   = 0;
3219         txd->addr_lo   = mapping & 0xffffffff;
3220         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3221         txd->vlan_tag  = 0 << TXD_VLAN_TAG_SHIFT;
3222 }
3223 #endif
3224
3225 static void tg3_transmit(struct nic *nic, const char *dst_addr,
3226         unsigned int type, unsigned int size, const char *packet)
3227 {
3228         static struct eth_frame {
3229                 uint8_t  dst_addr[ETH_ALEN];
3230                 uint8_t  src_addr[ETH_ALEN];
3231                 uint16_t type;
3232                 uint8_t  data [ETH_FRAME_LEN - ETH_HLEN];
3233         } frame[2];
3234         static int frame_idx;
3235         
3236         /* send the packet to destination */
3237         struct tg3_tx_buffer_desc *txd;
3238         struct tg3 *tp;
3239         uint32_t entry;
3240         int i;
3241
3242         /* Wait until there is a free packet frame */
3243         tp = &tg3;
3244         i = 0;
3245         entry = tp->tx_prod;
3246         while((tp->hw_status->idx[0].tx_consumer != entry) &&
3247                 (tp->hw_status->idx[0].tx_consumer != PREV_TX(entry))) {
3248                 mdelay(10);     /* give the nick a chance */
3249                 poll_interruptions();
3250                 if (++i > 500) { /* timeout 5s for transmit */
3251                         printf("transmit timed out\n");
3252                         tg3_halt(tp);
3253                         tg3_setup_hw(tp);
3254                         return;
3255                 }
3256         }
3257         if (i != 0) {
3258                 printf("#");
3259         }
3260         
3261         /* Copy the packet to the our local buffer */
3262         memcpy(&frame[frame_idx].dst_addr, dst_addr, ETH_ALEN);
3263         memcpy(&frame[frame_idx].src_addr, nic->node_addr, ETH_ALEN);
3264         frame[frame_idx].type = htons(type);
3265         memset(&frame[frame_idx].data, 0, sizeof(frame[frame_idx].data));
3266         memcpy(&frame[frame_idx].data, packet, size);
3267
3268         /* Setup the ring buffer entry to transmit */
3269         txd            = &tp->tx_ring[entry];
3270         txd->addr_hi   = 0; /* Etherboot runs under 4GB */
3271         txd->addr_lo   = virt_to_bus(&frame[frame_idx]);
3272         txd->len_flags = ((size + ETH_HLEN) << TXD_LEN_SHIFT) | TXD_FLAG_END;
3273         txd->vlan_tag  = 0 << TXD_VLAN_TAG_SHIFT;
3274
3275         /* Advance to the next entry */
3276         entry = NEXT_TX(entry);
3277         frame_idx ^= 1;
3278
3279         /* Packets are ready, update Tx producer idx local and on card */
3280         tw32_mailbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3281         tw32_mailbox2((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3282         tp->tx_prod = entry;
3283 }
3284
3285 /**************************************************************************
3286 DISABLE - Turn off ethernet interface
3287 ***************************************************************************/
3288 static void tg3_disable(struct dev *dev __unused)
3289 {
3290         struct tg3 *tp = &tg3;
3291         /* put the card in its initial state */
3292         /* This function serves 3 purposes.
3293          * This disables DMA and interrupts so we don't receive
3294          *  unexpected packets or interrupts from the card after
3295          *  etherboot has finished. 
3296          * This frees resources so etherboot may use
3297          *  this driver on another interface
3298          * This allows etherboot to reinitialize the interface
3299          *  if something is something goes wrong.
3300          */
3301         tg3_halt(tp);
3302         tp->tg3_flags &= ~(TG3_FLAG_INIT_COMPLETE|TG3_FLAG_GOT_SERDES_FLOWCTL);
3303         tp->carrier_ok = 0;
3304         iounmap((void *)tp->regs);
3305 }
3306
3307 /**************************************************************************
3308 IRQ - Enable, Disable, or Force interrupts
3309 ***************************************************************************/
3310 static void tg3_irq(struct nic *nic __unused, irq_action_t action __unused)
3311 {
3312   switch ( action ) {
3313   case DISABLE :
3314     break;
3315   case ENABLE :
3316     break;
3317   case FORCE :
3318     break;
3319   }
3320 }
3321
3322 /**************************************************************************
3323 PROBE - Look for an adapter, this routine's visible to the outside
3324 You should omit the last argument struct pci_device * for a non-PCI NIC
3325 ***************************************************************************/
3326 static int tg3_probe(struct dev *dev, struct pci_device *pdev)
3327 {
3328         struct nic *nic = (struct nic *)dev;
3329         struct tg3 *tp = &tg3;
3330         unsigned long tg3reg_base, tg3reg_len;
3331         int i, err, pm_cap;
3332
3333         if (pdev == 0)
3334                 return 0;
3335
3336         memset(tp, 0, sizeof(*tp));
3337
3338         adjust_pci_device(pdev);
3339
3340         nic->irqno  = 0;
3341         nic->ioaddr = pdev->ioaddr & ~3;
3342
3343         /* Find power-management capability. */
3344         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3345         if (pm_cap == 0) {
3346                 printf("Cannot find PowerManagement capability, aborting.\n");
3347                 return 0;
3348         }
3349         tg3reg_base = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
3350         if (tg3reg_base == -1UL) {
3351                 printf("Unuseable bar\n");
3352                 return 0;
3353         }
3354         tg3reg_len  = pci_bar_size(pdev,  PCI_BASE_ADDRESS_0);
3355
3356         tp->pdev       = pdev;
3357         tp->nic        = nic;
3358         tp->pm_cap     = pm_cap;
3359         tp->rx_mode    = 0;
3360         tp->tx_mode    = 0;
3361         tp->mi_mode    = MAC_MI_MODE_BASE;
3362         tp->tg3_flags  = 0 & ~TG3_FLAG_INIT_COMPLETE; 
3363         
3364         /* The word/byte swap controls here control register access byte
3365          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
3366          * setting below.
3367          */
3368         tp->misc_host_ctrl =
3369                 MISC_HOST_CTRL_MASK_PCI_INT |
3370                 MISC_HOST_CTRL_WORD_SWAP |
3371                 MISC_HOST_CTRL_INDIR_ACCESS |
3372                 MISC_HOST_CTRL_PCISTATE_RW;
3373
3374         /* The NONFRM (non-frame) byte/word swap controls take effect
3375          * on descriptor entries, anything which isn't packet data.
3376          *
3377          * The StrongARM chips on the board (one for tx, one for rx)
3378          * are running in big-endian mode.
3379          */
3380         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
3381                         GRC_MODE_WSWAP_NONFRM_DATA);
3382 #if __BYTE_ORDER == __BIG_ENDIAN
3383         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
3384 #endif
3385         tp->regs = (unsigned long) ioremap(tg3reg_base, tg3reg_len);
3386         if (tp->regs == 0UL) {
3387                 printf("Cannot map device registers, aborting\n");
3388                 return 0;
3389         }
3390
3391         tg3_init_link_config(tp);
3392
3393         err = tg3_get_invariants(tp);
3394         if (err) {
3395                 printf("Problem fetching invariants of chip, aborting.\n");
3396                 goto err_out_iounmap;
3397         }
3398
3399         err = tg3_get_device_address(tp);
3400         if (err) {
3401                 printf("Could not obtain valid ethernet address, aborting.\n");
3402                 goto err_out_iounmap;
3403         }
3404         printf("Ethernet addr: %!\n", nic->node_addr);
3405
3406         tg3_setup_dma(tp);
3407
3408         /* Now that we have fully setup the chip, save away a snapshot
3409          * of the PCI config space.  We need to restore this after
3410          * GRC_MISC_CFG core clock resets and some resume events.
3411          */
3412         pci_save_state(tp->pdev, tp->pci_cfg_state);
3413
3414         printf("Tigon3 [partno(%s) rev %hx PHY(%s)] (PCI%s:%s:%s)\n",
3415                 tp->board_part_number,
3416                 tp->pci_chip_rev_id,
3417                 tg3_phy_string(tp),
3418                 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "X" : ""),
3419                 ((tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) ?
3420                         ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "133MHz" : "66MHz") :
3421                         ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "100MHz" : "33MHz")),
3422                 ((tp->tg3_flags & TG3_FLAG_PCI_32BIT) ? "32-bit" : "64-bit"));
3423
3424
3425         err = tg3_setup_hw(tp); 
3426         if (err) {
3427                 goto err_out_disable;
3428         } 
3429         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
3430
3431         /* Wait for a reasonable time for the link to come up */
3432         tg3_poll_link(tp);
3433         for(i = 0; !tp->carrier_ok && (i < VALID_LINK_TIMEOUT*100); i++) {
3434                 mdelay(1);
3435                 tg3_poll_link(tp);
3436         }
3437         if (!tp->carrier_ok){
3438                 printf("Valid link not established\n");
3439                 goto err_out_disable;
3440         }
3441
3442         dev->disable  = tg3_disable;
3443         nic->poll     = tg3_poll;
3444         nic->transmit = tg3_transmit;
3445         nic->irq      = tg3_irq;
3446
3447         return 1;
3448
3449  err_out_iounmap:
3450         iounmap((void *)tp->regs);
3451         return 0;
3452  err_out_disable:
3453         tg3_disable(dev);
3454         return 0;
3455 }
3456
3457 static struct pci_id tg3_nics[] = {
3458 PCI_ROM(0x14e4, 0x1644, "tg3-5700",        "Broadcom Tigon 3 5700"),
3459 PCI_ROM(0x14e4, 0x1645, "tg3-5701",        "Broadcom Tigon 3 5701"),
3460 PCI_ROM(0x14e4, 0x1646, "tg3-5702",        "Broadcom Tigon 3 5702"),
3461 PCI_ROM(0x14e4, 0x1647, "tg3-5703",        "Broadcom Tigon 3 5703"),
3462 PCI_ROM(0x14e4, 0x1648, "tg3-5704",        "Broadcom Tigon 3 5704"),
3463 PCI_ROM(0x14e4, 0x164d, "tg3-5702FE",      "Broadcom Tigon 3 5702FE"),
3464 PCI_ROM(0x14e4, 0x1653, "tg3-5705",        "Broadcom Tigon 3 5705"),
3465 PCI_ROM(0x14e4, 0x1654, "tg3-5705_2",      "Broadcom Tigon 3 5705_2"),
3466 PCI_ROM(0x14e4, 0x1659, "tg3-5721",        "Broadcom Tigon 3 5721"),
3467 PCI_ROM(0x14e4, 0x165d, "tg3-5705M",       "Broadcom Tigon 3 5705M"),
3468 PCI_ROM(0x14e4, 0x165e, "tg3-5705M_2",     "Broadcom Tigon 3 5705M_2"),
3469 PCI_ROM(0x14e4, 0x1677, "tg3-5751",        "Broadcom Tigon 3 5751"),
3470 PCI_ROM(0x14e4, 0x1696, "tg3-5782",        "Broadcom Tigon 3 5782"),
3471 PCI_ROM(0x14e4, 0x169c, "tg3-5788",        "Broadcom Tigon 3 5788"),
3472 PCI_ROM(0x14e4, 0x16a6, "tg3-5702X",       "Broadcom Tigon 3 5702X"),
3473 PCI_ROM(0x14e4, 0x16a7, "tg3-5703X",       "Broadcom Tigon 3 5703X"),
3474 PCI_ROM(0x14e4, 0x16a8, "tg3-5704S",       "Broadcom Tigon 3 5704S"),
3475 PCI_ROM(0x14e4, 0x16c6, "tg3-5702A3",      "Broadcom Tigon 3 5702A3"),
3476 PCI_ROM(0x14e4, 0x16c7, "tg3-5703A3",      "Broadcom Tigon 3 5703A3"),
3477 PCI_ROM(0x14e4, 0x170d, "tg3-5901",        "Broadcom Tigon 3 5901"),
3478 PCI_ROM(0x14e4, 0x170e, "tg3-5901_2",      "Broadcom Tigon 3 5901_2"),
3479 PCI_ROM(0x1148, 0x4400, "tg3-9DXX",        "Syskonnect 9DXX"),
3480 PCI_ROM(0x1148, 0x4500, "tg3-9MXX",        "Syskonnect 9MXX"),
3481 PCI_ROM(0x173b, 0x03e8, "tg3-ac1000",      "Altima AC1000"),
3482 PCI_ROM(0x173b, 0x03e9, "tg3-ac1001",      "Altima AC1001"),
3483 PCI_ROM(0x173b, 0x03ea, "tg3-ac9100",      "Altima AC9100"),
3484 PCI_ROM(0x173b, 0x03eb, "tg3-ac1003",      "Altima AC1003"),
3485 };
3486
3487 static struct pci_driver tg3_driver __pci_driver = {
3488         .type     = NIC_DRIVER,
3489         .name     = "TG3",
3490         .probe    = tg3_probe,
3491         .ids      = tg3_nics,
3492         .id_count = sizeof(tg3_nics)/sizeof(tg3_nics[0]),
3493         .class    = 0,
3494 };