Initial revision
[etherboot.git] / src / drivers / net / tg3.c
1 /* $Id$
2  * tg3.c: Broadcom Tigon3 ethernet driver.
3  *
4  * Copyright (C) 2001, 2002 David S. Miller (davem@redhat.com)
5  * Copyright (C) 2001, 2002 Jeff Garzik (jgarzik@mandrakesoft.com)
6  * Copyright (C) 2003 Eric Biederman (ebiederman@lnxi.com)  [etherboot port]
7  */
8
9 /* 11-13-2003   timlegge        Fix Issue with NetGear GA302T 
10  * 11-18-2003   ebiederm        Generalize NetGear Fix to what the code was supposed to be.
11  * 01-06-2005   Alf (Frederic Olivie) Add Dell bcm 5751 (0x1677) support
12  */
13
14 #include "etherboot.h"
15 #include "nic.h"
16 #include "pci.h"
17 #include "timer.h"
18 #include "string.h"
19 #include "tg3.h"
20
21 #define SUPPORT_COPPER_PHY  1
22 #define SUPPORT_FIBER_PHY   1
23 #define SUPPORT_LINK_REPORT 1
24 #define SUPPORT_PARTNO_STR  1
25 #define SUPPORT_PHY_STR     1
26
27 struct tg3 tg3;
28
29 /* Dummy defines for error handling */
30 #define EBUSY  1
31 #define ENODEV 2
32 #define EINVAL 3
33 #define ENOMEM 4
34
35
36 /* These numbers seem to be hard coded in the NIC firmware somehow.
37  * You can't change the ring sizes, but you can change where you place
38  * them in the NIC onboard memory.
39  */
40 #define TG3_RX_RING_SIZE                512
41 #define TG3_DEF_RX_RING_PENDING         20      /* RX_RING_PENDING seems to be o.k. at 20 and 200 */
42 #define TG3_RX_RCB_RING_SIZE    1024
43
44 /*      (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ? \
45          512 : 1024) */
46 #define TG3_TX_RING_SIZE                512
47 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
48
49 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_RING_SIZE)
50 #define TG3_RX_RCB_RING_BYTES   (sizeof(struct tg3_rx_buffer_desc) * TG3_RX_RCB_RING_SIZE)
51
52 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * TG3_TX_RING_SIZE)
53 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
54 #define PREV_TX(N)              (((N) - 1) & (TG3_TX_RING_SIZE - 1))
55
56 #define RX_PKT_BUF_SZ           (1536 + 2 + 64)
57
58
59 static struct bss {
60         struct tg3_rx_buffer_desc rx_std[TG3_RX_RING_SIZE];
61         struct tg3_rx_buffer_desc rx_rcb[TG3_RX_RCB_RING_SIZE];
62         struct tg3_tx_buffer_desc tx_ring[TG3_TX_RING_SIZE];
63         struct tg3_hw_status      hw_status;
64         struct tg3_hw_stats       hw_stats;
65         unsigned char             rx_bufs[TG3_DEF_RX_RING_PENDING][RX_PKT_BUF_SZ];
66 } tg3_bss;
67
68 /**
69  * pci_save_state - save the PCI configuration space of a device before suspending
70  * @dev: - PCI device that we're dealing with
71  * @buffer: - buffer to hold config space context
72  *
73  * @buffer must be large enough to hold the entire PCI 2.2 config space 
74  * (>= 64 bytes).
75  */
76 static int pci_save_state(struct pci_device *dev, uint32_t *buffer)
77 {
78         int i;
79         for (i = 0; i < 16; i++)
80                 pci_read_config_dword(dev, i * 4,&buffer[i]);
81         return 0;
82 }
83
84 /** 
85  * pci_restore_state - Restore the saved state of a PCI device
86  * @dev: - PCI device that we're dealing with
87  * @buffer: - saved PCI config space
88  *
89  */
90 static int pci_restore_state(struct pci_device *dev, uint32_t *buffer)
91 {
92         int i;
93
94         for (i = 0; i < 16; i++)
95                 pci_write_config_dword(dev,i * 4, buffer[i]);
96         return 0;
97 }
98
99 static void tg3_write_indirect_reg32(uint32_t off, uint32_t val)
100 {
101         pci_write_config_dword(tg3.pdev, TG3PCI_REG_BASE_ADDR, off);
102         pci_write_config_dword(tg3.pdev, TG3PCI_REG_DATA, val);
103 }
104
105 #define tw32(reg,val)           tg3_write_indirect_reg32((reg),(val))
106 #define tw32_mailbox(reg, val)  writel(((val) & 0xffffffff), tg3.regs + (reg))
107 #define tw16(reg,val)           writew(((val) & 0xffff), tg3.regs + (reg))
108 #define tw8(reg,val)            writeb(((val) & 0xff), tg3.regs + (reg))
109 #define tr32(reg)               readl(tg3.regs + (reg))
110 #define tr16(reg)               readw(tg3.regs + (reg))
111 #define tr8(reg)                readb(tg3.regs + (reg))
112
113 static void tw32_carefully(uint32_t reg, uint32_t val)
114 {
115         tw32(reg, val);
116         tr32(reg);
117         udelay(100);
118 }
119
120 static void tw32_mailbox2(uint32_t reg, uint32_t val)
121 {
122         tw32_mailbox(reg, val);
123         tr32(reg);
124 }
125
126 static void tg3_write_mem(uint32_t off, uint32_t val)
127 {
128         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
129         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_DATA, val);
130
131         /* Always leave this as zero. */
132         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
133 }
134
135 static void tg3_read_mem(uint32_t off, uint32_t *val)
136 {
137         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
138         pci_read_config_dword(tg3.pdev, TG3PCI_MEM_WIN_DATA, val);
139
140         /* Always leave this as zero. */
141         pci_write_config_dword(tg3.pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
142 }
143
144 static void tg3_disable_ints(struct tg3 *tp)
145 {
146         tw32(TG3PCI_MISC_HOST_CTRL,
147              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
148         tw32_mailbox2(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
149 }
150
151 static void tg3_switch_clocks(struct tg3 *tp)
152 {
153         uint32_t orig_clock_ctrl, clock_ctrl;
154
155         clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
156
157         orig_clock_ctrl = clock_ctrl;
158         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN | CLOCK_CTRL_CLKRUN_OENABLE | 0x1f);
159         tp->pci_clock_ctrl = clock_ctrl;
160         
161         if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) &&
162             (!((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
163                && (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) &&
164                 (orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE)!=0) {
165                 tw32_carefully(TG3PCI_CLOCK_CTRL, 
166                         clock_ctrl | (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK));
167                 tw32_carefully(TG3PCI_CLOCK_CTRL, 
168                         clock_ctrl | (CLOCK_CTRL_ALTCLK));
169         }
170         tw32_carefully(TG3PCI_CLOCK_CTRL, clock_ctrl);
171 }
172
173 #define PHY_BUSY_LOOPS  5000
174
175 static int tg3_readphy(struct tg3 *tp, int reg, uint32_t *val)
176 {
177         uint32_t frame_val;
178         int loops, ret;
179
180         tw32_carefully(MAC_MI_MODE, tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL);
181
182         *val = 0xffffffff;
183
184         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
185                       MI_COM_PHY_ADDR_MASK);
186         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
187                       MI_COM_REG_ADDR_MASK);
188         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
189         
190         tw32_carefully(MAC_MI_COM, frame_val);
191
192         loops = PHY_BUSY_LOOPS;
193         while (loops-- > 0) {
194                 udelay(10);
195                 frame_val = tr32(MAC_MI_COM);
196
197                 if ((frame_val & MI_COM_BUSY) == 0) {
198                         udelay(5);
199                         frame_val = tr32(MAC_MI_COM);
200                         break;
201                 }
202         }
203
204         ret = -EBUSY;
205         if (loops > 0) {
206                 *val = frame_val & MI_COM_DATA_MASK;
207                 ret = 0;
208         }
209
210         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
211
212         return ret;
213 }
214
215 static int tg3_writephy(struct tg3 *tp, int reg, uint32_t val)
216 {
217         uint32_t frame_val;
218         int loops, ret;
219
220         tw32_carefully(MAC_MI_MODE, tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL);
221
222         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
223                       MI_COM_PHY_ADDR_MASK);
224         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
225                       MI_COM_REG_ADDR_MASK);
226         frame_val |= (val & MI_COM_DATA_MASK);
227         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
228         
229         tw32_carefully(MAC_MI_COM, frame_val);
230
231         loops = PHY_BUSY_LOOPS;
232         while (loops-- > 0) {
233                 udelay(10);
234                 frame_val = tr32(MAC_MI_COM);
235                 if ((frame_val & MI_COM_BUSY) == 0) {
236                         udelay(5);
237                         frame_val = tr32(MAC_MI_COM);
238                         break;
239                 }
240         }
241
242         ret = -EBUSY;
243         if (loops > 0)
244                 ret = 0;
245
246         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
247
248         return ret;
249 }
250
251 static int tg3_writedsp(struct tg3 *tp, uint16_t addr, uint16_t val)
252 {
253         int err;
254         err  = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, addr);
255         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
256         return err;
257 }
258
259
260 static void tg3_phy_set_wirespeed(struct tg3 *tp)
261 {
262         uint32_t val;
263
264         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
265                 return;
266
267         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007);
268         tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
269         tg3_writephy(tp, MII_TG3_AUX_CTRL, (val | (1 << 15) | (1 << 4)));
270 }
271
272 static int tg3_bmcr_reset(struct tg3 *tp)
273 {
274         uint32_t phy_control;
275         int limit, err;
276
277         /* OK, reset it, and poll the BMCR_RESET bit until it
278          * clears or we time out.
279          */
280         phy_control = BMCR_RESET;
281         err = tg3_writephy(tp, MII_BMCR, phy_control);
282         if (err != 0)
283                 return -EBUSY;
284
285         limit = 5000;
286         while (limit--) {
287                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
288                 if (err != 0)
289                         return -EBUSY;
290
291                 if ((phy_control & BMCR_RESET) == 0) {
292                         udelay(40);
293                         break;
294                 }
295                 udelay(10);
296         }
297         if (limit <= 0)
298                 return -EBUSY;
299
300         return 0;
301 }
302
303 static int tg3_wait_macro_done(struct tg3 *tp)
304 {
305         int limit = 100;
306
307         while (limit--) {
308                 uint32_t tmp32;
309
310                 tg3_readphy(tp, 0x16, &tmp32);
311                 if ((tmp32 & 0x1000) == 0)
312                         break;
313         }
314         if (limit <= 0)
315                 return -EBUSY;
316
317         return 0;
318 }
319
320 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
321 {
322         static const uint32_t test_pat[4][6] = {
323         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
324         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
325         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
326         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
327         };
328         int chan;
329
330         for (chan = 0; chan < 4; chan++) {
331                 int i;
332
333                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
334                         (chan * 0x2000) | 0x0200);
335                 tg3_writephy(tp, 0x16, 0x0002);
336
337                 for (i = 0; i < 6; i++)
338                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
339                                 test_pat[chan][i]);
340
341                 tg3_writephy(tp, 0x16, 0x0202);
342                 if (tg3_wait_macro_done(tp)) {
343                         *resetp = 1;
344                         return -EBUSY;
345                 }
346
347                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
348                              (chan * 0x2000) | 0x0200);
349                 tg3_writephy(tp, 0x16, 0x0082);
350                 if (tg3_wait_macro_done(tp)) {
351                         *resetp = 1;
352                         return -EBUSY;
353                 }
354
355                 tg3_writephy(tp, 0x16, 0x0802);
356                 if (tg3_wait_macro_done(tp)) {
357                         *resetp = 1;
358                         return -EBUSY;
359                 }
360
361                 for (i = 0; i < 6; i += 2) {
362                         uint32_t low, high;
363
364                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low);
365                         tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high);
366                         if (tg3_wait_macro_done(tp)) {
367                                 *resetp = 1;
368                                 return -EBUSY;
369                         }
370                         low &= 0x7fff;
371                         high &= 0x000f;
372                         if (low != test_pat[chan][i] ||
373                             high != test_pat[chan][i+1]) {
374                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
375                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
376                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
377
378                                 return -EBUSY;
379                         }
380                 }
381         }
382
383         return 0;
384 }
385
386 static int tg3_phy_reset_chanpat(struct tg3 *tp)
387 {
388         int chan;
389
390         for (chan = 0; chan < 4; chan++) {
391                 int i;
392
393                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
394                              (chan * 0x2000) | 0x0200);
395                 tg3_writephy(tp, 0x16, 0x0002);
396                 for (i = 0; i < 6; i++)
397                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
398                 tg3_writephy(tp, 0x16, 0x0202);
399                 if (tg3_wait_macro_done(tp))
400                         return -EBUSY;
401         }
402
403         return 0;
404 }
405
406 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
407 {
408         uint32_t reg32, phy9_orig;
409         int retries, do_phy_reset, err;
410
411         retries = 10;
412         do_phy_reset = 1;
413         do {
414                 if (do_phy_reset) {
415                         err = tg3_bmcr_reset(tp);
416                         if (err)
417                                 return err;
418                         do_phy_reset = 0;
419                 }
420                 
421                 /* Disable transmitter and interrupt.  */
422                 tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);
423                 reg32 |= 0x3000;
424                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
425
426                 /* Set full-duplex, 1000 mbps.  */
427                 tg3_writephy(tp, MII_BMCR,
428                         BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
429
430                 /* Set to master mode.  */
431                 tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig);
432                 tg3_writephy(tp, MII_TG3_CTRL,
433                         (MII_TG3_CTRL_AS_MASTER |
434                                 MII_TG3_CTRL_ENABLE_AS_MASTER));
435
436                 /* Enable SM_DSP_CLOCK and 6dB.  */
437                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
438
439                 /* Block the PHY control access.  */
440                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
441                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
442
443                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
444                 if (!err)
445                         break;
446         } while (--retries);
447
448         err = tg3_phy_reset_chanpat(tp);
449         if (err)
450                 return err;
451
452         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
453         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
454
455         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
456         tg3_writephy(tp, 0x16, 0x0000);
457
458         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
459
460         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
461
462         tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32);
463         reg32 &= ~0x3000;
464         tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
465
466         return err;
467 }
468
469 /* This will reset the tigon3 PHY if there is no valid
470  * link.
471  */
472 static int tg3_phy_reset(struct tg3 *tp)
473 {
474         uint32_t phy_status;
475         int err;
476
477         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
478         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
479         if (err != 0)
480                 return -EBUSY;
481
482         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
483                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
484                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
485                 err = tg3_phy_reset_5703_4_5(tp);
486                 if (err)
487                         return err;
488                 goto out;
489         }
490         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
491           // Taken from Broadcom's source code
492           tg3_writephy(tp, 0x18, 0x0c00);
493           tg3_writephy(tp, 0x17, 0x000a);
494           tg3_writephy(tp, 0x15, 0x310b);
495           tg3_writephy(tp, 0x17, 0x201f);
496           tg3_writephy(tp, 0x15, 0x9506);
497           tg3_writephy(tp, 0x17, 0x401f);
498           tg3_writephy(tp, 0x15, 0x14e2);
499           tg3_writephy(tp, 0x18, 0x0400);
500         }
501         err = tg3_bmcr_reset(tp);
502         if (err)
503                 return err;
504  out:
505         tg3_phy_set_wirespeed(tp);
506         return 0;
507 }
508
509 static void tg3_set_power_state_0(struct tg3 *tp)
510 {
511         uint16_t power_control;
512         int pm = tp->pm_cap;
513
514         /* Make sure register accesses (indirect or otherwise)
515          * will function correctly.
516          */
517         pci_write_config_dword(tp->pdev,  TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
518
519         pci_read_config_word(tp->pdev, pm + PCI_PM_CTRL, &power_control);
520
521         power_control |= PCI_PM_CTRL_PME_STATUS;
522         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
523         power_control |= 0;
524         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
525
526         tw32_carefully(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
527
528         return;
529 }
530
531
532 #if SUPPORT_LINK_REPORT
533 static void tg3_link_report(struct tg3 *tp)
534 {
535         if (!tp->carrier_ok) {
536                 printf("Link is down.\n");
537         } else {
538                 printf("Link is up at %d Mbps, %s duplex. %s %s %s\n",
539                         (tp->link_config.active_speed == SPEED_1000 ?
540                                1000 :
541                         (tp->link_config.active_speed == SPEED_100 ?
542                                 100 : 10)),
543                         (tp->link_config.active_duplex == DUPLEX_FULL ?  
544                                 "full" : "half"),
545                         (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "TX" : "",
546                         (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "RX" : "",
547                         (tp->tg3_flags & (TG3_FLAG_TX_PAUSE |TG3_FLAG_RX_PAUSE)) ? "flow control" : "");
548         }
549 }
550 #else
551 #define tg3_link_report(tp)
552 #endif
553
554 static void tg3_setup_flow_control(struct tg3 *tp, uint32_t local_adv, uint32_t remote_adv)
555 {
556         uint32_t new_tg3_flags = 0;
557
558         if (local_adv & ADVERTISE_PAUSE_CAP) {
559                 if (local_adv & ADVERTISE_PAUSE_ASYM) {
560                         if (remote_adv & LPA_PAUSE_CAP)
561                                 new_tg3_flags |=
562                                         (TG3_FLAG_RX_PAUSE |
563                                          TG3_FLAG_TX_PAUSE);
564                         else if (remote_adv & LPA_PAUSE_ASYM)
565                                 new_tg3_flags |=
566                                         (TG3_FLAG_RX_PAUSE);
567                 } else {
568                         if (remote_adv & LPA_PAUSE_CAP)
569                                 new_tg3_flags |=
570                                         (TG3_FLAG_RX_PAUSE |
571                                          TG3_FLAG_TX_PAUSE);
572                 }
573         } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
574                 if ((remote_adv & LPA_PAUSE_CAP) &&
575                     (remote_adv & LPA_PAUSE_ASYM))
576                         new_tg3_flags |= TG3_FLAG_TX_PAUSE;
577         }
578
579         tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
580         tp->tg3_flags |= new_tg3_flags;
581
582         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
583                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
584         else
585                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
586
587         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
588                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
589         else
590                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
591 }
592
593 #if SUPPORT_COPPER_PHY
594 static void tg3_aux_stat_to_speed_duplex(
595         struct tg3 *tp __unused, uint32_t val, uint8_t *speed, uint8_t *duplex)
596 {
597         static const uint8_t map[] = {
598                 [0] = (SPEED_INVALID << 2) | DUPLEX_INVALID,
599                 [MII_TG3_AUX_STAT_10HALF >> 8]   = (SPEED_10 << 2) | DUPLEX_HALF,
600                 [MII_TG3_AUX_STAT_10FULL >> 8]   = (SPEED_10 << 2) | DUPLEX_FULL,
601                 [MII_TG3_AUX_STAT_100HALF >> 8]  = (SPEED_100 << 2) | DUPLEX_HALF,
602                 [MII_TG3_AUX_STAT_100_4 >> 8] = (SPEED_INVALID << 2) | DUPLEX_INVALID,
603                 [MII_TG3_AUX_STAT_100FULL >> 8]  = (SPEED_100 << 2) | DUPLEX_FULL,
604                 [MII_TG3_AUX_STAT_1000HALF >> 8] = (SPEED_1000 << 2) | DUPLEX_HALF,
605                 [MII_TG3_AUX_STAT_1000FULL >> 8] = (SPEED_1000 << 2) | DUPLEX_FULL,
606         };
607         uint8_t result;
608         result = map[(val & MII_TG3_AUX_STAT_SPDMASK) >> 8];
609         *speed = result >> 2;
610         *duplex = result & 3;
611 }
612
613 static int tg3_phy_copper_begin(struct tg3 *tp)
614 {
615         uint32_t new_adv;
616
617         tp->link_config.advertising =
618                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
619                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
620                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
621                         ADVERTISED_Autoneg | ADVERTISED_MII);
622         
623         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY) {
624                 tp->link_config.advertising &=
625                         ~(ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
626         }
627         
628         new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
629         if (tp->link_config.advertising & ADVERTISED_10baseT_Half) {
630                 new_adv |= ADVERTISE_10HALF;
631         }
632         if (tp->link_config.advertising & ADVERTISED_10baseT_Full) {
633                 new_adv |= ADVERTISE_10FULL;
634         }
635         if (tp->link_config.advertising & ADVERTISED_100baseT_Half) {
636                 new_adv |= ADVERTISE_100HALF;
637         }
638         if (tp->link_config.advertising & ADVERTISED_100baseT_Full) {
639                 new_adv |= ADVERTISE_100FULL;
640         }
641         tg3_writephy(tp, MII_ADVERTISE, new_adv);
642         
643         if (tp->link_config.advertising &
644                 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
645                 new_adv = 0;
646                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half) {
647                         new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
648                 }
649                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full) {
650                         new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
651                 }
652                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
653                         (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
654                                 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)) {
655                         new_adv |= (MII_TG3_CTRL_AS_MASTER |
656                                 MII_TG3_CTRL_ENABLE_AS_MASTER);
657                 }
658                 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
659         } else {
660                 tg3_writephy(tp, MII_TG3_CTRL, 0);
661         }
662
663         tg3_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
664
665         return 0;
666 }
667
668 static int tg3_init_5401phy_dsp(struct tg3 *tp)
669 {
670         int err;
671
672         /* Turn off tap power management. */
673         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c20);
674         
675         err |= tg3_writedsp(tp, 0x0012, 0x1804);
676         err |= tg3_writedsp(tp, 0x0013, 0x1204);
677         err |= tg3_writedsp(tp, 0x8006, 0x0132);
678         err |= tg3_writedsp(tp, 0x8006, 0x0232);
679         err |= tg3_writedsp(tp, 0x201f, 0x0a20);
680
681         udelay(40);
682
683         return err;
684 }
685
686 static int tg3_setup_copper_phy(struct tg3 *tp)
687 {
688         int current_link_up;
689         uint32_t bmsr, dummy;
690         int i, err;
691
692         tw32_carefully(MAC_STATUS,
693                 (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED
694                  | MAC_STATUS_LNKSTATE_CHANGED));
695
696         tp->mi_mode = MAC_MI_MODE_BASE;
697         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
698
699         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
700
701         /* Some third-party PHYs need to be reset on link going
702          * down.
703          */
704         if (    (       (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
705                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
706                         (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)) &&
707                 (tp->carrier_ok)) {
708                 tg3_readphy(tp, MII_BMSR, &bmsr);
709                 tg3_readphy(tp, MII_BMSR, &bmsr);
710                 if (!(bmsr & BMSR_LSTATUS))
711                         tg3_phy_reset(tp);
712         }
713
714         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
715                 tg3_readphy(tp, MII_BMSR, &bmsr);
716                 tg3_readphy(tp, MII_BMSR, &bmsr);
717
718                 if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
719                         bmsr = 0;
720
721                 if (!(bmsr & BMSR_LSTATUS)) {
722                         err = tg3_init_5401phy_dsp(tp);
723                         if (err)
724                                 return err;
725
726                         tg3_readphy(tp, MII_BMSR, &bmsr);
727                         for (i = 0; i < 1000; i++) {
728                                 udelay(10);
729                                 tg3_readphy(tp, MII_BMSR, &bmsr);
730                                 if (bmsr & BMSR_LSTATUS) {
731                                         udelay(40);
732                                         break;
733                                 }
734                         }
735
736                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
737                             !(bmsr & BMSR_LSTATUS) &&
738                             tp->link_config.active_speed == SPEED_1000) {
739                                 err = tg3_phy_reset(tp);
740                                 if (!err)
741                                         err = tg3_init_5401phy_dsp(tp);
742                                 if (err)
743                                         return err;
744                         }
745                 }
746         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
747                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
748                 /* 5701 {A0,B0} CRC bug workaround */
749                 tg3_writephy(tp, 0x15, 0x0a75);
750                 tg3_writephy(tp, 0x1c, 0x8c68);
751                 tg3_writephy(tp, 0x1c, 0x8d68);
752                 tg3_writephy(tp, 0x1c, 0x8c68);
753         }
754
755         /* Clear pending interrupts... */
756         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
757         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
758
759         tg3_writephy(tp, MII_TG3_IMASK, ~0);
760
761         if (tp->led_mode == led_mode_three_link)
762                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
763                              MII_TG3_EXT_CTRL_LNK3_LED_MODE);
764         else
765                 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
766
767         current_link_up = 0;
768
769         tg3_readphy(tp, MII_BMSR, &bmsr);
770         tg3_readphy(tp, MII_BMSR, &bmsr);
771
772         if (bmsr & BMSR_LSTATUS) {
773                 uint32_t aux_stat, bmcr;
774
775                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
776                 for (i = 0; i < 2000; i++) {
777                         udelay(10);
778                         tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
779                         if (aux_stat)
780                                 break;
781                 }
782
783                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
784                         &tp->link_config.active_speed,
785                         &tp->link_config.active_duplex);
786                 tg3_readphy(tp, MII_BMCR, &bmcr);
787                 tg3_readphy(tp, MII_BMCR, &bmcr);
788                 if (bmcr & BMCR_ANENABLE) {
789                         uint32_t gig_ctrl;
790                         
791                         current_link_up = 1;
792                         
793                         /* Force autoneg restart if we are exiting
794                          * low power mode.
795                          */
796                         tg3_readphy(tp, MII_TG3_CTRL, &gig_ctrl);
797                         if (!(gig_ctrl & (MII_TG3_CTRL_ADV_1000_HALF |
798                                       MII_TG3_CTRL_ADV_1000_FULL))) {
799                                 current_link_up = 0;
800                         }
801                 } else {
802                         current_link_up = 0;
803                 }
804         }
805
806         if (current_link_up == 1 &&
807                 (tp->link_config.active_duplex == DUPLEX_FULL)) {
808                 uint32_t local_adv, remote_adv;
809
810                 tg3_readphy(tp, MII_ADVERTISE, &local_adv);
811                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
812
813                 tg3_readphy(tp, MII_LPA, &remote_adv);
814                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
815
816                 /* If we are not advertising full pause capability,
817                  * something is wrong.  Bring the link down and reconfigure.
818                  */
819                 if (local_adv != ADVERTISE_PAUSE_CAP) {
820                         current_link_up = 0;
821                 } else {
822                         tg3_setup_flow_control(tp, local_adv, remote_adv);
823                 }
824         }
825
826         if (current_link_up == 0) {
827                 uint32_t tmp;
828
829                 tg3_phy_copper_begin(tp);
830
831                 tg3_readphy(tp, MII_BMSR, &tmp);
832                 tg3_readphy(tp, MII_BMSR, &tmp);
833                 if (tmp & BMSR_LSTATUS)
834                         current_link_up = 1;
835         }
836
837         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
838         if (current_link_up == 1) {
839                 if (tp->link_config.active_speed == SPEED_100 ||
840                     tp->link_config.active_speed == SPEED_10)
841                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
842                 else
843                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
844         } else
845                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
846
847         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
848         if (tp->link_config.active_duplex == DUPLEX_HALF)
849                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
850
851         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
852         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
853                 if ((tp->led_mode == led_mode_link10) ||
854                     (current_link_up == 1 &&
855                      tp->link_config.active_speed == SPEED_10))
856                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
857         } else {
858                 if (current_link_up == 1)
859                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
860                 tw32(MAC_LED_CTRL, LED_CTRL_PHY_MODE_1);
861         }
862
863         /* ??? Without this setting Netgear GA302T PHY does not
864          * ??? send/receive packets...
865          * With this other PHYs cannot bring up the link
866          */
867         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
868                 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
869                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
870                 tw32_carefully(MAC_MI_MODE, tp->mi_mode);
871         }
872
873         tw32_carefully(MAC_MODE, tp->mac_mode);
874
875         /* Link change polled. */
876         tw32_carefully(MAC_EVENT, 0);
877
878         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
879             current_link_up == 1 &&
880             tp->link_config.active_speed == SPEED_1000 &&
881             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
882              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
883                 udelay(120);
884                 tw32_carefully(MAC_STATUS,
885                         (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED));
886                 tg3_write_mem(
887                               NIC_SRAM_FIRMWARE_MBOX,
888                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
889         }
890
891         if (current_link_up != tp->carrier_ok) {
892                 tp->carrier_ok = current_link_up;
893                 tg3_link_report(tp);
894         }
895
896         return 0;
897 }
898 #else
899 #define tg3_setup_copper_phy(TP) (-EINVAL)
900 #endif /* SUPPORT_COPPER_PHY */
901
902 #if SUPPORT_FIBER_PHY
903 struct tg3_fiber_aneginfo {
904         int state;
905 #define ANEG_STATE_UNKNOWN              0
906 #define ANEG_STATE_AN_ENABLE            1
907 #define ANEG_STATE_RESTART_INIT         2
908 #define ANEG_STATE_RESTART              3
909 #define ANEG_STATE_DISABLE_LINK_OK      4
910 #define ANEG_STATE_ABILITY_DETECT_INIT  5
911 #define ANEG_STATE_ABILITY_DETECT       6
912 #define ANEG_STATE_ACK_DETECT_INIT      7
913 #define ANEG_STATE_ACK_DETECT           8
914 #define ANEG_STATE_COMPLETE_ACK_INIT    9
915 #define ANEG_STATE_COMPLETE_ACK         10
916 #define ANEG_STATE_IDLE_DETECT_INIT     11
917 #define ANEG_STATE_IDLE_DETECT          12
918 #define ANEG_STATE_LINK_OK              13
919 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
920 #define ANEG_STATE_NEXT_PAGE_WAIT       15
921
922         uint32_t flags;
923 #define MR_AN_ENABLE            0x00000001
924 #define MR_RESTART_AN           0x00000002
925 #define MR_AN_COMPLETE          0x00000004
926 #define MR_PAGE_RX              0x00000008
927 #define MR_NP_LOADED            0x00000010
928 #define MR_TOGGLE_TX            0x00000020
929 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
930 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
931 #define MR_LP_ADV_SYM_PAUSE     0x00000100
932 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
933 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
934 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
935 #define MR_LP_ADV_NEXT_PAGE     0x00001000
936 #define MR_TOGGLE_RX            0x00002000
937 #define MR_NP_RX                0x00004000
938
939 #define MR_LINK_OK              0x80000000
940
941         unsigned long link_time, cur_time;
942
943         uint32_t ability_match_cfg;
944         int ability_match_count;
945
946         char ability_match, idle_match, ack_match;
947
948         uint32_t txconfig, rxconfig;
949 #define ANEG_CFG_NP             0x00000080
950 #define ANEG_CFG_ACK            0x00000040
951 #define ANEG_CFG_RF2            0x00000020
952 #define ANEG_CFG_RF1            0x00000010
953 #define ANEG_CFG_PS2            0x00000001
954 #define ANEG_CFG_PS1            0x00008000
955 #define ANEG_CFG_HD             0x00004000
956 #define ANEG_CFG_FD             0x00002000
957 #define ANEG_CFG_INVAL          0x00001f06
958
959 };
960 #define ANEG_OK         0
961 #define ANEG_DONE       1
962 #define ANEG_TIMER_ENAB 2
963 #define ANEG_FAILED     -1
964
965 #define ANEG_STATE_SETTLE_TIME  10000
966
967 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
968                                    struct tg3_fiber_aneginfo *ap)
969 {
970         unsigned long delta;
971         uint32_t rx_cfg_reg;
972         int ret;
973
974         if (ap->state == ANEG_STATE_UNKNOWN) {
975                 ap->rxconfig = 0;
976                 ap->link_time = 0;
977                 ap->cur_time = 0;
978                 ap->ability_match_cfg = 0;
979                 ap->ability_match_count = 0;
980                 ap->ability_match = 0;
981                 ap->idle_match = 0;
982                 ap->ack_match = 0;
983         }
984         ap->cur_time++;
985
986         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
987                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
988
989                 if (rx_cfg_reg != ap->ability_match_cfg) {
990                         ap->ability_match_cfg = rx_cfg_reg;
991                         ap->ability_match = 0;
992                         ap->ability_match_count = 0;
993                 } else {
994                         if (++ap->ability_match_count > 1) {
995                                 ap->ability_match = 1;
996                                 ap->ability_match_cfg = rx_cfg_reg;
997                         }
998                 }
999                 if (rx_cfg_reg & ANEG_CFG_ACK)
1000                         ap->ack_match = 1;
1001                 else
1002                         ap->ack_match = 0;
1003
1004                 ap->idle_match = 0;
1005         } else {
1006                 ap->idle_match = 1;
1007                 ap->ability_match_cfg = 0;
1008                 ap->ability_match_count = 0;
1009                 ap->ability_match = 0;
1010                 ap->ack_match = 0;
1011
1012                 rx_cfg_reg = 0;
1013         }
1014
1015         ap->rxconfig = rx_cfg_reg;
1016         ret = ANEG_OK;
1017
1018         switch(ap->state) {
1019         case ANEG_STATE_UNKNOWN:
1020                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
1021                         ap->state = ANEG_STATE_AN_ENABLE;
1022
1023                 /* fallthru */
1024         case ANEG_STATE_AN_ENABLE:
1025                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
1026                 if (ap->flags & MR_AN_ENABLE) {
1027                         ap->link_time = 0;
1028                         ap->cur_time = 0;
1029                         ap->ability_match_cfg = 0;
1030                         ap->ability_match_count = 0;
1031                         ap->ability_match = 0;
1032                         ap->idle_match = 0;
1033                         ap->ack_match = 0;
1034
1035                         ap->state = ANEG_STATE_RESTART_INIT;
1036                 } else {
1037                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
1038                 }
1039                 break;
1040
1041         case ANEG_STATE_RESTART_INIT:
1042                 ap->link_time = ap->cur_time;
1043                 ap->flags &= ~(MR_NP_LOADED);
1044                 ap->txconfig = 0;
1045                 tw32(MAC_TX_AUTO_NEG, 0);
1046                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1047                 tw32_carefully(MAC_MODE, tp->mac_mode);
1048
1049                 ret = ANEG_TIMER_ENAB;
1050                 ap->state = ANEG_STATE_RESTART;
1051
1052                 /* fallthru */
1053         case ANEG_STATE_RESTART:
1054                 delta = ap->cur_time - ap->link_time;
1055                 if (delta > ANEG_STATE_SETTLE_TIME) {
1056                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
1057                 } else {
1058                         ret = ANEG_TIMER_ENAB;
1059                 }
1060                 break;
1061
1062         case ANEG_STATE_DISABLE_LINK_OK:
1063                 ret = ANEG_DONE;
1064                 break;
1065
1066         case ANEG_STATE_ABILITY_DETECT_INIT:
1067                 ap->flags &= ~(MR_TOGGLE_TX);
1068                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
1069                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1070                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1071                 tw32_carefully(MAC_MODE, tp->mac_mode);
1072
1073                 ap->state = ANEG_STATE_ABILITY_DETECT;
1074                 break;
1075
1076         case ANEG_STATE_ABILITY_DETECT:
1077                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
1078                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
1079                 }
1080                 break;
1081
1082         case ANEG_STATE_ACK_DETECT_INIT:
1083                 ap->txconfig |= ANEG_CFG_ACK;
1084                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
1085                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
1086                 tw32_carefully(MAC_MODE, tp->mac_mode);
1087
1088                 ap->state = ANEG_STATE_ACK_DETECT;
1089
1090                 /* fallthru */
1091         case ANEG_STATE_ACK_DETECT:
1092                 if (ap->ack_match != 0) {
1093                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
1094                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
1095                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
1096                         } else {
1097                                 ap->state = ANEG_STATE_AN_ENABLE;
1098                         }
1099                 } else if (ap->ability_match != 0 &&
1100                            ap->rxconfig == 0) {
1101                         ap->state = ANEG_STATE_AN_ENABLE;
1102                 }
1103                 break;
1104
1105         case ANEG_STATE_COMPLETE_ACK_INIT:
1106                 if (ap->rxconfig & ANEG_CFG_INVAL) {
1107                         ret = ANEG_FAILED;
1108                         break;
1109                 }
1110                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
1111                                MR_LP_ADV_HALF_DUPLEX |
1112                                MR_LP_ADV_SYM_PAUSE |
1113                                MR_LP_ADV_ASYM_PAUSE |
1114                                MR_LP_ADV_REMOTE_FAULT1 |
1115                                MR_LP_ADV_REMOTE_FAULT2 |
1116                                MR_LP_ADV_NEXT_PAGE |
1117                                MR_TOGGLE_RX |
1118                                MR_NP_RX);
1119                 if (ap->rxconfig & ANEG_CFG_FD)
1120                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
1121                 if (ap->rxconfig & ANEG_CFG_HD)
1122                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
1123                 if (ap->rxconfig & ANEG_CFG_PS1)
1124                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
1125                 if (ap->rxconfig & ANEG_CFG_PS2)
1126                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
1127                 if (ap->rxconfig & ANEG_CFG_RF1)
1128                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
1129                 if (ap->rxconfig & ANEG_CFG_RF2)
1130                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
1131                 if (ap->rxconfig & ANEG_CFG_NP)
1132                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
1133
1134                 ap->link_time = ap->cur_time;
1135
1136                 ap->flags ^= (MR_TOGGLE_TX);
1137                 if (ap->rxconfig & 0x0008)
1138                         ap->flags |= MR_TOGGLE_RX;
1139                 if (ap->rxconfig & ANEG_CFG_NP)
1140                         ap->flags |= MR_NP_RX;
1141                 ap->flags |= MR_PAGE_RX;
1142
1143                 ap->state = ANEG_STATE_COMPLETE_ACK;
1144                 ret = ANEG_TIMER_ENAB;
1145                 break;
1146
1147         case ANEG_STATE_COMPLETE_ACK:
1148                 if (ap->ability_match != 0 &&
1149                     ap->rxconfig == 0) {
1150                         ap->state = ANEG_STATE_AN_ENABLE;
1151                         break;
1152                 }
1153                 delta = ap->cur_time - ap->link_time;
1154                 if (delta > ANEG_STATE_SETTLE_TIME) {
1155                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
1156                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
1157                         } else {
1158                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
1159                                     !(ap->flags & MR_NP_RX)) {
1160                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
1161                                 } else {
1162                                         ret = ANEG_FAILED;
1163                                 }
1164                         }
1165                 }
1166                 break;
1167
1168         case ANEG_STATE_IDLE_DETECT_INIT:
1169                 ap->link_time = ap->cur_time;
1170                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
1171                 tw32_carefully(MAC_MODE, tp->mac_mode);
1172
1173                 ap->state = ANEG_STATE_IDLE_DETECT;
1174                 ret = ANEG_TIMER_ENAB;
1175                 break;
1176
1177         case ANEG_STATE_IDLE_DETECT:
1178                 if (ap->ability_match != 0 &&
1179                     ap->rxconfig == 0) {
1180                         ap->state = ANEG_STATE_AN_ENABLE;
1181                         break;
1182                 }
1183                 delta = ap->cur_time - ap->link_time;
1184                 if (delta > ANEG_STATE_SETTLE_TIME) {
1185                         /* XXX another gem from the Broadcom driver :( */
1186                         ap->state = ANEG_STATE_LINK_OK;
1187                 }
1188                 break;
1189
1190         case ANEG_STATE_LINK_OK:
1191                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
1192                 ret = ANEG_DONE;
1193                 break;
1194
1195         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
1196                 /* ??? unimplemented */
1197                 break;
1198
1199         case ANEG_STATE_NEXT_PAGE_WAIT:
1200                 /* ??? unimplemented */
1201                 break;
1202
1203         default:
1204                 ret = ANEG_FAILED;
1205                 break;
1206         };
1207
1208         return ret;
1209 }
1210
1211 static int tg3_setup_fiber_phy(struct tg3 *tp)
1212 {
1213         uint32_t orig_pause_cfg;
1214         uint16_t orig_active_speed;
1215         uint8_t orig_active_duplex;
1216         int current_link_up;
1217         int i;
1218
1219         orig_pause_cfg =
1220                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
1221                                   TG3_FLAG_TX_PAUSE));
1222         orig_active_speed = tp->link_config.active_speed;
1223         orig_active_duplex = tp->link_config.active_duplex;
1224
1225         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
1226         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
1227         tw32_carefully(MAC_MODE, tp->mac_mode);
1228
1229         /* Reset when initting first time or we have a link. */
1230         if (!(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) ||
1231             (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED)) {
1232                 /* Set PLL lock range. */
1233                 tg3_writephy(tp, 0x16, 0x8007);
1234
1235                 /* SW reset */
1236                 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
1237
1238                 /* Wait for reset to complete. */
1239                 mdelay(5);
1240
1241                 /* Config mode; select PMA/Ch 1 regs. */
1242                 tg3_writephy(tp, 0x10, 0x8411);
1243
1244                 /* Enable auto-lock and comdet, select txclk for tx. */
1245                 tg3_writephy(tp, 0x11, 0x0a10);
1246
1247                 tg3_writephy(tp, 0x18, 0x00a0);
1248                 tg3_writephy(tp, 0x16, 0x41ff);
1249
1250                 /* Assert and deassert POR. */
1251                 tg3_writephy(tp, 0x13, 0x0400);
1252                 udelay(40);
1253                 tg3_writephy(tp, 0x13, 0x0000);
1254
1255                 tg3_writephy(tp, 0x11, 0x0a50);
1256                 udelay(40);
1257                 tg3_writephy(tp, 0x11, 0x0a10);
1258
1259                 /* Wait for signal to stabilize */
1260                 mdelay(150);
1261
1262                 /* Deselect the channel register so we can read the PHYID
1263                  * later.
1264                  */
1265                 tg3_writephy(tp, 0x10, 0x8011);
1266         }
1267
1268         /* Disable link change interrupt.  */
1269         tw32_carefully(MAC_EVENT, 0);
1270
1271         current_link_up = 0;
1272         if (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) {
1273                 if (!(tp->tg3_flags & TG3_FLAG_GOT_SERDES_FLOWCTL)) {
1274                         struct tg3_fiber_aneginfo aninfo;
1275                         int status = ANEG_FAILED;
1276                         unsigned int tick;
1277                         uint32_t tmp;
1278
1279                         memset(&aninfo, 0, sizeof(aninfo));
1280                         aninfo.flags |= (MR_AN_ENABLE);
1281
1282                         tw32(MAC_TX_AUTO_NEG, 0);
1283
1284                         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
1285                         tw32_carefully(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
1286
1287                         tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
1288
1289                         aninfo.state = ANEG_STATE_UNKNOWN;
1290                         aninfo.cur_time = 0;
1291                         tick = 0;
1292                         while (++tick < 195000) {
1293                                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
1294                                 if (status == ANEG_DONE ||
1295                                     status == ANEG_FAILED)
1296                                         break;
1297
1298                                 udelay(1);
1299                         }
1300
1301                         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
1302                         tw32_carefully(MAC_MODE, tp->mac_mode);
1303
1304                         if (status == ANEG_DONE &&
1305                             (aninfo.flags &
1306                              (MR_AN_COMPLETE | MR_LINK_OK |
1307                               MR_LP_ADV_FULL_DUPLEX))) {
1308                                 uint32_t local_adv, remote_adv;
1309
1310                                 local_adv = ADVERTISE_PAUSE_CAP;
1311                                 remote_adv = 0;
1312                                 if (aninfo.flags & MR_LP_ADV_SYM_PAUSE)
1313                                         remote_adv |= LPA_PAUSE_CAP;
1314                                 if (aninfo.flags & MR_LP_ADV_ASYM_PAUSE)
1315                                         remote_adv |= LPA_PAUSE_ASYM;
1316
1317                                 tg3_setup_flow_control(tp, local_adv, remote_adv);
1318
1319                                 tp->tg3_flags |=
1320                                         TG3_FLAG_GOT_SERDES_FLOWCTL;
1321                                 current_link_up = 1;
1322                         }
1323                         for (i = 0; i < 60; i++) {
1324                                 udelay(20);
1325                                 tw32_carefully(MAC_STATUS,
1326                                         (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED));
1327                                 if ((tr32(MAC_STATUS) &
1328                                      (MAC_STATUS_SYNC_CHANGED |
1329                                       MAC_STATUS_CFG_CHANGED)) == 0)
1330                                         break;
1331                         }
1332                         if (current_link_up == 0 &&
1333                             (tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED)) {
1334                                 current_link_up = 1;
1335                         }
1336                 } else {
1337                         /* Forcing 1000FD link up. */
1338                         current_link_up = 1;
1339                 }
1340         }
1341
1342         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1343         tw32_carefully(MAC_MODE, tp->mac_mode);
1344
1345         tp->hw_status->status =
1346                 (SD_STATUS_UPDATED |
1347                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
1348
1349         for (i = 0; i < 100; i++) {
1350                 udelay(20);
1351                 tw32_carefully(MAC_STATUS,
1352                         (MAC_STATUS_SYNC_CHANGED | MAC_STATUS_CFG_CHANGED));
1353                 if ((tr32(MAC_STATUS) &
1354                      (MAC_STATUS_SYNC_CHANGED |
1355                       MAC_STATUS_CFG_CHANGED)) == 0)
1356                         break;
1357         }
1358
1359         if ((tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) == 0)
1360                 current_link_up = 0;
1361
1362         if (current_link_up == 1) {
1363                 tp->link_config.active_speed = SPEED_1000;
1364                 tp->link_config.active_duplex = DUPLEX_FULL;
1365         } else {
1366                 tp->link_config.active_speed = SPEED_INVALID;
1367                 tp->link_config.active_duplex = DUPLEX_INVALID;
1368         }
1369
1370         if (current_link_up != tp->carrier_ok) {
1371                 tp->carrier_ok = current_link_up;
1372                 tg3_link_report(tp);
1373         } else {
1374                 uint32_t now_pause_cfg =
1375                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
1376                                          TG3_FLAG_TX_PAUSE);
1377                 if (orig_pause_cfg != now_pause_cfg ||
1378                     orig_active_speed != tp->link_config.active_speed ||
1379                     orig_active_duplex != tp->link_config.active_duplex)
1380                         tg3_link_report(tp);
1381         }
1382
1383         if ((tr32(MAC_STATUS) & MAC_STATUS_PCS_SYNCED) == 0) {
1384                 tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_LINK_POLARITY);
1385                 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
1386                         tw32_carefully(MAC_MODE, tp->mac_mode);
1387                 }
1388         }
1389
1390         return 0;
1391 }
1392 #else
1393 #define tg3_setup_fiber_phy(TP) (-EINVAL)
1394 #endif /* SUPPORT_FIBER_PHY */
1395
1396 static int tg3_setup_phy(struct tg3 *tp)
1397 {
1398         int err;
1399
1400         if (tp->phy_id == PHY_ID_SERDES) {
1401                 err = tg3_setup_fiber_phy(tp);
1402         } else {
1403                 err = tg3_setup_copper_phy(tp);
1404         }
1405
1406         if (tp->link_config.active_speed == SPEED_1000 &&
1407             tp->link_config.active_duplex == DUPLEX_HALF)
1408                 tw32(MAC_TX_LENGTHS,
1409                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1410                       (6 << TX_LENGTHS_IPG_SHIFT) |
1411                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1412         else
1413                 tw32(MAC_TX_LENGTHS,
1414                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1415                       (6 << TX_LENGTHS_IPG_SHIFT) |
1416                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1417
1418         return err;
1419 }
1420
1421
1422 #define MAX_WAIT_CNT 1000
1423
1424 /* To stop a block, clear the enable bit and poll till it
1425  * clears.  
1426  */
1427 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, uint32_t enable_bit)
1428 {
1429         unsigned int i;
1430         uint32_t val;
1431
1432         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1433                 switch(ofs) {
1434                 case RCVLSC_MODE:
1435                 case DMAC_MODE:
1436                 case MBFREE_MODE:
1437                 case BUFMGR_MODE:
1438                 case MEMARB_MODE:
1439                         /* We can't enable/disable these bits of the
1440                          * 5705, just say success.
1441                          */
1442                         return 0;
1443                 default:
1444                         break;
1445                 }
1446         }
1447         val = tr32(ofs);
1448         val &= ~enable_bit;
1449         tw32(ofs, val);
1450         tr32(ofs);
1451
1452         for (i = 0; i < MAX_WAIT_CNT; i++) {
1453                 udelay(100);
1454                 val = tr32(ofs);
1455                 if ((val & enable_bit) == 0)
1456                         break;
1457         }
1458
1459         if (i == MAX_WAIT_CNT) {
1460                 printf("tg3_stop_block timed out, ofs=%lx enable_bit=%x\n",
1461                        ofs, enable_bit);
1462                 return -ENODEV;
1463         }
1464
1465         return 0;
1466 }
1467
1468 static int tg3_abort_hw(struct tg3 *tp)
1469 {
1470         int i, err;
1471
1472         tg3_disable_ints(tp);
1473
1474         tp->rx_mode &= ~RX_MODE_ENABLE;
1475         tw32_carefully(MAC_RX_MODE, tp->rx_mode);
1476
1477         err  = tg3_stop_block(tp, RCVBDI_MODE,   RCVBDI_MODE_ENABLE);
1478         err |= tg3_stop_block(tp, RCVLPC_MODE,   RCVLPC_MODE_ENABLE);
1479         err |= tg3_stop_block(tp, RCVLSC_MODE,   RCVLSC_MODE_ENABLE);
1480         err |= tg3_stop_block(tp, RCVDBDI_MODE,  RCVDBDI_MODE_ENABLE);
1481         err |= tg3_stop_block(tp, RCVDCC_MODE,   RCVDCC_MODE_ENABLE);
1482         err |= tg3_stop_block(tp, RCVCC_MODE,    RCVCC_MODE_ENABLE);
1483
1484         err |= tg3_stop_block(tp, SNDBDS_MODE,   SNDBDS_MODE_ENABLE);
1485         err |= tg3_stop_block(tp, SNDBDI_MODE,   SNDBDI_MODE_ENABLE);
1486         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
1487         err |= tg3_stop_block(tp, RDMAC_MODE,    RDMAC_MODE_ENABLE);
1488         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
1489         err |= tg3_stop_block(tp, SNDBDC_MODE,   SNDBDC_MODE_ENABLE);
1490         if (err)
1491                 goto out;
1492
1493         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
1494         tw32_carefully(MAC_MODE, tp->mac_mode);
1495
1496         tp->tx_mode &= ~TX_MODE_ENABLE;
1497         tw32_carefully(MAC_TX_MODE, tp->tx_mode);
1498
1499         for (i = 0; i < MAX_WAIT_CNT; i++) {
1500                 udelay(100);
1501                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
1502                         break;
1503         }
1504         if (i >= MAX_WAIT_CNT) {
1505                 printf("tg3_abort_hw timed out TX_MODE_ENABLE will not clear MAC_TX_MODE=%x\n",
1506                         tr32(MAC_TX_MODE));
1507                 return -ENODEV;
1508         }
1509
1510         err  = tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE);
1511         err |= tg3_stop_block(tp, WDMAC_MODE,  WDMAC_MODE_ENABLE);
1512         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE);
1513
1514         tw32(FTQ_RESET, 0xffffffff);
1515         tw32(FTQ_RESET, 0x00000000);
1516
1517         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE);
1518         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE);
1519         if (err)
1520                 goto out;
1521
1522         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
1523
1524 out:
1525         return err;
1526 }
1527
1528 static void tg3_chip_reset(struct tg3 *tp)
1529 {
1530         uint32_t val;
1531
1532         if (!(tp->tg3_flags2 & TG3_FLG2_SUN_5704)) {
1533                 /* Force NVRAM to settle.
1534                  * This deals with a chip bug which can result in EEPROM
1535                  * corruption.
1536                  */
1537                 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
1538                         int i;
1539         
1540                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
1541                         for (i = 0; i < 100000; i++) {
1542                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
1543                                         break;
1544                                 udelay(10);
1545                         }
1546                 }
1547         }
1548         /* In Etherboot we don't need to worry about the 5701
1549          * REG_WRITE_BUG because we do all register writes indirectly.
1550          */
1551
1552         // Alf: here patched
1553         /* do the reset */
1554         val = GRC_MISC_CFG_CORECLK_RESET;
1555         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
1556             || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
1557                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
1558         }
1559
1560         // Alf : Please VALIDATE THIS.
1561         // It is necessary in my case (5751) to prevent a reboot, but
1562         // I have no idea about a side effect on any other version.
1563         // It appears to be what's done in tigon3.c from Broadcom
1564         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
1565           tw32(GRC_MISC_CFG, 0x20000000) ;
1566           val |= 0x20000000 ;
1567         }
1568
1569         tw32(GRC_MISC_CFG, val);
1570
1571         /* Flush PCI posted writes.  The normal MMIO registers
1572          * are inaccessible at this time so this is the only
1573          * way to make this reliably.  I tried to use indirect
1574          * register read/write but this upset some 5701 variants.
1575          */
1576         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
1577
1578         udelay(120);
1579
1580         /* Re-enable indirect register accesses. */
1581         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
1582                                tp->misc_host_ctrl);
1583
1584         /* Set MAX PCI retry to zero. */
1585         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
1586         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
1587             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
1588                 val |= PCISTATE_RETRY_SAME_DMA;
1589         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
1590
1591         pci_restore_state(tp->pdev, tp->pci_cfg_state);
1592
1593         /* Make sure PCI-X relaxed ordering bit is clear. */
1594         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
1595         val &= ~PCIX_CAPS_RELAXED_ORDERING;
1596         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
1597
1598         tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
1599
1600         if (((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0) &&
1601                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
1602                 tp->pci_clock_ctrl |=
1603                         (CLOCK_CTRL_FORCE_CLKRUN | CLOCK_CTRL_CLKRUN_OENABLE);
1604                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
1605         }
1606
1607         tw32(TG3PCI_MISC_HOST_CTRL, tp->misc_host_ctrl);
1608 }
1609
1610 static void tg3_stop_fw(struct tg3 *tp)
1611 {
1612         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
1613                 uint32_t val;
1614                 int i;
1615
1616                 tg3_write_mem(NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
1617                 val = tr32(GRC_RX_CPU_EVENT);
1618                 val |= (1 << 14);
1619                 tw32(GRC_RX_CPU_EVENT, val);
1620
1621                 /* Wait for RX cpu to ACK the event.  */
1622                 for (i = 0; i < 100; i++) {
1623                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
1624                                 break;
1625                         udelay(1);
1626                 }
1627         }
1628 }
1629
1630 static int tg3_restart_fw(struct tg3 *tp, uint32_t state)
1631 {
1632         uint32_t val;
1633         int i;
1634         
1635         tg3_write_mem(NIC_SRAM_FIRMWARE_MBOX, 
1636                 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
1637         /* Wait for firmware initialization to complete. */
1638         for (i = 0; i < 100000; i++) {
1639                 tg3_read_mem(NIC_SRAM_FIRMWARE_MBOX, &val);
1640                 if (val == (uint32_t) ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1641                         break;
1642                 udelay(10);
1643         }
1644         if (i >= 100000 &&
1645                     !(tp->tg3_flags2 & TG3_FLG2_SUN_5704)) {
1646                 printf("Firmware will not restart magic=%x\n",
1647                         val);
1648                 return -ENODEV;
1649         }
1650         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1651           state = DRV_STATE_SUSPEND;
1652         }
1653
1654         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
1655             (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)) {
1656           // Enable PCIE bug fix
1657           tg3_read_mem(0x7c00, &val);
1658           tg3_write_mem(0x7c00, val | 0x02000000);
1659         }
1660         tg3_write_mem(NIC_SRAM_FW_DRV_STATE_MBOX, state);
1661         return 0;
1662 }
1663
1664 static int tg3_halt(struct tg3 *tp)
1665 {
1666         tg3_stop_fw(tp);
1667         tg3_abort_hw(tp);
1668         tg3_chip_reset(tp);
1669         return tg3_restart_fw(tp, DRV_STATE_UNLOAD);
1670 }
1671
1672 static void __tg3_set_mac_addr(struct tg3 *tp)
1673 {
1674         uint32_t addr_high, addr_low;
1675         int i;
1676
1677         addr_high = ((tp->nic->node_addr[0] << 8) |
1678                      tp->nic->node_addr[1]);
1679         addr_low = ((tp->nic->node_addr[2] << 24) |
1680                     (tp->nic->node_addr[3] << 16) |
1681                     (tp->nic->node_addr[4] <<  8) |
1682                     (tp->nic->node_addr[5] <<  0));
1683         for (i = 0; i < 4; i++) {
1684                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
1685                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
1686         }
1687
1688         if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
1689                 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
1690                 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705)) {
1691                 for(i = 0; i < 12; i++) {
1692                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
1693                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
1694                 }
1695         }
1696         addr_high = (tp->nic->node_addr[0] +
1697                      tp->nic->node_addr[1] +
1698                      tp->nic->node_addr[2] +
1699                      tp->nic->node_addr[3] +
1700                      tp->nic->node_addr[4] +
1701                      tp->nic->node_addr[5]) &
1702                 TX_BACKOFF_SEED_MASK;
1703         tw32(MAC_TX_BACKOFF_SEED, addr_high);
1704 }
1705
1706 static void tg3_set_bdinfo(struct tg3 *tp, uint32_t bdinfo_addr,
1707                            dma_addr_t mapping, uint32_t maxlen_flags,
1708                            uint32_t nic_addr)
1709 {
1710         tg3_write_mem((bdinfo_addr +
1711                        TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
1712                       ((uint64_t) mapping >> 32));
1713         tg3_write_mem((bdinfo_addr +
1714                        TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
1715                       ((uint64_t) mapping & 0xffffffff));
1716         tg3_write_mem((bdinfo_addr +
1717                        TG3_BDINFO_MAXLEN_FLAGS),
1718                        maxlen_flags);
1719         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1720                 tg3_write_mem((bdinfo_addr + TG3_BDINFO_NIC_ADDR), nic_addr);
1721         }
1722 }
1723
1724
1725 static void tg3_init_rings(struct tg3 *tp)
1726 {
1727         unsigned i;
1728
1729         /* Zero out the tg3 variables */
1730         memset(&tg3_bss, 0, sizeof(tg3_bss));
1731         tp->rx_std    = &tg3_bss.rx_std[0];
1732         tp->rx_rcb    = &tg3_bss.rx_rcb[0];
1733         tp->tx_ring   = &tg3_bss.tx_ring[0];
1734         tp->hw_status = &tg3_bss.hw_status;
1735         tp->hw_stats  = &tg3_bss.hw_stats;
1736         tp->mac_mode  = 0;
1737
1738
1739         /* Initialize tx/rx rings for packet processing.
1740          *
1741          * The chip has been shut down and the driver detached from
1742          * the networking, so no interrupts or new tx packets will
1743          * end up in the driver.
1744          */
1745
1746         /* Initialize invariants of the rings, we only set this
1747          * stuff once.  This works because the card does not
1748          * write into the rx buffer posting rings.
1749          */
1750         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
1751                 struct tg3_rx_buffer_desc *rxd;
1752
1753                 rxd = &tp->rx_std[i];
1754                 rxd->idx_len = (RX_PKT_BUF_SZ - 2 - 64) << RXD_LEN_SHIFT;
1755                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
1756                 rxd->opaque = (RXD_OPAQUE_RING_STD | (i << RXD_OPAQUE_INDEX_SHIFT));
1757
1758                 /* Note where the receive buffer for the ring is placed */
1759                 rxd->addr_hi = 0;
1760                 rxd->addr_lo = virt_to_bus(
1761                         &tg3_bss.rx_bufs[i%TG3_DEF_RX_RING_PENDING][2]);
1762         }
1763 }
1764
1765 #define TG3_WRITE_SETTINGS(TABLE) \
1766 do { \
1767         const uint32_t *_table, *_end; \
1768         _table = TABLE; \
1769         _end = _table + sizeof(TABLE)/sizeof(TABLE[0]);  \
1770         for(; _table < _end; _table += 2) { \
1771                 tw32(_table[0], _table[1]); \
1772         } \
1773 } while(0)
1774
1775
1776 /* initialize/reset the tg3 */
1777 static int tg3_setup_hw(struct tg3 *tp)
1778 {
1779         uint32_t val, rdmac_mode;
1780         int i, err, limit;
1781
1782         /* Simply don't support setups with extremly buggy firmware in etherboot */
1783         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
1784                 printf("Error 5701_A0 firmware bug detected\n");
1785                 return -EINVAL;
1786         }
1787
1788         tg3_disable_ints(tp);
1789
1790         /* Originally this was all in tg3_init_hw */
1791
1792         /* Force the chip into D0. */
1793         tg3_set_power_state_0(tp);
1794
1795         tg3_switch_clocks(tp);
1796
1797         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
1798
1799         // This should go somewhere else
1800 #define T3_PCIE_CAPABILITY_ID_REG           0xD0
1801 #define T3_PCIE_CAPABILITY_ID               0x10
1802 #define T3_PCIE_CAPABILITY_REG              0xD2
1803
1804         /* Originally this was all in tg3_reset_hw */
1805
1806         tg3_stop_fw(tp);
1807
1808         /* No need to call tg3_abort_hw here, it is called before tg3_setup_hw. */
1809
1810         tg3_chip_reset(tp);
1811
1812         tw32(GRC_MODE, tp->grc_mode);  /* Redundant? */
1813
1814         err = tg3_restart_fw(tp, DRV_STATE_START);
1815         if (err)
1816                 return err;
1817
1818         if (tp->phy_id == PHY_ID_SERDES) {
1819                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
1820         }
1821         tw32_carefully(MAC_MODE, tp->mac_mode);
1822
1823
1824         /* This works around an issue with Athlon chipsets on
1825          * B3 tigon3 silicon.  This bit has no effect on any
1826          * other revision.
1827          * Alf: Except 5750 ! (which reboots)
1828          */
1829
1830         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
1831           tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
1832         tw32_carefully(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
1833
1834         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
1835             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
1836                 val = tr32(TG3PCI_PCISTATE);
1837                 val |= PCISTATE_RETRY_SAME_DMA;
1838                 tw32(TG3PCI_PCISTATE, val);
1839         }
1840
1841         /* Descriptor ring init may make accesses to the
1842          * NIC SRAM area to setup the TX descriptors, so we
1843          * can only do this after the hardware has been
1844          * successfully reset.
1845          */
1846         tg3_init_rings(tp);
1847
1848         /* Clear statistics/status block in chip */
1849         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1850                 for (i = NIC_SRAM_STATS_BLK;
1851                      i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
1852                      i += sizeof(uint32_t)) {
1853                         tg3_write_mem(i, 0);
1854                         udelay(40);
1855                 }
1856         }
1857
1858         /* This value is determined during the probe time DMA
1859          * engine test, tg3_setup_dma.
1860          */
1861         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
1862
1863         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
1864                           GRC_MODE_4X_NIC_SEND_RINGS |
1865                           GRC_MODE_NO_TX_PHDR_CSUM |
1866                           GRC_MODE_NO_RX_PHDR_CSUM);
1867         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
1868         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
1869         tp->grc_mode |= GRC_MODE_NO_RX_PHDR_CSUM;
1870
1871         tw32(GRC_MODE,
1872                 tp->grc_mode | 
1873                 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
1874
1875         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
1876         tw32(GRC_MISC_CFG,
1877              (65 << GRC_MISC_CFG_PRESCALAR_SHIFT));
1878
1879         /* Initialize MBUF/DESC pool. */
1880         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1881                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
1882                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
1883                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
1884                 else
1885                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
1886                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
1887                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
1888         }
1889         if (!(tp->tg3_flags & TG3_FLAG_JUMBO_ENABLE)) {
1890                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
1891                      tp->bufmgr_config.mbuf_read_dma_low_water);
1892                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
1893                      tp->bufmgr_config.mbuf_mac_rx_low_water);
1894                 tw32(BUFMGR_MB_HIGH_WATER,
1895                      tp->bufmgr_config.mbuf_high_water);
1896         } else {
1897                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
1898                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
1899                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
1900                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
1901                 tw32(BUFMGR_MB_HIGH_WATER,
1902                      tp->bufmgr_config.mbuf_high_water_jumbo);
1903         }
1904         tw32(BUFMGR_DMA_LOW_WATER,
1905              tp->bufmgr_config.dma_low_water);
1906         tw32(BUFMGR_DMA_HIGH_WATER,
1907              tp->bufmgr_config.dma_high_water);
1908
1909         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
1910         for (i = 0; i < 2000; i++) {
1911                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
1912                         break;
1913                 udelay(10);
1914         }
1915         if (i >= 2000) {
1916                 printf("tg3_setup_hw cannot enable BUFMGR\n");
1917                 return -ENODEV;
1918         }
1919
1920         tw32(FTQ_RESET, 0xffffffff);
1921         tw32(FTQ_RESET, 0x00000000);
1922         for (i = 0; i < 2000; i++) {
1923                 if (tr32(FTQ_RESET) == 0x00000000)
1924                         break;
1925                 udelay(10);
1926         }
1927         if (i >= 2000) {
1928                 printf("tg3_setup_hw cannot reset FTQ\n");
1929                 return -ENODEV;
1930         }
1931
1932         /* Initialize TG3_BDINFO's at:
1933          *  RCVDBDI_STD_BD:     standard eth size rx ring
1934          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
1935          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
1936          *
1937          * like so:
1938          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
1939          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
1940          *                              ring attribute flags
1941          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
1942          *
1943          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
1944          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
1945          *
1946          * ??? No space allocated for mini receive ring? :(
1947          *
1948          * The size of each ring is fixed in the firmware, but the location is
1949          * configurable.
1950          */
1951         {
1952                 static const uint32_t table_all[] = {
1953                         /* Setup replenish thresholds. */
1954                         RCVBDI_STD_THRESH, TG3_DEF_RX_RING_PENDING / 8,
1955
1956                         /* Etherboot lives below 4GB */
1957                         RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH, 0,
1958                         RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR, NIC_SRAM_RX_BUFFER_DESC,
1959                 };
1960                 static const uint32_t table_not_5705[] = {
1961                         /* Buffer maximum length */
1962                         RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT,
1963                         
1964                         /* Disable the mini frame rx ring */
1965                         RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,      BDINFO_FLAGS_DISABLED,
1966                         
1967                         /* Disable the jumbo frame rx ring */
1968                         RCVBDI_JUMBO_THRESH, 0,
1969                         RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS, BDINFO_FLAGS_DISABLED,
1970                         
1971                         
1972                 };
1973                 TG3_WRITE_SETTINGS(table_all);
1974                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW, 
1975                         virt_to_bus(tp->rx_std));
1976                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1977                         tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
1978                                 RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
1979                 } else {
1980                         TG3_WRITE_SETTINGS(table_not_5705);
1981                 }
1982         }
1983
1984         
1985         /* There is only one send ring on 5705, no need to explicitly
1986          * disable the others.
1987          */
1988         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
1989                 /* Clear out send RCB ring in SRAM. */
1990                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
1991                         tg3_write_mem(i + TG3_BDINFO_MAXLEN_FLAGS, BDINFO_FLAGS_DISABLED);
1992         }
1993
1994         tp->tx_prod = 0;
1995         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
1996         tw32_mailbox2(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
1997
1998         tg3_set_bdinfo(tp,
1999                 NIC_SRAM_SEND_RCB,
2000                 virt_to_bus(tp->tx_ring),
2001                 (TG3_TX_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
2002                 NIC_SRAM_TX_BUFFER_DESC);
2003
2004         /* There is only one receive return ring on 5705, no need to explicitly
2005          * disable the others.
2006          */
2007         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
2008                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK; i += TG3_BDINFO_SIZE) {
2009                         tg3_write_mem(i + TG3_BDINFO_MAXLEN_FLAGS,
2010                                 BDINFO_FLAGS_DISABLED);
2011                 }
2012         }
2013
2014         tp->rx_rcb_ptr = 0;
2015         tw32_mailbox2(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
2016
2017         tg3_set_bdinfo(tp,
2018                 NIC_SRAM_RCV_RET_RCB,
2019                 virt_to_bus(tp->rx_rcb),
2020                 (TG3_RX_RCB_RING_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT),
2021                 0);
2022
2023         tp->rx_std_ptr = TG3_DEF_RX_RING_PENDING;
2024         tw32_mailbox2(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
2025                      tp->rx_std_ptr);
2026
2027         tw32_mailbox2(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW, 0);
2028
2029         /* Initialize MAC address and backoff seed. */
2030         __tg3_set_mac_addr(tp);
2031
2032         /* Calculate RDMAC_MODE setting early, we need it to determine
2033          * the RCVLPC_STATE_ENABLE mask.
2034          */
2035         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
2036                 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
2037                 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
2038                 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
2039                 RDMAC_MODE_LNGREAD_ENAB);
2040         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
2041                 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
2042         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2043                 if (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
2044                         if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
2045                                 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
2046                                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
2047                         }
2048                 }
2049         }
2050
2051         /* Setup host coalescing engine. */
2052         tw32(HOSTCC_MODE, 0);
2053         for (i = 0; i < 2000; i++) {
2054                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
2055                         break;
2056                 udelay(10);
2057         }
2058
2059         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
2060                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
2061         tw32_carefully(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
2062
2063         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
2064         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
2065                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
2066                                        GRC_LCLCTRL_GPIO_OUTPUT1);
2067         tw32_carefully(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
2068
2069         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
2070         tr32(MAILBOX_INTERRUPT_0);
2071
2072         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
2073                 tw32_carefully(DMAC_MODE, DMAC_MODE_ENABLE);
2074         }
2075
2076         val = ( WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
2077                 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
2078                 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
2079                 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
2080                 WDMAC_MODE_LNGREAD_ENAB);
2081         if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) &&
2082                 ((tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) != 0) &&
2083                 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
2084                 val |= WDMAC_MODE_RX_ACCEL;
2085         }
2086         tw32_carefully(WDMAC_MODE, val);
2087
2088         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
2089                 val = tr32(TG3PCI_X_CAPS);
2090                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
2091                         val &= PCIX_CAPS_BURST_MASK;
2092                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
2093                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2094                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
2095                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
2096                         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
2097                                 val |= (tp->split_mode_max_reqs <<
2098                                         PCIX_CAPS_SPLIT_SHIFT);
2099                 }
2100                 tw32(TG3PCI_X_CAPS, val);
2101         }
2102
2103         tw32_carefully(RDMAC_MODE, rdmac_mode);
2104         {
2105                 static const uint32_t table_all[] = {
2106                         /* MTU + ethernet header + FCS + optional VLAN tag */
2107                         MAC_RX_MTU_SIZE, ETH_MAX_MTU + ETH_HLEN + 8,
2108                         
2109                         /* The slot time is changed by tg3_setup_phy if we
2110                          * run at gigabit with half duplex.
2111                          */
2112                         MAC_TX_LENGTHS, 
2113                         (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
2114                         (6 << TX_LENGTHS_IPG_SHIFT) |
2115                         (32 << TX_LENGTHS_SLOT_TIME_SHIFT),
2116                         
2117                         /* Receive rules. */
2118                         MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS,
2119                         RCVLPC_CONFIG, 0x0181,
2120                         
2121                         /* Receive/send statistics. */
2122                         RCVLPC_STATS_ENABLE, 0xffffff,
2123                         RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE,
2124                         SNDDATAI_STATSENAB, 0xffffff,
2125                         SNDDATAI_STATSCTRL, (SNDDATAI_SCTRL_ENABLE |SNDDATAI_SCTRL_FASTUPD),
2126                         
2127                         /* Host coalescing engine */
2128                         HOSTCC_RXCOL_TICKS, 0,
2129                         HOSTCC_TXCOL_TICKS, LOW_TXCOL_TICKS,
2130                         HOSTCC_RXMAX_FRAMES, 1,
2131                         HOSTCC_TXMAX_FRAMES, LOW_RXMAX_FRAMES,
2132                         HOSTCC_RXCOAL_MAXF_INT, 1,
2133                         HOSTCC_TXCOAL_MAXF_INT, 0,
2134                         
2135                         /* Status/statistics block address. */
2136                         /* Etherboot lives below 4GB, so HIGH == 0 */
2137                         HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, 0,
2138
2139                         /* No need to enable 32byte coalesce mode. */
2140                         HOSTCC_MODE, HOSTCC_MODE_ENABLE | 0,
2141                         
2142                         RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE,
2143                         RCVLPC_MODE, RCVLPC_MODE_ENABLE,
2144                         
2145                         RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE,
2146
2147                         SNDDATAC_MODE, SNDDATAC_MODE_ENABLE,
2148                         SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE,
2149                         RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB,
2150                         RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ,
2151                         SNDDATAI_MODE, SNDDATAI_MODE_ENABLE,
2152                         SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE,
2153                         SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE,
2154                         
2155                         /* Accept all multicast frames. */
2156                         MAC_HASH_REG_0, 0xffffffff,
2157                         MAC_HASH_REG_1, 0xffffffff,
2158                         MAC_HASH_REG_2, 0xffffffff,
2159                         MAC_HASH_REG_3, 0xffffffff,
2160                 };
2161                 static const uint32_t table_not_5705[] = {
2162                         /* Host coalescing engine */
2163                         HOSTCC_RXCOAL_TICK_INT, 0,
2164                         HOSTCC_TXCOAL_TICK_INT, 0,
2165
2166                         /* Status/statistics block address. */
2167                         /* Etherboot lives below 4GB, so HIGH == 0 */
2168                         HOSTCC_STAT_COAL_TICKS, DEFAULT_STAT_COAL_TICKS,
2169                         HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH, 0,
2170                         HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK,
2171                         HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK,
2172
2173                         RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE,
2174
2175                         MBFREE_MODE, MBFREE_MODE_ENABLE,
2176                 };
2177                 TG3_WRITE_SETTINGS(table_all);
2178                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
2179                         virt_to_bus(tp->hw_stats));
2180                 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
2181                         virt_to_bus(tp->hw_status));
2182                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
2183                         TG3_WRITE_SETTINGS(table_not_5705);
2184                 }
2185         }
2186
2187         tp->tx_mode = TX_MODE_ENABLE;
2188         tw32_carefully(MAC_TX_MODE, tp->tx_mode);
2189
2190         tp->rx_mode = RX_MODE_ENABLE;
2191         tw32_carefully(MAC_RX_MODE, tp->rx_mode);
2192
2193         tp->mi_mode = MAC_MI_MODE_BASE;
2194         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
2195
2196         tw32(MAC_LED_CTRL, 0);
2197         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
2198         if (tp->phy_id == PHY_ID_SERDES) {
2199                 tw32_carefully(MAC_RX_MODE, RX_MODE_RESET);
2200         }
2201         tp->rx_mode |= RX_MODE_KEEP_VLAN_TAG; /* drop tagged vlan packets */
2202         tw32_carefully(MAC_RX_MODE, tp->rx_mode);
2203
2204         if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
2205                 tw32(MAC_SERDES_CFG, 0x616000);
2206
2207         /* Prevent chip from dropping frames when flow control
2208          * is enabled.
2209          */
2210         tw32(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
2211         tr32(MAC_LOW_WMARK_MAX_RX_FRAME);
2212
2213         err = tg3_setup_phy(tp);
2214
2215         /* Ignore CRC stats */
2216
2217         /* Initialize receive rules. */
2218         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
2219         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
2220         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
2221         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
2222
2223         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
2224             || (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750))
2225                 limit = 8;
2226         else
2227                 limit = 16;
2228         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
2229                 limit -= 4;
2230         switch (limit) {
2231         case 16:        tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
2232         case 15:        tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
2233         case 14:        tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
2234         case 13:        tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
2235         case 12:        tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
2236         case 11:        tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
2237         case 10:        tw32(MAC_RCV_RULE_9,  0);  tw32(MAC_RCV_VALUE_9,  0);
2238         case 9:         tw32(MAC_RCV_RULE_8,  0);  tw32(MAC_RCV_VALUE_8,  0);
2239         case 8:         tw32(MAC_RCV_RULE_7,  0);  tw32(MAC_RCV_VALUE_7,  0);
2240         case 7:         tw32(MAC_RCV_RULE_6,  0);  tw32(MAC_RCV_VALUE_6,  0);
2241         case 6:         tw32(MAC_RCV_RULE_5,  0);  tw32(MAC_RCV_VALUE_5,  0);
2242         case 5:         tw32(MAC_RCV_RULE_4,  0);  tw32(MAC_RCV_VALUE_4,  0);
2243         case 4:         /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
2244         case 3:         /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
2245         case 2:
2246         case 1:
2247         default:
2248                 break;
2249         };
2250
2251         return err;
2252 }
2253
2254
2255
2256 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
2257 static void tg3_nvram_init(struct tg3 *tp)
2258 {
2259         tw32(GRC_EEPROM_ADDR,
2260              (EEPROM_ADDR_FSM_RESET |
2261               (EEPROM_DEFAULT_CLOCK_PERIOD <<
2262                EEPROM_ADDR_CLKPERD_SHIFT)));
2263
2264         mdelay(1);
2265
2266         /* Enable seeprom accesses. */
2267         tw32_carefully(GRC_LOCAL_CTRL,
2268                 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
2269
2270         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2271             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2272                 uint32_t nvcfg1 = tr32(NVRAM_CFG1);
2273
2274                 tp->tg3_flags |= TG3_FLAG_NVRAM;
2275                 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
2276                         if (nvcfg1 & NVRAM_CFG1_BUFFERED_MODE)
2277                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
2278                 } else {
2279                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
2280                         tw32(NVRAM_CFG1, nvcfg1);
2281                 }
2282
2283         } else {
2284                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
2285         }
2286 }
2287
2288
2289 static int tg3_nvram_read_using_eeprom(
2290         struct tg3 *tp __unused, uint32_t offset, uint32_t *val)
2291 {
2292         uint32_t tmp;
2293         int i;
2294
2295         if (offset > EEPROM_ADDR_ADDR_MASK ||
2296                 (offset % 4) != 0) {
2297                 return -EINVAL;
2298         }
2299
2300         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2301                                         EEPROM_ADDR_DEVID_MASK |
2302                                         EEPROM_ADDR_READ);
2303         tw32(GRC_EEPROM_ADDR,
2304              tmp |
2305              (0 << EEPROM_ADDR_DEVID_SHIFT) |
2306              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2307               EEPROM_ADDR_ADDR_MASK) |
2308              EEPROM_ADDR_READ | EEPROM_ADDR_START);
2309
2310         for (i = 0; i < 10000; i++) {
2311                 tmp = tr32(GRC_EEPROM_ADDR);
2312
2313                 if (tmp & EEPROM_ADDR_COMPLETE)
2314                         break;
2315                 udelay(100);
2316         }
2317         if (!(tmp & EEPROM_ADDR_COMPLETE)) {
2318                 return -EBUSY;
2319         }
2320
2321         *val = tr32(GRC_EEPROM_DATA);
2322         return 0;
2323 }
2324
2325 static int tg3_nvram_read(struct tg3 *tp, uint32_t offset, uint32_t *val)
2326 {
2327         int i, saw_done_clear;
2328
2329         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2330                 return tg3_nvram_read_using_eeprom(tp, offset, val);
2331
2332         if (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED)
2333                 offset = ((offset / NVRAM_BUFFERED_PAGE_SIZE) <<
2334                           NVRAM_BUFFERED_PAGE_POS) +
2335                         (offset % NVRAM_BUFFERED_PAGE_SIZE);
2336
2337         if (offset > NVRAM_ADDR_MSK)
2338                 return -EINVAL;
2339
2340         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2341         for (i = 0; i < 1000; i++) {
2342                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2343                         break;
2344                 udelay(20);
2345         }
2346
2347         tw32(NVRAM_ADDR, offset);
2348         tw32(NVRAM_CMD,
2349              NVRAM_CMD_RD | NVRAM_CMD_GO |
2350              NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2351
2352         /* Wait for done bit to clear then set again. */
2353         saw_done_clear = 0;
2354         for (i = 0; i < 1000; i++) {
2355                 udelay(10);
2356                 if (!saw_done_clear &&
2357                     !(tr32(NVRAM_CMD) & NVRAM_CMD_DONE))
2358                         saw_done_clear = 1;
2359                 else if (saw_done_clear &&
2360                          (tr32(NVRAM_CMD) & NVRAM_CMD_DONE))
2361                         break;
2362         }
2363         if (i >= 1000) {
2364                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2365                 return -EBUSY;
2366         }
2367
2368         *val = bswap_32(tr32(NVRAM_RDDATA));
2369         tw32(NVRAM_SWARB, 0x20);
2370
2371         return 0;
2372 }
2373
2374 struct subsys_tbl_ent {
2375         uint16_t subsys_vendor, subsys_devid;
2376         uint32_t phy_id;
2377 };
2378
2379 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
2380         /* Broadcom boards. */
2381         { 0x14e4, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
2382         { 0x14e4, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
2383         { 0x14e4, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
2384         { 0x14e4, 0x0003, PHY_ID_SERDES  }, /* BCM95700A9 */
2385         { 0x14e4, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
2386         { 0x14e4, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
2387         { 0x14e4, 0x0007, PHY_ID_SERDES  }, /* BCM95701A7 */
2388         { 0x14e4, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
2389         { 0x14e4, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
2390         { 0x14e4, 0x0009, PHY_ID_BCM5701 }, /* BCM95703Ax1 */
2391         { 0x14e4, 0x8009, PHY_ID_BCM5701 }, /* BCM95703Ax2 */
2392
2393         /* 3com boards. */
2394         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
2395         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
2396         /* { PCI_VENDOR_ID_3COM, 0x1002, PHY_ID_XXX },     3C996CT */
2397         /* { PCI_VENDOR_ID_3COM, 0x1003, PHY_ID_XXX },     3C997T */
2398         { PCI_VENDOR_ID_3COM, 0x1004, PHY_ID_SERDES  }, /* 3C996SX */
2399         /* { PCI_VENDOR_ID_3COM, 0x1005, PHY_ID_XXX },     3C997SZ */
2400         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
2401         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
2402
2403         /* DELL boards. */
2404         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
2405         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
2406         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
2407         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
2408         { PCI_VENDOR_ID_DELL, 0x0179, PHY_ID_BCM5751 }, /* EtherXpress */
2409
2410         /* Compaq boards. */
2411         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
2412         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
2413         { PCI_VENDOR_ID_COMPAQ, 0x007d, PHY_ID_SERDES  }, /* CHANGELING */
2414         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
2415         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }  /* NC7780_2 */
2416 };
2417
2418 static int tg3_phy_probe(struct tg3 *tp)
2419 {
2420         uint32_t eeprom_phy_id, hw_phy_id_1, hw_phy_id_2;
2421         uint32_t hw_phy_id, hw_phy_id_masked;
2422         enum phy_led_mode eeprom_led_mode;
2423         uint32_t val;
2424         unsigned i;
2425         int eeprom_signature_found, err;
2426
2427         tp->phy_id = PHY_ID_INVALID;
2428
2429         for (i = 0; i < sizeof(subsys_id_to_phy_id)/sizeof(subsys_id_to_phy_id[0]); i++) {
2430                 if ((subsys_id_to_phy_id[i].subsys_vendor == tp->subsystem_vendor) &&
2431                         (subsys_id_to_phy_id[i].subsys_devid == tp->subsystem_device)) {
2432                         tp->phy_id = subsys_id_to_phy_id[i].phy_id;
2433                         break;
2434                 }
2435         }
2436
2437         eeprom_phy_id = PHY_ID_INVALID;
2438         eeprom_led_mode = led_mode_auto;
2439         eeprom_signature_found = 0;
2440         tg3_read_mem(NIC_SRAM_DATA_SIG, &val);
2441         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
2442                 uint32_t nic_cfg;
2443
2444                 tg3_read_mem(NIC_SRAM_DATA_CFG, &nic_cfg);
2445                 tp->nic_sram_data_cfg = nic_cfg;
2446
2447                 eeprom_signature_found = 1;
2448
2449                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
2450                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER) {
2451                         eeprom_phy_id = PHY_ID_SERDES;
2452                 } else {
2453                         uint32_t nic_phy_id;
2454
2455                         tg3_read_mem(NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
2456                         if (nic_phy_id != 0) {
2457                                 uint32_t id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
2458                                 uint32_t id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
2459
2460                                 eeprom_phy_id  = (id1 >> 16) << 10;
2461                                 eeprom_phy_id |= (id2 & 0xfc00) << 16;
2462                                 eeprom_phy_id |= (id2 & 0x03ff) <<  0;
2463                         }
2464                 }
2465
2466                 switch (nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK) {
2467                 case NIC_SRAM_DATA_CFG_LED_TRIPLE_SPD:
2468                         eeprom_led_mode = led_mode_three_link;
2469                         break;
2470
2471                 case NIC_SRAM_DATA_CFG_LED_LINK_SPD:
2472                         eeprom_led_mode = led_mode_link10;
2473                         break;
2474
2475                 default:
2476                         eeprom_led_mode = led_mode_auto;
2477                         break;
2478                 };
2479                 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
2480                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
2481                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) &&
2482                         (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP)) {
2483                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
2484                 }
2485
2486                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE)
2487                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
2488                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
2489                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
2490         }
2491
2492         /* Now read the physical PHY_ID from the chip and verify
2493          * that it is sane.  If it doesn't look good, we fall back
2494          * to either the hard-coded table based PHY_ID and failing
2495          * that the value found in the eeprom area.
2496          */
2497         err  = tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
2498         err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
2499
2500         hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
2501         hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
2502         hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
2503
2504         hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
2505
2506         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
2507                 tp->phy_id = hw_phy_id;
2508         } else {
2509                 /* phy_id currently holds the value found in the
2510                  * subsys_id_to_phy_id[] table or PHY_ID_INVALID
2511                  * if a match was not found there.
2512                  */
2513                 if (tp->phy_id == PHY_ID_INVALID) {
2514                         if (!eeprom_signature_found ||
2515                             !KNOWN_PHY_ID(eeprom_phy_id & PHY_ID_MASK))
2516                                 return -ENODEV;
2517                         tp->phy_id = eeprom_phy_id;
2518                 }
2519         }
2520
2521         err = tg3_phy_reset(tp);
2522         if (err)
2523                 return err;
2524
2525         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2526             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
2527                 uint32_t mii_tg3_ctrl;
2528                 
2529                 /* These chips, when reset, only advertise 10Mb
2530                  * capabilities.  Fix that.
2531                  */
2532                 err  = tg3_writephy(tp, MII_ADVERTISE,
2533                                     (ADVERTISE_CSMA |
2534                                      ADVERTISE_PAUSE_CAP |
2535                                      ADVERTISE_10HALF |
2536                                      ADVERTISE_10FULL |
2537                                      ADVERTISE_100HALF |
2538                                      ADVERTISE_100FULL));
2539                 mii_tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
2540                                 MII_TG3_CTRL_ADV_1000_FULL |
2541                                 MII_TG3_CTRL_AS_MASTER |
2542                                 MII_TG3_CTRL_ENABLE_AS_MASTER);
2543                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2544                         mii_tg3_ctrl = 0;
2545
2546                 err |= tg3_writephy(tp, MII_TG3_CTRL, mii_tg3_ctrl);
2547                 err |= tg3_writephy(tp, MII_BMCR,
2548                                     (BMCR_ANRESTART | BMCR_ANENABLE));
2549         }
2550
2551         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
2552                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
2553                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2554                 tg3_writedsp(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
2555         }
2556
2557         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2558                 tg3_writephy(tp, 0x1c, 0x8d68);
2559                 tg3_writephy(tp, 0x1c, 0x8d68);
2560         }
2561
2562         /* Enable Ethernet@WireSpeed */
2563         tg3_phy_set_wirespeed(tp);
2564
2565         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
2566                 err = tg3_init_5401phy_dsp(tp);
2567         }
2568
2569         /* Determine the PHY led mode. 
2570          * Be careful if this gets set wrong it can result in an inability to 
2571          * establish a link.
2572          */
2573         if (tp->phy_id == PHY_ID_SERDES) {
2574                 tp->led_mode = led_mode_three_link;
2575         }
2576         else if (tp->subsystem_vendor == PCI_VENDOR_ID_DELL) {
2577                 tp->led_mode = led_mode_link10;
2578         } else {
2579                 tp->led_mode = led_mode_three_link;
2580                 if (eeprom_signature_found &&
2581                     eeprom_led_mode != led_mode_auto)
2582                         tp->led_mode = eeprom_led_mode;
2583         }
2584
2585         if (tp->phy_id == PHY_ID_SERDES)
2586                 tp->link_config.advertising =
2587                         (ADVERTISED_1000baseT_Half |
2588                          ADVERTISED_1000baseT_Full |
2589                          ADVERTISED_Autoneg |
2590                          ADVERTISED_FIBRE);
2591         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2592                 tp->link_config.advertising &=
2593                         ~(ADVERTISED_1000baseT_Half |
2594                           ADVERTISED_1000baseT_Full);
2595
2596         return err;
2597 }
2598
2599 #if SUPPORT_PARTNO_STR
2600 static void tg3_read_partno(struct tg3 *tp)
2601 {
2602         unsigned char vpd_data[256];
2603         int i;
2604
2605         for (i = 0; i < 256; i += 4) {
2606                 uint32_t tmp;
2607
2608                 if (tg3_nvram_read(tp, 0x100 + i, &tmp))
2609                         goto out_not_found;
2610
2611                 vpd_data[i + 0] = ((tmp >>  0) & 0xff);
2612                 vpd_data[i + 1] = ((tmp >>  8) & 0xff);
2613                 vpd_data[i + 2] = ((tmp >> 16) & 0xff);
2614                 vpd_data[i + 3] = ((tmp >> 24) & 0xff);
2615         }
2616
2617         /* Now parse and find the part number. */
2618         for (i = 0; i < 256; ) {
2619                 unsigned char val = vpd_data[i];
2620                 int block_end;
2621
2622                 if (val == 0x82 || val == 0x91) {
2623                         i = (i + 3 +
2624                              (vpd_data[i + 1] +
2625                               (vpd_data[i + 2] << 8)));
2626                         continue;
2627                 }
2628
2629                 if (val != 0x90)
2630                         goto out_not_found;
2631
2632                 block_end = (i + 3 +
2633                              (vpd_data[i + 1] +
2634                               (vpd_data[i + 2] << 8)));
2635                 i += 3;
2636                 while (i < block_end) {
2637                         if (vpd_data[i + 0] == 'P' &&
2638                             vpd_data[i + 1] == 'N') {
2639                                 int partno_len = vpd_data[i + 2];
2640
2641                                 if (partno_len > 24)
2642                                         goto out_not_found;
2643
2644                                 memcpy(tp->board_part_number,
2645                                        &vpd_data[i + 3],
2646                                        partno_len);
2647
2648                                 /* Success. */
2649                                 return;
2650                         }
2651                 }
2652
2653                 /* Part number not found. */
2654                 goto out_not_found;
2655         }
2656
2657 out_not_found:
2658         memcpy(tp->board_part_number, "none", sizeof("none"));
2659 }
2660 #else
2661 #define tg3_read_partno(TP) ((TP)->board_part_number[0] = '\0')
2662 #endif
2663
2664 static int tg3_get_invariants(struct tg3 *tp)
2665 {
2666         uint32_t misc_ctrl_reg;
2667         uint32_t pci_state_reg, grc_misc_cfg;
2668         uint16_t pci_cmd;
2669         uint8_t  pci_latency;
2670         uint32_t val ;
2671         int err;
2672
2673         /* Read the subsystem vendor and device ids */
2674         pci_read_config_word(tp->pdev, PCI_SUBSYSTEM_VENDOR_ID, &tp->subsystem_vendor);
2675         pci_read_config_word(tp->pdev, PCI_SUBSYSTEM_ID, &tp->subsystem_device);
2676
2677         /* The sun_5704 code needs infrastructure etherboot does have
2678          * ignore it for now.
2679          */
2680
2681         /* If we have an AMD 762 or Intel ICH/ICH0 chipset, write
2682          * reordering to the mailbox registers done by the host
2683          * controller can cause major troubles.  We read back from
2684          * every mailbox register write to force the writes to be
2685          * posted to the chip in order.
2686          *
2687          * TG3_FLAG_MBOX_WRITE_REORDER has been forced on.
2688          */
2689
2690         /* Force memory write invalidate off.  If we leave it on,
2691          * then on 5700_BX chips we have to enable a workaround.
2692          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundry
2693          * to match the cacheline size.  The Broadcom driver have this
2694          * workaround but turns MWI off all the times so never uses
2695          * it.  This seems to suggest that the workaround is insufficient.
2696          */
2697         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
2698         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
2699         /* Also, force SERR#/PERR# in PCI command. */
2700         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
2701         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
2702
2703         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
2704          * has the register indirect write enable bit set before
2705          * we try to access any of the MMIO registers.  It is also
2706          * critical that the PCI-X hw workaround situation is decided
2707          * before that as well.
2708          */
2709         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL, &misc_ctrl_reg);
2710
2711         tp->pci_chip_rev_id = (misc_ctrl_reg >> MISC_HOST_CTRL_CHIPREV_SHIFT);
2712
2713         /* Initialize misc host control in PCI block. */
2714         tp->misc_host_ctrl |= (misc_ctrl_reg &
2715                                MISC_HOST_CTRL_CHIPREV);
2716         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
2717                                tp->misc_host_ctrl);
2718
2719         pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER, &pci_latency);
2720         if (pci_latency < 64) {
2721                 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER, 64);
2722         }
2723
2724         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &pci_state_reg);
2725
2726         /* If this is a 5700 BX chipset, and we are in PCI-X
2727          * mode, enable register write workaround.
2728          *
2729          * The workaround is to use indirect register accesses
2730          * for all chip writes not to mailbox registers.
2731          *
2732          * In etherboot to simplify things we just always use this work around.
2733          */
2734         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
2735                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
2736         }
2737         /* Back to back register writes can cause problems on the 5701,
2738          * the workaround is to read back all reg writes except those to
2739          * mailbox regs.
2740          * In etherboot we always use indirect register accesses so
2741          * we don't see this.
2742          */
2743
2744         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
2745                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
2746         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
2747                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
2748
2749         /* Chip-specific fixup from Broadcom driver */
2750         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
2751             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
2752                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
2753                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
2754         }
2755
2756         /* determine if it is PCIE system */
2757         // Alf : I have no idea what this is about...
2758         // But it's definitely usefull
2759         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
2760           val = tr32(TG3PCI_MSI_CAP_ID) ;
2761           if (((val >> 8) & 0xff) == T3_PCIE_CAPABILITY_ID_REG) {
2762             val = tr32(T3_PCIE_CAPABILITY_ID_REG) ;
2763             if ((val & 0xff) == T3_PCIE_CAPABILITY_ID) {
2764               tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS ;
2765             }
2766           }
2767         }
2768
2769         /* Force the chip into D0. */
2770         tg3_set_power_state_0(tp);
2771
2772         /* Etherboot does not ask the tg3 to do checksums */
2773         /* Etherboot does not ask the tg3 to do jumbo frames */
2774         /* Ehterboot does not ask the tg3 to use WakeOnLan. */
2775
2776         /* A few boards don't want Ethernet@WireSpeed phy feature */
2777         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
2778             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
2779                 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2780                         (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
2781                         (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1))) {
2782                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
2783         }
2784
2785         /* Avoid tagged irq status etherboot does not use irqs */
2786
2787         /* Only 5701 and later support tagged irq status mode.
2788          * Also, 5788 chips cannot use tagged irq status.
2789          *
2790          * However, since etherboot does not use irqs avoid tagged irqs
2791          * status  because the interrupt condition is more difficult to
2792          * fully clear in that mode.
2793          */
2794         
2795         /* Since some 5700_AX && 5700_BX have problems with 32BYTE
2796          * coalesce_mode, and the rest work fine anything set.
2797          * Don't enable HOST_CC_MODE_32BYTE in etherboot.
2798          */
2799
2800         /* Initialize MAC MI mode, polling disabled. */
2801         tw32_carefully(MAC_MI_MODE, tp->mi_mode);
2802
2803         /* Initialize data/descriptor byte/word swapping. */
2804         tw32(GRC_MODE, tp->grc_mode);
2805
2806         tg3_switch_clocks(tp);
2807
2808         /* Clear this out for sanity. */
2809         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
2810
2811         /* Etherboot does not need to check if the PCIX_TARGET_HWBUG
2812          * is needed.  It always uses it.
2813          */
2814         
2815         udelay(50);
2816         tg3_nvram_init(tp);
2817
2818         /* The TX descriptors will reside in main memory.
2819          */
2820
2821         /* See which board we are using.
2822          */
2823         grc_misc_cfg = tr32(GRC_MISC_CFG);
2824         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
2825
2826         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
2827             grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
2828                 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
2829                 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
2830         }
2831
2832         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
2833             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
2834              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
2835                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
2836
2837 #define PCI_DEVICE_ID_TIGON3_5901       0x170d
2838 #define PCI_DEVICE_ID_TIGON3_5901_2     0x170e
2839
2840         /* these are limited to 10/100 only */
2841         if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) &&
2842                     ((grc_misc_cfg == 0x8000) || (grc_misc_cfg == 0x4000))) ||
2843                 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
2844                         (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM) &&
2845                         ((tp->pdev->dev_id == PCI_DEVICE_ID_TIGON3_5901) ||
2846                                 (tp->pdev->dev_id == PCI_DEVICE_ID_TIGON3_5901_2)))) {
2847                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
2848         }
2849
2850         err = tg3_phy_probe(tp);
2851         if (err) {
2852                 printf("phy probe failed, err %d\n", err);
2853         }
2854
2855         tg3_read_partno(tp);
2856
2857
2858         /* 5700 BX chips need to have their TX producer index mailboxes
2859          * written twice to workaround a bug.
2860          * In etherboot we do this unconditionally to simplify things.
2861          */
2862
2863         /* 5700 chips can get confused if TX buffers straddle the
2864          * 4GB address boundary in some cases.
2865          * 
2866          * In etherboot we can ignore the problem as etherboot lives below 4GB.
2867          */
2868
2869         /* In etherboot wake-on-lan is unconditionally disabled */
2870         return err;
2871 }
2872
2873 static int  tg3_get_device_address(struct tg3 *tp)
2874 {
2875         struct nic *nic = tp->nic;
2876         uint32_t hi, lo, mac_offset;
2877
2878         if (PCI_FUNC(tp->pdev->devfn) == 0)
2879                 mac_offset = 0x7c;
2880         else
2881                 mac_offset = 0xcc;
2882
2883         /* First try to get it from MAC address mailbox. */
2884         tg3_read_mem(NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
2885         if ((hi >> 16) == 0x484b) {
2886                 nic->node_addr[0] = (hi >>  8) & 0xff;
2887                 nic->node_addr[1] = (hi >>  0) & 0xff;
2888
2889                 tg3_read_mem(NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
2890                 nic->node_addr[2] = (lo >> 24) & 0xff;
2891                 nic->node_addr[3] = (lo >> 16) & 0xff;
2892                 nic->node_addr[4] = (lo >>  8) & 0xff;
2893                 nic->node_addr[5] = (lo >>  0) & 0xff;
2894         }
2895         /* Next, try NVRAM. */
2896         else if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
2897                  !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
2898                 nic->node_addr[0] = ((hi >> 16) & 0xff);
2899                 nic->node_addr[1] = ((hi >> 24) & 0xff);
2900                 nic->node_addr[2] = ((lo >>  0) & 0xff);
2901                 nic->node_addr[3] = ((lo >>  8) & 0xff);
2902                 nic->node_addr[4] = ((lo >> 16) & 0xff);
2903                 nic->node_addr[5] = ((lo >> 24) & 0xff);
2904         }
2905         /* Finally just fetch it out of the MAC control regs. */
2906         else {
2907                 hi = tr32(MAC_ADDR_0_HIGH);
2908                 lo = tr32(MAC_ADDR_0_LOW);
2909
2910                 nic->node_addr[5] = lo & 0xff;
2911                 nic->node_addr[4] = (lo >> 8) & 0xff;
2912                 nic->node_addr[3] = (lo >> 16) & 0xff;
2913                 nic->node_addr[2] = (lo >> 24) & 0xff;
2914                 nic->node_addr[1] = hi & 0xff;
2915                 nic->node_addr[0] = (hi >> 8) & 0xff;
2916         }
2917
2918         return 0;
2919 }
2920
2921
2922 static int tg3_setup_dma(struct tg3 *tp)
2923 {
2924         tw32(TG3PCI_CLOCK_CTRL, 0);
2925
2926         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) == 0) {
2927                 tp->dma_rwctrl =
2928                         (0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
2929                         (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
2930                         (0x7 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
2931                         (0x7 << DMA_RWCTRL_READ_WATER_SHIFT) |
2932                         (0x0f << DMA_RWCTRL_MIN_DMA_SHIFT);
2933                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
2934                         tp->dma_rwctrl &= ~(DMA_RWCTRL_MIN_DMA << DMA_RWCTRL_MIN_DMA_SHIFT);
2935                 }
2936         } else {
2937                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
2938                         tp->dma_rwctrl =
2939                                 (0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
2940                                 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
2941                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
2942                                 (0x7 << DMA_RWCTRL_READ_WATER_SHIFT) |
2943                                 (0x00 << DMA_RWCTRL_MIN_DMA_SHIFT);
2944                 else
2945                         tp->dma_rwctrl =
2946                                 (0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
2947                                 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT) |
2948                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
2949                                 (0x3 << DMA_RWCTRL_READ_WATER_SHIFT) |
2950                                 (0x0f << DMA_RWCTRL_MIN_DMA_SHIFT);
2951
2952                 /* Wheee, some more chip bugs... */
2953                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
2954                         (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)) {
2955                         uint32_t ccval = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
2956
2957                         if ((ccval == 0x6) || (ccval == 0x7)) {
2958                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
2959                         }
2960                 }
2961         }
2962
2963         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) ||
2964                 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)) {
2965                 tp->dma_rwctrl &= ~(DMA_RWCTRL_MIN_DMA << DMA_RWCTRL_MIN_DMA_SHIFT);
2966         }
2967
2968         /*
2969           Alf : Tried that, but it does not work. Should be this way though :-(
2970         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
2971           tp->dma_rwctrl |= 0x001f0000;
2972         }
2973         */
2974         tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
2975
2976         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
2977
2978         return 0;
2979 }
2980
2981 static void tg3_init_link_config(struct tg3 *tp)
2982 {
2983         tp->link_config.advertising =
2984                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2985                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2986                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
2987                  ADVERTISED_Autoneg | ADVERTISED_MII);
2988         tp->carrier_ok = 0;
2989         tp->link_config.active_speed = SPEED_INVALID;
2990         tp->link_config.active_duplex = DUPLEX_INVALID;
2991 }
2992
2993
2994 #if SUPPORT_PHY_STR
2995 static const char * tg3_phy_string(struct tg3 *tp)
2996 {
2997         switch (tp->phy_id & PHY_ID_MASK) {
2998         case PHY_ID_BCM5400:    return "5400";
2999         case PHY_ID_BCM5401:    return "5401";
3000         case PHY_ID_BCM5411:    return "5411";
3001         case PHY_ID_BCM5701:    return "5701";
3002         case PHY_ID_BCM5703:    return "5703";
3003         case PHY_ID_BCM5704:    return "5704";
3004         case PHY_ID_BCM5705:    return "5705";
3005         case PHY_ID_BCM5750:    return "5750";
3006         case PHY_ID_BCM5751:    return "5751"; 
3007         case PHY_ID_BCM8002:    return "8002/serdes";
3008         case PHY_ID_SERDES:     return "serdes";
3009         default:                return "unknown";
3010         };
3011 }
3012 #else
3013 #define tg3_phy_string(TP) "?"
3014 #endif
3015
3016
3017 static void tg3_poll_link(struct tg3 *tp)
3018 {
3019         uint32_t mac_stat;
3020
3021         mac_stat = tr32(MAC_STATUS);
3022         if (tp->phy_id == PHY_ID_SERDES) {
3023                 if (tp->carrier_ok?
3024                         (mac_stat & MAC_STATUS_LNKSTATE_CHANGED):
3025                         (mac_stat & MAC_STATUS_PCS_SYNCED)) {
3026                         tw32_carefully(MAC_MODE, tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK);
3027                         tw32_carefully(MAC_MODE, tp->mac_mode);
3028
3029                         tg3_setup_phy(tp);
3030                 }
3031         }
3032         else {
3033                 if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED) {
3034                         tg3_setup_phy(tp);
3035                 }
3036         }
3037 }
3038
3039 /**************************************************************************
3040 POLL - Wait for a frame
3041 ***************************************************************************/
3042 static void tg3_ack_irqs(struct tg3 *tp)
3043 {
3044         if (tp->hw_status->status & SD_STATUS_UPDATED) {
3045                 /*
3046                  * writing any value to intr-mbox-0 clears PCI INTA# and
3047                  * chip-internal interrupt pending events.
3048                  * writing non-zero to intr-mbox-0 additional tells the
3049                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3050                  * event coalescing.
3051                  */
3052                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 
3053                         0x00000001);
3054                 /*
3055                  * Flush PCI write.  This also guarantees that our
3056                  * status block has been flushed to host memory.
3057                  */
3058                 tr32(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW);
3059                 tp->hw_status->status &= ~SD_STATUS_UPDATED;
3060         }
3061 }
3062
3063 static int tg3_poll(struct nic *nic, int retrieve)
3064 {
3065         /* return true if there's an ethernet packet ready to read */
3066         /* nic->packet should contain data on return */
3067         /* nic->packetlen should contain length of data */
3068
3069         struct tg3 *tp = &tg3;
3070         int result;
3071
3072         result = 0;
3073
3074         if ( (tp->hw_status->idx[0].rx_producer != tp->rx_rcb_ptr) && !retrieve ) 
3075           return 1;
3076
3077         tg3_ack_irqs(tp);
3078
3079         if (tp->hw_status->idx[0].rx_producer != tp->rx_rcb_ptr) {
3080                 struct tg3_rx_buffer_desc *desc;
3081                 unsigned int len;
3082                 desc = &tp->rx_rcb[tp->rx_rcb_ptr];
3083                 if ((desc->opaque & RXD_OPAQUE_RING_MASK) == RXD_OPAQUE_RING_STD) {
3084                         len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3085                         
3086                         nic->packetlen = len;
3087                         memcpy(nic->packet, bus_to_virt(desc->addr_lo), len);
3088                         result = 1;
3089                 }
3090                 tp->rx_rcb_ptr = (tp->rx_rcb_ptr + 1) % TG3_RX_RCB_RING_SIZE;
3091                 
3092                 /* ACK the status ring */
3093                 tw32_mailbox2(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, tp->rx_rcb_ptr);
3094
3095                 /* Refill RX ring. */
3096                 if (result) {
3097                         tp->rx_std_ptr = (tp->rx_std_ptr + 1) % TG3_RX_RING_SIZE;
3098                         tw32_mailbox2(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW, tp->rx_std_ptr);
3099                 }
3100         }
3101         tg3_poll_link(tp);
3102         return result;
3103 }
3104
3105 /**************************************************************************
3106 TRANSMIT - Transmit a frame
3107 ***************************************************************************/
3108 #if 0
3109 static void tg3_set_txd(struct tg3 *tp, int entry,
3110         dma_addr_t mapping, int len, uint32_t flags,
3111         uint32_t mss_and_is_end)
3112 {
3113         struct tg3_tx_buffer_desc *txd =  &tp->tx_ring[entry];
3114         int is_end = (mss_and_is_end & 0x1);
3115         if (is_end) {
3116                 flags |= TXD_FLAG_END;
3117         }
3118
3119         txd->addr_hi   = 0;
3120         txd->addr_lo   = mapping & 0xffffffff;
3121         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3122         txd->vlan_tag  = 0 << TXD_VLAN_TAG_SHIFT;
3123 }
3124 #endif
3125
3126 static void tg3_transmit(struct nic *nic, const char *dst_addr,
3127         unsigned int type, unsigned int size, const char *packet)
3128 {
3129         static struct eth_frame {
3130                 uint8_t  dst_addr[ETH_ALEN];
3131                 uint8_t  src_addr[ETH_ALEN];
3132                 uint16_t type;
3133                 uint8_t  data [ETH_FRAME_LEN - ETH_HLEN];
3134         } frame[2];
3135         static int frame_idx;
3136         
3137         /* send the packet to destination */
3138         struct tg3_tx_buffer_desc *txd;
3139         struct tg3 *tp;
3140         uint32_t entry;
3141         int i;
3142
3143         /* Wait until there is a free packet frame */
3144         tp = &tg3;
3145         i = 0;
3146         entry = tp->tx_prod;
3147         while((tp->hw_status->idx[0].tx_consumer != entry) &&
3148                 (tp->hw_status->idx[0].tx_consumer != PREV_TX(entry))) {
3149                 mdelay(10);     /* give the nick a chance */
3150                 poll_interruptions();
3151                 if (++i > 500) { /* timeout 5s for transmit */
3152                         printf("transmit timed out\n");
3153                         tg3_halt(tp);
3154                         tg3_setup_hw(tp);
3155                         return;
3156                 }
3157         }
3158         if (i != 0) {
3159                 printf("#");
3160         }
3161         
3162         /* Copy the packet to the our local buffer */
3163         memcpy(&frame[frame_idx].dst_addr, dst_addr, ETH_ALEN);
3164         memcpy(&frame[frame_idx].src_addr, nic->node_addr, ETH_ALEN);
3165         frame[frame_idx].type = htons(type);
3166         memset(&frame[frame_idx].data, 0, sizeof(frame[frame_idx].data));
3167         memcpy(&frame[frame_idx].data, packet, size);
3168
3169         /* Setup the ring buffer entry to transmit */
3170         txd            = &tp->tx_ring[entry];
3171         txd->addr_hi   = 0; /* Etherboot runs under 4GB */
3172         txd->addr_lo   = virt_to_bus(&frame[frame_idx]);
3173         txd->len_flags = ((size + ETH_HLEN) << TXD_LEN_SHIFT) | TXD_FLAG_END;
3174         txd->vlan_tag  = 0 << TXD_VLAN_TAG_SHIFT;
3175
3176         /* Advance to the next entry */
3177         entry = NEXT_TX(entry);
3178         frame_idx ^= 1;
3179
3180         /* Packets are ready, update Tx producer idx local and on card */
3181         tw32_mailbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3182         tw32_mailbox2((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3183         tp->tx_prod = entry;
3184 }
3185
3186 /**************************************************************************
3187 DISABLE - Turn off ethernet interface
3188 ***************************************************************************/
3189 static void tg3_disable(struct dev *dev __unused)
3190 {
3191         struct tg3 *tp = &tg3;
3192         /* put the card in its initial state */
3193         /* This function serves 3 purposes.
3194          * This disables DMA and interrupts so we don't receive
3195          *  unexpected packets or interrupts from the card after
3196          *  etherboot has finished. 
3197          * This frees resources so etherboot may use
3198          *  this driver on another interface
3199          * This allows etherboot to reinitialize the interface
3200          *  if something is something goes wrong.
3201          */
3202         tg3_halt(tp);
3203         tp->tg3_flags &= ~(TG3_FLAG_INIT_COMPLETE|TG3_FLAG_GOT_SERDES_FLOWCTL);
3204         tp->carrier_ok = 0;
3205         iounmap((void *)tp->regs);
3206 }
3207
3208 /**************************************************************************
3209 IRQ - Enable, Disable, or Force interrupts
3210 ***************************************************************************/
3211 static void tg3_irq(struct nic *nic __unused, irq_action_t action __unused)
3212 {
3213   switch ( action ) {
3214   case DISABLE :
3215     break;
3216   case ENABLE :
3217     break;
3218   case FORCE :
3219     break;
3220   }
3221 }
3222
3223 /**************************************************************************
3224 PROBE - Look for an adapter, this routine's visible to the outside
3225 You should omit the last argument struct pci_device * for a non-PCI NIC
3226 ***************************************************************************/
3227 static int tg3_probe(struct dev *dev, struct pci_device *pdev)
3228 {
3229         struct nic *nic = (struct nic *)dev;
3230         struct tg3 *tp = &tg3;
3231         unsigned long tg3reg_base, tg3reg_len;
3232         int i, err, pm_cap;
3233
3234         if (pdev == 0)
3235                 return 0;
3236
3237         memset(tp, 0, sizeof(*tp));
3238
3239         adjust_pci_device(pdev);
3240
3241         nic->irqno  = 0;
3242         nic->ioaddr = pdev->ioaddr & ~3;
3243
3244         /* Find power-management capability. */
3245         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
3246         if (pm_cap == 0) {
3247                 printf("Cannot find PowerManagement capability, aborting.\n");
3248                 return 0;
3249         }
3250         tg3reg_base = pci_bar_start(pdev, PCI_BASE_ADDRESS_0);
3251         if (tg3reg_base == -1UL) {
3252                 printf("Unuseable bar\n");
3253                 return 0;
3254         }
3255         tg3reg_len  = pci_bar_size(pdev,  PCI_BASE_ADDRESS_0);
3256
3257         tp->pdev       = pdev;
3258         tp->nic        = nic;
3259         tp->pm_cap     = pm_cap;
3260         tp->rx_mode    = 0;
3261         tp->tx_mode    = 0;
3262         tp->mi_mode    = MAC_MI_MODE_BASE;
3263         tp->tg3_flags  = 0 & ~TG3_FLAG_INIT_COMPLETE; 
3264         
3265         /* The word/byte swap controls here control register access byte
3266          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
3267          * setting below.
3268          */
3269         tp->misc_host_ctrl =
3270                 MISC_HOST_CTRL_MASK_PCI_INT |
3271                 MISC_HOST_CTRL_WORD_SWAP |
3272                 MISC_HOST_CTRL_INDIR_ACCESS |
3273                 MISC_HOST_CTRL_PCISTATE_RW;
3274
3275         /* The NONFRM (non-frame) byte/word swap controls take effect
3276          * on descriptor entries, anything which isn't packet data.
3277          *
3278          * The StrongARM chips on the board (one for tx, one for rx)
3279          * are running in big-endian mode.
3280          */
3281         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
3282                         GRC_MODE_WSWAP_NONFRM_DATA);
3283 #if __BYTE_ORDER == __BIG_ENDIAN
3284         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
3285 #endif
3286         tp->regs = (unsigned long) ioremap(tg3reg_base, tg3reg_len);
3287         if (tp->regs == 0UL) {
3288                 printf("Cannot map device registers, aborting\n");
3289                 return 0;
3290         }
3291
3292         tg3_init_link_config(tp);
3293
3294         err = tg3_get_invariants(tp);
3295         if (err) {
3296                 printf("Problem fetching invariants of chip, aborting.\n");
3297                 goto err_out_iounmap;
3298         }
3299
3300         err = tg3_get_device_address(tp);
3301         if (err) {
3302                 printf("Could not obtain valid ethernet address, aborting.\n");
3303                 goto err_out_iounmap;
3304         }
3305         printf("Ethernet addr: %!\n", nic->node_addr);
3306
3307         tg3_setup_dma(tp);
3308
3309         /* Now that we have fully setup the chip, save away a snapshot
3310          * of the PCI config space.  We need to restore this after
3311          * GRC_MISC_CFG core clock resets and some resume events.
3312          */
3313         pci_save_state(tp->pdev, tp->pci_cfg_state);
3314
3315         printf("Tigon3 [partno(%s) rev %hx PHY(%s)] (PCI%s:%s:%s)\n",
3316                 tp->board_part_number,
3317                 tp->pci_chip_rev_id,
3318                 tg3_phy_string(tp),
3319                 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "X" : ""),
3320                 ((tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED) ?
3321                         ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "133MHz" : "66MHz") :
3322                         ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ? "100MHz" : "33MHz")),
3323                 ((tp->tg3_flags & TG3_FLAG_PCI_32BIT) ? "32-bit" : "64-bit"));
3324
3325
3326         err = tg3_setup_hw(tp); 
3327         if (err) {
3328                 goto err_out_disable;
3329         } 
3330         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
3331
3332         /* Wait for a reasonable time for the link to come up */
3333         tg3_poll_link(tp);
3334         for(i = 0; !tp->carrier_ok && (i < VALID_LINK_TIMEOUT*100); i++) {
3335                 mdelay(1);
3336                 tg3_poll_link(tp);
3337         }
3338         if (!tp->carrier_ok){
3339                 printf("Valid link not established\n");
3340                 goto err_out_disable;
3341         }
3342
3343         dev->disable  = tg3_disable;
3344         nic->poll     = tg3_poll;
3345         nic->transmit = tg3_transmit;
3346         nic->irq      = tg3_irq;
3347
3348         return 1;
3349
3350  err_out_iounmap:
3351         iounmap((void *)tp->regs);
3352         return 0;
3353  err_out_disable:
3354         tg3_disable(dev);
3355         return 0;
3356 }
3357
3358 static struct pci_id tg3_nics[] = {
3359 PCI_ROM(0x14e4, 0x1644, "tg3-5700",        "Broadcom Tigon 3 5700"),
3360 PCI_ROM(0x14e4, 0x1645, "tg3-5701",        "Broadcom Tigon 3 5701"),
3361 PCI_ROM(0x14e4, 0x1646, "tg3-5702",        "Broadcom Tigon 3 5702"),
3362 PCI_ROM(0x14e4, 0x1647, "tg3-5703",        "Broadcom Tigon 3 5703"),
3363 PCI_ROM(0x14e4, 0x1648, "tg3-5704",        "Broadcom Tigon 3 5704"),
3364 PCI_ROM(0x14e4, 0x164d, "tg3-5702FE",      "Broadcom Tigon 3 5702FE"),
3365 PCI_ROM(0x14e4, 0x1653, "tg3-5705",        "Broadcom Tigon 3 5705"),
3366 PCI_ROM(0x14e4, 0x1654, "tg3-5705_2",      "Broadcom Tigon 3 5705_2"),
3367 PCI_ROM(0x14e4, 0x165d, "tg3-5705M",       "Broadcom Tigon 3 5705M"),
3368 PCI_ROM(0x14e4, 0x165e, "tg3-5705M_2",     "Broadcom Tigon 3 5705M_2"),
3369 PCI_ROM(0x14e4, 0x1677, "tg3-5751",        "Broadcom Tigon 3 5751"),
3370 PCI_ROM(0x14e4, 0x1696, "tg3-5782",        "Broadcom Tigon 3 5782"),
3371 PCI_ROM(0x14e4, 0x169c, "tg3-5788",        "Broadcom Tigon 3 5788"),
3372 PCI_ROM(0x14e4, 0x16a6, "tg3-5702X",       "Broadcom Tigon 3 5702X"),
3373 PCI_ROM(0x14e4, 0x16a7, "tg3-5703X",       "Broadcom Tigon 3 5703X"),
3374 PCI_ROM(0x14e4, 0x16a8, "tg3-5704S",       "Broadcom Tigon 3 5704S"),
3375 PCI_ROM(0x14e4, 0x16c6, "tg3-5702A3",      "Broadcom Tigon 3 5702A3"),
3376 PCI_ROM(0x14e4, 0x16c7, "tg3-5703A3",      "Broadcom Tigon 3 5703A3"),
3377 PCI_ROM(0x14e4, 0x170d, "tg3-5901",        "Broadcom Tigon 3 5901"),
3378 PCI_ROM(0x14e4, 0x170e, "tg3-5901_2",      "Broadcom Tigon 3 5901_2"),
3379 PCI_ROM(0x1148, 0x4400, "tg3-9DXX",        "Syskonnect 9DXX"),
3380 PCI_ROM(0x1148, 0x4500, "tg3-9MXX",        "Syskonnect 9MXX"),
3381 PCI_ROM(0x173b, 0x03e8, "tg3-ac1000",      "Altima AC1000"),
3382 PCI_ROM(0x173b, 0x03e9, "tg3-ac1001",      "Altima AC1001"),
3383 PCI_ROM(0x173b, 0x03ea, "tg3-ac9100",      "Altima AC9100"),
3384 PCI_ROM(0x173b, 0x03eb, "tg3-ac1003",      "Altima AC1003"),
3385 };
3386
3387 static struct pci_driver tg3_driver __pci_driver = {
3388         .type     = NIC_DRIVER,
3389         .name     = "TG3",
3390         .probe    = tg3_probe,
3391         .ids      = tg3_nics,
3392         .id_count = sizeof(tg3_nics)/sizeof(tg3_nics[0]),
3393         .class    = 0,
3394 };