Initial revision
[etherboot.git] / src / drivers / net / e1000.c
1 /**************************************************************************
2 Etherboot -  BOOTP/TFTP Bootstrap Program
3 Inter Pro 1000 for Etherboot
4 Drivers are port from Intel's Linux driver e1000-4.3.15
5
6 ***************************************************************************/
7 /*******************************************************************************
8
9   
10   Copyright(c) 1999 - 2003 Intel Corporation. All rights reserved.
11   
12   This program is free software; you can redistribute it and/or modify it 
13   under the terms of the GNU General Public License as published by the Free 
14   Software Foundation; either version 2 of the License, or (at your option) 
15   any later version.
16   
17   This program is distributed in the hope that it will be useful, but WITHOUT 
18   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 
19   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for 
20   more details.
21   
22   You should have received a copy of the GNU General Public License along with
23   this program; if not, write to the Free Software Foundation, Inc., 59 
24   Temple Place - Suite 330, Boston, MA  02111-1307, USA.
25   
26   The full GNU General Public License is included in this distribution in the
27   file called LICENSE.
28   
29   Contact Information:
30   Linux NICS <linux.nics@intel.com>
31   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
32
33 *******************************************************************************/
34 /*
35  *  Copyright (C) Archway Digital Solutions.
36  *
37  *  written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
38  *  2/9/2002
39  *
40  *  Copyright (C) Linux Networx.
41  *  Massive upgrade to work with the new intel gigabit NICs.
42  *  <ebiederman at lnxi dot com>
43  *
44  *  Support for 82541ei & 82547ei chips from Intel's Linux driver 5.1.13 added by
45  *  Georg Baum <gbaum@users.sf.net>, sponsored by PetaMem GmbH and linkLINE Communications, Inc.
46  *
47  *  01/2004: Updated to Linux driver 5.2.22 by Georg Baum <gbaum@users.sf.net>
48  */
49
50 /* to get some global routines like printf */
51 #include "etherboot.h"
52 /* to get the interface to the body of the program */
53 #include "nic.h"
54 /* to get the PCI support functions, if this is a PCI NIC */
55 #include "pci.h"
56 #include "timer.h"
57
58 typedef unsigned char *dma_addr_t;
59
60 typedef enum {
61         FALSE = 0,
62         TRUE = 1
63 } boolean_t;
64
65 #define DEBUG 0
66
67
68 /* Some pieces of code are disabled with #if 0 ... #endif.
69  * They are not deleted to show where the etherboot driver differs
70  * from the linux driver below the function level.
71  * Some member variables of the hw struct have been eliminated
72  * and the corresponding inplace checks inserted instead.
73  * Pieces such as LED handling that we definitely don't need are deleted.
74  *
75  * The following defines should not be needed normally,
76  * but may be helpful for debugging purposes. */
77
78 /* Define this if you want to program the transmission control register
79  * the way the Linux driver does it. */
80 #undef LINUX_DRIVER_TCTL
81
82 /* Define this to behave more like the Linux driver. */
83 #undef LINUX_DRIVER
84
85 #include "e1000_hw.h"
86
87 /* NIC specific static variables go here */
88 static struct e1000_hw hw;
89 static char tx_pool[128 + 16];
90 static char rx_pool[128 + 16];
91 static char packet[2096];
92
93 static struct e1000_tx_desc *tx_base;
94 static struct e1000_rx_desc *rx_base;
95
96 static int tx_tail;
97 static int rx_tail, rx_last;
98
99 /* Function forward declarations */
100 static int e1000_setup_link(struct e1000_hw *hw);
101 static int e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
102 static int e1000_setup_copper_link(struct e1000_hw *hw);
103 static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
104 static void e1000_config_collision_dist(struct e1000_hw *hw);
105 static int e1000_config_mac_to_phy(struct e1000_hw *hw);
106 static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
107 static int e1000_check_for_link(struct e1000_hw *hw);
108 static int e1000_wait_autoneg(struct e1000_hw *hw);
109 static void e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t *speed, uint16_t *duplex);
110 static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
111 static int e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
112 static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
113 static int e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr, uint16_t phy_data);
114 static void e1000_phy_hw_reset(struct e1000_hw *hw);
115 static int e1000_phy_reset(struct e1000_hw *hw);
116 static int e1000_detect_gig_phy(struct e1000_hw *hw);
117 static void e1000_irq(struct nic *nic, irq_action_t action);
118
119 /* Printing macros... */
120
121 #define E1000_ERR(args...) printf("e1000: " args)
122
123 #if DEBUG >= 3
124 #define E1000_DBG(args...) printf("e1000: " args)
125 #else
126 #define E1000_DBG(args...)
127 #endif
128
129 #define MSGOUT(S, A, B)     printk(S "\n", A, B)
130 #if DEBUG >= 2
131 #define DEBUGFUNC(F)        DEBUGOUT(F "\n");
132 #else
133 #define DEBUGFUNC(F)
134 #endif
135 #if DEBUG >= 1
136 #define DEBUGOUT(S) printf(S)
137 #define DEBUGOUT1(S,A) printf(S,A)
138 #define DEBUGOUT2(S,A,B) printf(S,A,B)
139 #define DEBUGOUT3(S,A,B,C) printf(S,A,B,C)
140 #define DEBUGOUT7(S,A,B,C,D,E,F,G) printf(S,A,B,C,D,E,F,G)
141 #else
142 #define DEBUGOUT(S)
143 #define DEBUGOUT1(S,A)
144 #define DEBUGOUT2(S,A,B)
145 #define DEBUGOUT3(S,A,B,C)
146 #define DEBUGOUT7(S,A,B,C,D,E,F,G)
147 #endif
148
149 #define E1000_WRITE_REG(a, reg, value) ( \
150     ((a)->mac_type >= e1000_82543) ? \
151         (writel((value), ((a)->hw_addr + E1000_##reg))) : \
152         (writel((value), ((a)->hw_addr + E1000_82542_##reg))))
153
154 #define E1000_READ_REG(a, reg) ( \
155     ((a)->mac_type >= e1000_82543) ? \
156         readl((a)->hw_addr + E1000_##reg) : \
157         readl((a)->hw_addr + E1000_82542_##reg))
158
159 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) ( \
160     ((a)->mac_type >= e1000_82543) ? \
161         writel((value), ((a)->hw_addr + E1000_##reg + ((offset) << 2))) : \
162         writel((value), ((a)->hw_addr + E1000_82542_##reg + ((offset) << 2))))
163
164 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \
165     ((a)->mac_type >= e1000_82543) ? \
166         readl((a)->hw_addr + E1000_##reg + ((offset) << 2)) : \
167         readl((a)->hw_addr + E1000_82542_##reg + ((offset) << 2)))
168
169 #define E1000_WRITE_FLUSH(a) {uint32_t x; x = E1000_READ_REG(a, STATUS);}
170
171 uint32_t
172 e1000_io_read(struct e1000_hw *hw __unused, uint32_t port)
173 {
174         return inl(port);
175 }
176
177 void
178 e1000_io_write(struct e1000_hw *hw __unused, uint32_t port, uint32_t value)
179 {
180         outl(value, port);
181 }
182
183 static inline void e1000_pci_set_mwi(struct e1000_hw *hw)
184 {
185         pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
186 }
187
188 static inline void e1000_pci_clear_mwi(struct e1000_hw *hw)
189 {
190         pci_write_config_word(hw->pdev, PCI_COMMAND,
191                               hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
192 }
193
194 /******************************************************************************
195  * Raises the EEPROM's clock input.
196  *
197  * hw - Struct containing variables accessed by shared code
198  * eecd - EECD's current value
199  *****************************************************************************/
200 static void
201 e1000_raise_ee_clk(struct e1000_hw *hw,
202                    uint32_t *eecd)
203 {
204         /* Raise the clock input to the EEPROM (by setting the SK bit), and then
205          * wait <delay> microseconds.
206          */
207         *eecd = *eecd | E1000_EECD_SK;
208         E1000_WRITE_REG(hw, EECD, *eecd);
209         E1000_WRITE_FLUSH(hw);
210         udelay(hw->eeprom.delay_usec);
211 }
212
213 /******************************************************************************
214  * Lowers the EEPROM's clock input.
215  *
216  * hw - Struct containing variables accessed by shared code 
217  * eecd - EECD's current value
218  *****************************************************************************/
219 static void
220 e1000_lower_ee_clk(struct e1000_hw *hw,
221                    uint32_t *eecd)
222 {
223         /* Lower the clock input to the EEPROM (by clearing the SK bit), and then 
224          * wait 50 microseconds. 
225          */
226         *eecd = *eecd & ~E1000_EECD_SK;
227         E1000_WRITE_REG(hw, EECD, *eecd);
228         E1000_WRITE_FLUSH(hw);
229         udelay(hw->eeprom.delay_usec);
230 }
231
232 /******************************************************************************
233  * Shift data bits out to the EEPROM.
234  *
235  * hw - Struct containing variables accessed by shared code
236  * data - data to send to the EEPROM
237  * count - number of bits to shift out
238  *****************************************************************************/
239 static void
240 e1000_shift_out_ee_bits(struct e1000_hw *hw,
241                         uint16_t data,
242                         uint16_t count)
243 {
244         struct e1000_eeprom_info *eeprom = &hw->eeprom;
245         uint32_t eecd;
246         uint32_t mask;
247         
248         /* We need to shift "count" bits out to the EEPROM. So, value in the
249          * "data" parameter will be shifted out to the EEPROM one bit at a time.
250          * In order to do this, "data" must be broken down into bits. 
251          */
252         mask = 0x01 << (count - 1);
253         eecd = E1000_READ_REG(hw, EECD);
254         if (eeprom->type == e1000_eeprom_microwire) {
255                 eecd &= ~E1000_EECD_DO;
256         } else if (eeprom->type == e1000_eeprom_spi) {
257                 eecd |= E1000_EECD_DO;
258         }
259         do {
260                 /* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
261                  * and then raising and then lowering the clock (the SK bit controls
262                  * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
263                  * by setting "DI" to "0" and then raising and then lowering the clock.
264                  */
265                 eecd &= ~E1000_EECD_DI;
266                 
267                 if(data & mask)
268                         eecd |= E1000_EECD_DI;
269                 
270                 E1000_WRITE_REG(hw, EECD, eecd);
271                 E1000_WRITE_FLUSH(hw);
272                 
273                 udelay(eeprom->delay_usec);
274                 
275                 e1000_raise_ee_clk(hw, &eecd);
276                 e1000_lower_ee_clk(hw, &eecd);
277                 
278                 mask = mask >> 1;
279                 
280         } while(mask);
281
282         /* We leave the "DI" bit set to "0" when we leave this routine. */
283         eecd &= ~E1000_EECD_DI;
284         E1000_WRITE_REG(hw, EECD, eecd);
285 }
286
287 /******************************************************************************
288  * Shift data bits in from the EEPROM
289  *
290  * hw - Struct containing variables accessed by shared code
291  *****************************************************************************/
292 static uint16_t
293 e1000_shift_in_ee_bits(struct e1000_hw *hw,
294                        uint16_t count)
295 {
296         uint32_t eecd;
297         uint32_t i;
298         uint16_t data;
299         
300         /* In order to read a register from the EEPROM, we need to shift 'count' 
301          * bits in from the EEPROM. Bits are "shifted in" by raising the clock
302          * input to the EEPROM (setting the SK bit), and then reading the value of
303          * the "DO" bit.  During this "shifting in" process the "DI" bit should
304          * always be clear.
305          */
306         
307         eecd = E1000_READ_REG(hw, EECD);
308         
309         eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
310         data = 0;
311         
312         for(i = 0; i < count; i++) {
313                 data = data << 1;
314                 e1000_raise_ee_clk(hw, &eecd);
315                 
316                 eecd = E1000_READ_REG(hw, EECD);
317                 
318                 eecd &= ~(E1000_EECD_DI);
319                 if(eecd & E1000_EECD_DO)
320                         data |= 1;
321                 
322                 e1000_lower_ee_clk(hw, &eecd);
323         }
324         
325         return data;
326 }
327
328 /******************************************************************************
329  * Prepares EEPROM for access
330  *
331  * hw - Struct containing variables accessed by shared code
332  *
333  * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This 
334  * function should be called before issuing a command to the EEPROM.
335  *****************************************************************************/
336 static int32_t
337 e1000_acquire_eeprom(struct e1000_hw *hw)
338 {
339         struct e1000_eeprom_info *eeprom = &hw->eeprom;
340         uint32_t eecd, i=0;
341
342         eecd = E1000_READ_REG(hw, EECD);
343
344         /* Request EEPROM Access */
345         if(hw->mac_type > e1000_82544) {
346                 eecd |= E1000_EECD_REQ;
347                 E1000_WRITE_REG(hw, EECD, eecd);
348                 eecd = E1000_READ_REG(hw, EECD);
349                 while((!(eecd & E1000_EECD_GNT)) &&
350                       (i < E1000_EEPROM_GRANT_ATTEMPTS)) {
351                         i++;
352                         udelay(5);
353                         eecd = E1000_READ_REG(hw, EECD);
354                 }
355                 if(!(eecd & E1000_EECD_GNT)) {
356                         eecd &= ~E1000_EECD_REQ;
357                         E1000_WRITE_REG(hw, EECD, eecd);
358                         DEBUGOUT("Could not acquire EEPROM grant\n");
359                         return -E1000_ERR_EEPROM;
360                 }
361         }
362
363         /* Setup EEPROM for Read/Write */
364
365         if (eeprom->type == e1000_eeprom_microwire) {
366                 /* Clear SK and DI */
367                 eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
368                 E1000_WRITE_REG(hw, EECD, eecd);
369
370                 /* Set CS */
371                 eecd |= E1000_EECD_CS;
372                 E1000_WRITE_REG(hw, EECD, eecd);
373         } else if (eeprom->type == e1000_eeprom_spi) {
374                 /* Clear SK and CS */
375                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
376                 E1000_WRITE_REG(hw, EECD, eecd);
377                 udelay(1);
378         }
379
380         return E1000_SUCCESS;
381 }
382
383 /******************************************************************************
384  * Returns EEPROM to a "standby" state
385  * 
386  * hw - Struct containing variables accessed by shared code
387  *****************************************************************************/
388 static void
389 e1000_standby_eeprom(struct e1000_hw *hw)
390 {
391         struct e1000_eeprom_info *eeprom = &hw->eeprom;
392         uint32_t eecd;
393         
394         eecd = E1000_READ_REG(hw, EECD);
395
396         if(eeprom->type == e1000_eeprom_microwire) {
397
398                 /* Deselect EEPROM */
399                 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
400                 E1000_WRITE_REG(hw, EECD, eecd);
401                 E1000_WRITE_FLUSH(hw);
402                 udelay(eeprom->delay_usec);
403         
404                 /* Clock high */
405                 eecd |= E1000_EECD_SK;
406                 E1000_WRITE_REG(hw, EECD, eecd);
407                 E1000_WRITE_FLUSH(hw);
408                 udelay(eeprom->delay_usec);
409         
410                 /* Select EEPROM */
411                 eecd |= E1000_EECD_CS;
412                 E1000_WRITE_REG(hw, EECD, eecd);
413                 E1000_WRITE_FLUSH(hw);
414                 udelay(eeprom->delay_usec);
415
416                 /* Clock low */
417                 eecd &= ~E1000_EECD_SK;
418                 E1000_WRITE_REG(hw, EECD, eecd);
419                 E1000_WRITE_FLUSH(hw);
420                 udelay(eeprom->delay_usec);
421         } else if(eeprom->type == e1000_eeprom_spi) {
422                 /* Toggle CS to flush commands */
423                 eecd |= E1000_EECD_CS;
424                 E1000_WRITE_REG(hw, EECD, eecd);
425                 E1000_WRITE_FLUSH(hw);
426                 udelay(eeprom->delay_usec);
427                 eecd &= ~E1000_EECD_CS;
428                 E1000_WRITE_REG(hw, EECD, eecd);
429                 E1000_WRITE_FLUSH(hw);
430                 udelay(eeprom->delay_usec);
431         }
432 }
433
434 /******************************************************************************
435  * Terminates a command by inverting the EEPROM's chip select pin
436  *
437  * hw - Struct containing variables accessed by shared code
438  *****************************************************************************/
439 static void
440 e1000_release_eeprom(struct e1000_hw *hw)
441 {
442         uint32_t eecd;
443
444         eecd = E1000_READ_REG(hw, EECD);
445
446         if (hw->eeprom.type == e1000_eeprom_spi) {
447                 eecd |= E1000_EECD_CS;  /* Pull CS high */
448                 eecd &= ~E1000_EECD_SK; /* Lower SCK */
449
450                 E1000_WRITE_REG(hw, EECD, eecd);
451
452                 udelay(hw->eeprom.delay_usec);
453         } else if(hw->eeprom.type == e1000_eeprom_microwire) {
454                 /* cleanup eeprom */
455
456                 /* CS on Microwire is active-high */
457                 eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);
458
459                 E1000_WRITE_REG(hw, EECD, eecd);
460
461                 /* Rising edge of clock */
462                 eecd |= E1000_EECD_SK;
463                 E1000_WRITE_REG(hw, EECD, eecd);
464                 E1000_WRITE_FLUSH(hw);
465                 udelay(hw->eeprom.delay_usec);
466
467                 /* Falling edge of clock */
468                 eecd &= ~E1000_EECD_SK;
469                 E1000_WRITE_REG(hw, EECD, eecd);
470                 E1000_WRITE_FLUSH(hw);
471                 udelay(hw->eeprom.delay_usec);
472         }
473
474         /* Stop requesting EEPROM access */
475         if(hw->mac_type > e1000_82544) {
476                 eecd &= ~E1000_EECD_REQ;
477                 E1000_WRITE_REG(hw, EECD, eecd);
478         }
479 }
480
481 /******************************************************************************
482  * Reads a 16 bit word from the EEPROM.
483  *
484  * hw - Struct containing variables accessed by shared code
485  *****************************************************************************/
486 static int32_t
487 e1000_spi_eeprom_ready(struct e1000_hw *hw)
488 {
489         uint16_t retry_count = 0;
490         uint8_t spi_stat_reg;
491
492         /* Read "Status Register" repeatedly until the LSB is cleared.  The
493          * EEPROM will signal that the command has been completed by clearing
494          * bit 0 of the internal status register.  If it's not cleared within
495          * 5 milliseconds, then error out.
496          */
497         retry_count = 0;
498         do {
499                 e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
500                 hw->eeprom.opcode_bits);
501                 spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
502                 if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
503                         break;
504
505                 udelay(5);
506                 retry_count += 5;
507
508         } while(retry_count < EEPROM_MAX_RETRY_SPI);
509
510         /* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
511          * only 0-5mSec on 5V devices)
512          */
513         if(retry_count >= EEPROM_MAX_RETRY_SPI) {
514                 DEBUGOUT("SPI EEPROM Status error\n");
515                 return -E1000_ERR_EEPROM;
516         }
517
518         return E1000_SUCCESS;
519 }
520
521 /******************************************************************************
522  * Reads a 16 bit word from the EEPROM.
523  *
524  * hw - Struct containing variables accessed by shared code
525  * offset - offset of  word in the EEPROM to read
526  * data - word read from the EEPROM
527  * words - number of words to read
528  *****************************************************************************/
529 static int
530 e1000_read_eeprom(struct e1000_hw *hw,
531                   uint16_t offset,
532                   uint16_t words,
533                   uint16_t *data)
534 {
535         struct e1000_eeprom_info *eeprom = &hw->eeprom;
536         uint32_t i = 0;
537         
538         DEBUGFUNC("e1000_read_eeprom");
539
540         /* A check for invalid values:  offset too large, too many words, and not
541          * enough words.
542          */
543         if((offset > eeprom->word_size) || (words > eeprom->word_size - offset) ||
544            (words == 0)) {
545                 DEBUGOUT("\"words\" parameter out of bounds\n");
546                 return -E1000_ERR_EEPROM;
547         }
548
549         /*  Prepare the EEPROM for reading  */
550         if(e1000_acquire_eeprom(hw) != E1000_SUCCESS)
551                 return -E1000_ERR_EEPROM;
552
553         if(eeprom->type == e1000_eeprom_spi) {
554                 uint16_t word_in;
555                 uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
556
557                 if(e1000_spi_eeprom_ready(hw)) {
558                         e1000_release_eeprom(hw);
559                         return -E1000_ERR_EEPROM;
560                 }
561
562                 e1000_standby_eeprom(hw);
563
564                 /* Some SPI eeproms use the 8th address bit embedded in the opcode */
565                 if((eeprom->address_bits == 8) && (offset >= 128))
566                         read_opcode |= EEPROM_A8_OPCODE_SPI;
567
568                 /* Send the READ command (opcode + addr)  */
569                 e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
570                 e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
571
572                 /* Read the data.  The address of the eeprom internally increments with
573                  * each byte (spi) being read, saving on the overhead of eeprom setup
574                  * and tear-down.  The address counter will roll over if reading beyond
575                  * the size of the eeprom, thus allowing the entire memory to be read
576                  * starting from any offset. */
577                 for (i = 0; i < words; i++) {
578                         word_in = e1000_shift_in_ee_bits(hw, 16);
579                         data[i] = (word_in >> 8) | (word_in << 8);
580                 }
581         } else if(eeprom->type == e1000_eeprom_microwire) {
582                 for (i = 0; i < words; i++) {
583                         /*  Send the READ command (opcode + addr)  */
584                         e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
585                                                 eeprom->opcode_bits);
586                         e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
587                                                 eeprom->address_bits);
588
589                         /* Read the data.  For microwire, each word requires the overhead
590                          * of eeprom setup and tear-down. */
591                         data[i] = e1000_shift_in_ee_bits(hw, 16);
592                         e1000_standby_eeprom(hw);
593                 }
594         }
595
596         /* End this read operation */
597         e1000_release_eeprom(hw);
598
599         return E1000_SUCCESS;
600 }
601
602 /******************************************************************************
603  * Verifies that the EEPROM has a valid checksum
604  * 
605  * hw - Struct containing variables accessed by shared code
606  *
607  * Reads the first 64 16 bit words of the EEPROM and sums the values read.
608  * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
609  * valid.
610  *****************************************************************************/
611 static int
612 e1000_validate_eeprom_checksum(struct e1000_hw *hw)
613 {
614         uint16_t checksum = 0;
615         uint16_t i, eeprom_data;
616
617         DEBUGFUNC("e1000_validate_eeprom_checksum");
618
619         for(i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
620                 if(e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
621                         DEBUGOUT("EEPROM Read Error\n");
622                         return -E1000_ERR_EEPROM;
623                 }
624                 checksum += eeprom_data;
625         }
626         
627         if(checksum == (uint16_t) EEPROM_SUM)
628                 return E1000_SUCCESS;
629         else {
630                 DEBUGOUT("EEPROM Checksum Invalid\n");    
631                 return -E1000_ERR_EEPROM;
632         }
633 }
634
635 /******************************************************************************
636  * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
637  * second function of dual function devices
638  *
639  * hw - Struct containing variables accessed by shared code
640  *****************************************************************************/
641 static int 
642 e1000_read_mac_addr(struct e1000_hw *hw)
643 {
644         uint16_t offset;
645         uint16_t eeprom_data;
646         int i;
647
648         DEBUGFUNC("e1000_read_mac_addr");
649
650         for(i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
651                 offset = i >> 1;
652                 if(e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
653                         DEBUGOUT("EEPROM Read Error\n");
654                         return -E1000_ERR_EEPROM;
655                 }
656                 hw->mac_addr[i] = eeprom_data & 0xff;
657                 hw->mac_addr[i+1] = (eeprom_data >> 8) & 0xff;
658         }
659         if(((hw->mac_type == e1000_82546) || (hw->mac_type == e1000_82546_rev_3)) &&
660                 (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1))
661                 /* Invert the last bit if this is the second device */
662                 hw->mac_addr[5] ^= 1;
663         return E1000_SUCCESS;
664 }
665
666 /******************************************************************************
667  * Initializes receive address filters.
668  *
669  * hw - Struct containing variables accessed by shared code 
670  *
671  * Places the MAC address in receive address register 0 and clears the rest
672  * of the receive addresss registers. Clears the multicast table. Assumes
673  * the receiver is in reset when the routine is called.
674  *****************************************************************************/
675 static void
676 e1000_init_rx_addrs(struct e1000_hw *hw)
677 {
678         uint32_t i;
679         uint32_t addr_low;
680         uint32_t addr_high;
681         
682         DEBUGFUNC("e1000_init_rx_addrs");
683         
684         /* Setup the receive address. */
685         DEBUGOUT("Programming MAC Address into RAR[0]\n");
686         addr_low = (hw->mac_addr[0] |
687                 (hw->mac_addr[1] << 8) |
688                 (hw->mac_addr[2] << 16) | (hw->mac_addr[3] << 24));
689         
690         addr_high = (hw->mac_addr[4] |
691                 (hw->mac_addr[5] << 8) | E1000_RAH_AV);
692         
693         E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
694         E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);
695         
696         /* Zero out the other 15 receive addresses. */
697         DEBUGOUT("Clearing RAR[1-15]\n");
698         for(i = 1; i < E1000_RAR_ENTRIES; i++) {
699                 E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
700                 E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
701         }
702 }
703
704 /******************************************************************************
705  * Clears the VLAN filer table
706  *
707  * hw - Struct containing variables accessed by shared code
708  *****************************************************************************/
709 static void
710 e1000_clear_vfta(struct e1000_hw *hw)
711 {
712         uint32_t offset;
713     
714         for(offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
715                 E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
716 }
717
718 /******************************************************************************
719 * Writes a value to one of the devices registers using port I/O (as opposed to
720 * memory mapped I/O). Only 82544 and newer devices support port I/O. *
721 * hw - Struct containing variables accessed by shared code
722 * offset - offset to write to * value - value to write
723 *****************************************************************************/
724 void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value){
725         uint32_t io_addr = hw->io_base;
726         uint32_t io_data = hw->io_base + 4;
727         e1000_io_write(hw, io_addr, offset);
728         e1000_io_write(hw, io_data, value);
729 }
730
731 /******************************************************************************
732  * Set the phy type member in the hw struct.
733  *
734  * hw - Struct containing variables accessed by shared code
735  *****************************************************************************/
736 static int32_t
737 e1000_set_phy_type(struct e1000_hw *hw)
738 {
739         DEBUGFUNC("e1000_set_phy_type");
740
741         switch(hw->phy_id) {
742         case M88E1000_E_PHY_ID:
743         case M88E1000_I_PHY_ID:
744         case M88E1011_I_PHY_ID:
745                 hw->phy_type = e1000_phy_m88;
746                 break;
747         case IGP01E1000_I_PHY_ID:
748                 hw->phy_type = e1000_phy_igp;
749                 break;
750         default:
751                 /* Should never have loaded on this device */
752                 hw->phy_type = e1000_phy_undefined;
753                 return -E1000_ERR_PHY_TYPE;
754         }
755
756         return E1000_SUCCESS;
757 }
758
759 /******************************************************************************
760  * IGP phy init script - initializes the GbE PHY
761  *
762  * hw - Struct containing variables accessed by shared code
763  *****************************************************************************/
764 static void
765 e1000_phy_init_script(struct e1000_hw *hw)
766 {
767         DEBUGFUNC("e1000_phy_init_script");
768
769 #if 0
770         /* See e1000_sw_init() of the Linux driver */
771         if(hw->phy_init_script) {
772 #else
773         if((hw->mac_type == e1000_82541) ||
774            (hw->mac_type == e1000_82547) ||
775            (hw->mac_type == e1000_82541_rev_2) ||
776            (hw->mac_type == e1000_82547_rev_2)) {
777 #endif
778                 mdelay(20);
779
780                 e1000_write_phy_reg(hw,0x0000,0x0140);
781
782                 mdelay(5);
783
784                 if(hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547) {
785                         e1000_write_phy_reg(hw, 0x1F95, 0x0001);
786
787                         e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
788
789                         e1000_write_phy_reg(hw, 0x1F79, 0x0018);
790
791                         e1000_write_phy_reg(hw, 0x1F30, 0x1600);
792
793                         e1000_write_phy_reg(hw, 0x1F31, 0x0014);
794
795                         e1000_write_phy_reg(hw, 0x1F32, 0x161C);
796
797                         e1000_write_phy_reg(hw, 0x1F94, 0x0003);
798
799                         e1000_write_phy_reg(hw, 0x1F96, 0x003F);
800
801                         e1000_write_phy_reg(hw, 0x2010, 0x0008);
802                 } else {
803                         e1000_write_phy_reg(hw, 0x1F73, 0x0099);
804                 }
805
806                 e1000_write_phy_reg(hw, 0x0000, 0x3300);
807
808
809                 if(hw->mac_type == e1000_82547) {
810                         uint16_t fused, fine, coarse;
811
812                         /* Move to analog registers page */
813                         e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
814
815                         if(!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
816                                 e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
817
818                                 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
819                                 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
820
821                                 if(coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
822                                         coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
823                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
824                                 } else if(coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
825                                         fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
826
827                                 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) |
828                                         (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) |
829                                         (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
830
831                                 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
832                                 e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
833                                                 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
834                         }
835                 }
836         }
837 }
838
839 /******************************************************************************
840  * Set the mac type member in the hw struct.
841  * 
842  * hw - Struct containing variables accessed by shared code
843  *****************************************************************************/
844 static int
845 e1000_set_mac_type(struct e1000_hw *hw)
846 {
847         DEBUGFUNC("e1000_set_mac_type");
848
849         switch (hw->device_id) {
850         case E1000_DEV_ID_82542:
851                 switch (hw->revision_id) {
852                 case E1000_82542_2_0_REV_ID:
853                         hw->mac_type = e1000_82542_rev2_0;
854                         break;
855                 case E1000_82542_2_1_REV_ID:
856                         hw->mac_type = e1000_82542_rev2_1;
857                         break;
858                 default:
859                         /* Invalid 82542 revision ID */
860                         return -E1000_ERR_MAC_TYPE;
861                 }
862                 break;
863         case E1000_DEV_ID_82543GC_FIBER:
864         case E1000_DEV_ID_82543GC_COPPER:
865                 hw->mac_type = e1000_82543;
866                 break;
867         case E1000_DEV_ID_82544EI_COPPER:
868         case E1000_DEV_ID_82544EI_FIBER:
869         case E1000_DEV_ID_82544GC_COPPER:
870         case E1000_DEV_ID_82544GC_LOM:
871                 hw->mac_type = e1000_82544;
872                 break;
873         case E1000_DEV_ID_82540EM:
874         case E1000_DEV_ID_82540EM_LOM:
875         case E1000_DEV_ID_82540EP:
876         case E1000_DEV_ID_82540EP_LOM:
877         case E1000_DEV_ID_82540EP_LP:
878                 hw->mac_type = e1000_82540;
879                 break;
880         case E1000_DEV_ID_82545EM_COPPER:
881         case E1000_DEV_ID_82545EM_FIBER:
882                 hw->mac_type = e1000_82545;
883                 break;
884         case E1000_DEV_ID_82545GM_COPPER:
885         case E1000_DEV_ID_82545GM_FIBER:
886         case E1000_DEV_ID_82545GM_SERDES:
887                 hw->mac_type = e1000_82545_rev_3;
888                 break;
889         case E1000_DEV_ID_82546EB_COPPER:
890         case E1000_DEV_ID_82546EB_FIBER:
891         case E1000_DEV_ID_82546EB_QUAD_COPPER:
892                 hw->mac_type = e1000_82546;
893                 break;
894         case E1000_DEV_ID_82546GB_COPPER:
895         case E1000_DEV_ID_82546GB_FIBER:
896         case E1000_DEV_ID_82546GB_SERDES:
897                 hw->mac_type = e1000_82546_rev_3;
898                 break;
899         case E1000_DEV_ID_82541EI:
900         case E1000_DEV_ID_82541EI_MOBILE:
901                 hw->mac_type = e1000_82541;
902                 break;
903         case E1000_DEV_ID_82541ER:
904         case E1000_DEV_ID_82541GI:
905         case E1000_DEV_ID_82541GI_MOBILE:
906                 hw->mac_type = e1000_82541_rev_2;
907                 break;
908         case E1000_DEV_ID_82547EI:
909                 hw->mac_type = e1000_82547;
910                 break;
911         case E1000_DEV_ID_82547GI:
912                 hw->mac_type = e1000_82547_rev_2;
913                 break;
914         default:
915                 /* Should never have loaded on this device */
916                 return -E1000_ERR_MAC_TYPE;
917         }
918
919         return E1000_SUCCESS;
920 }
921
922 /*****************************************************************************
923  * Set media type and TBI compatibility.
924  *
925  * hw - Struct containing variables accessed by shared code
926  * **************************************************************************/
927 static void
928 e1000_set_media_type(struct e1000_hw *hw)
929 {
930         uint32_t status;
931
932         DEBUGFUNC("e1000_set_media_type");
933         
934         if(hw->mac_type != e1000_82543) {
935                 /* tbi_compatibility is only valid on 82543 */
936                 hw->tbi_compatibility_en = FALSE;
937         }
938
939         switch (hw->device_id) {
940                 case E1000_DEV_ID_82545GM_SERDES:
941                 case E1000_DEV_ID_82546GB_SERDES:
942                         hw->media_type = e1000_media_type_internal_serdes;
943                         break;
944                 default:
945                         if(hw->mac_type >= e1000_82543) {
946                                 status = E1000_READ_REG(hw, STATUS);
947                                 if(status & E1000_STATUS_TBIMODE) {
948                                         hw->media_type = e1000_media_type_fiber;
949                                         /* tbi_compatibility not valid on fiber */
950                                         hw->tbi_compatibility_en = FALSE;
951                                 } else {
952                                         hw->media_type = e1000_media_type_copper;
953                                 }
954                         } else {
955                                 /* This is an 82542 (fiber only) */
956                                 hw->media_type = e1000_media_type_fiber;
957                         }
958         }
959 }
960
961 /******************************************************************************
962  * Reset the transmit and receive units; mask and clear all interrupts.
963  *
964  * hw - Struct containing variables accessed by shared code
965  *****************************************************************************/
966 static void
967 e1000_reset_hw(struct e1000_hw *hw)
968 {
969         uint32_t ctrl;
970         uint32_t ctrl_ext;
971         uint32_t icr;
972         uint32_t manc;
973         
974         DEBUGFUNC("e1000_reset_hw");
975         
976         /* For 82542 (rev 2.0), disable MWI before issuing a device reset */
977         if(hw->mac_type == e1000_82542_rev2_0) {
978                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
979                 e1000_pci_clear_mwi(hw);
980         }
981
982         /* Clear interrupt mask to stop board from generating interrupts */
983         DEBUGOUT("Masking off all interrupts\n");
984         E1000_WRITE_REG(hw, IMC, 0xffffffff);
985         
986         /* Disable the Transmit and Receive units.  Then delay to allow
987          * any pending transactions to complete before we hit the MAC with
988          * the global reset.
989          */
990         E1000_WRITE_REG(hw, RCTL, 0);
991         E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
992         E1000_WRITE_FLUSH(hw);
993
994         /* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
995         hw->tbi_compatibility_on = FALSE;
996
997         /* Delay to allow any outstanding PCI transactions to complete before
998          * resetting the device
999          */ 
1000         mdelay(10);
1001
1002         ctrl = E1000_READ_REG(hw, CTRL);
1003
1004         /* Must reset the PHY before resetting the MAC */
1005         if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1006                 E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_PHY_RST));
1007                 mdelay(5);
1008         }
1009
1010         /* Issue a global reset to the MAC.  This will reset the chip's
1011          * transmit, receive, DMA, and link units.  It will not effect
1012          * the current PCI configuration.  The global reset bit is self-
1013          * clearing, and should clear within a microsecond.
1014          */
1015         DEBUGOUT("Issuing a global reset to MAC\n");
1016
1017         switch(hw->mac_type) {
1018                 case e1000_82544:
1019                 case e1000_82540:
1020                 case e1000_82545:
1021                 case e1000_82546:
1022                 case e1000_82541:
1023                 case e1000_82541_rev_2:
1024                         /* These controllers can't ack the 64-bit write when issuing the
1025                          * reset, so use IO-mapping as a workaround to issue the reset */
1026                         E1000_WRITE_REG_IO(hw, CTRL, (ctrl | E1000_CTRL_RST));
1027                         break;
1028                 case e1000_82545_rev_3:
1029                 case e1000_82546_rev_3:
1030                         /* Reset is performed on a shadow of the control register */
1031                         E1000_WRITE_REG(hw, CTRL_DUP, (ctrl | E1000_CTRL_RST));
1032                         break;
1033                 default:
1034                         E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));
1035                         break;
1036         }
1037
1038         /* After MAC reset, force reload of EEPROM to restore power-on settings to
1039          * device.  Later controllers reload the EEPROM automatically, so just wait
1040          * for reload to complete.
1041          */
1042         switch(hw->mac_type) {
1043                 case e1000_82542_rev2_0:
1044                 case e1000_82542_rev2_1:
1045                 case e1000_82543:
1046                 case e1000_82544:
1047                         /* Wait for reset to complete */
1048                         udelay(10);
1049                         ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1050                         ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1051                         E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1052                         E1000_WRITE_FLUSH(hw);
1053                         /* Wait for EEPROM reload */
1054                         mdelay(2);
1055                         break;
1056                 case e1000_82541:
1057                 case e1000_82541_rev_2:
1058                 case e1000_82547:
1059                 case e1000_82547_rev_2:
1060                         /* Wait for EEPROM reload */
1061                         mdelay(20);
1062                         break;
1063                 default:
1064                         /* Wait for EEPROM reload (it happens automatically) */
1065                         mdelay(5);
1066                         break;
1067         }
1068
1069         /* Disable HW ARPs on ASF enabled adapters */
1070         if(hw->mac_type >= e1000_82540) {
1071                 manc = E1000_READ_REG(hw, MANC);
1072                 manc &= ~(E1000_MANC_ARP_EN);
1073                 E1000_WRITE_REG(hw, MANC, manc);
1074         }
1075
1076         if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1077                 e1000_phy_init_script(hw);
1078         }
1079
1080         /* Clear interrupt mask to stop board from generating interrupts */
1081         DEBUGOUT("Masking off all interrupts\n");
1082         E1000_WRITE_REG(hw, IMC, 0xffffffff);
1083         
1084         /* Clear any pending interrupt events. */
1085         icr = E1000_READ_REG(hw, ICR);
1086
1087         /* If MWI was previously enabled, reenable it. */
1088         if(hw->mac_type == e1000_82542_rev2_0) {
1089 #ifdef LINUX_DRIVER
1090                 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1091 #endif
1092                         e1000_pci_set_mwi(hw);
1093         }
1094 }
1095
1096 /******************************************************************************
1097  * Performs basic configuration of the adapter.
1098  *
1099  * hw - Struct containing variables accessed by shared code
1100  * 
1101  * Assumes that the controller has previously been reset and is in a 
1102  * post-reset uninitialized state. Initializes the receive address registers,
1103  * multicast table, and VLAN filter table. Calls routines to setup link
1104  * configuration and flow control settings. Clears all on-chip counters. Leaves
1105  * the transmit and receive units disabled and uninitialized.
1106  *****************************************************************************/
1107 static int
1108 e1000_init_hw(struct e1000_hw *hw)
1109 {
1110         uint32_t ctrl, status;
1111         uint32_t i;
1112         int32_t ret_val;
1113         uint16_t pcix_cmd_word;
1114         uint16_t pcix_stat_hi_word;
1115         uint16_t cmd_mmrbc;
1116         uint16_t stat_mmrbc;
1117         e1000_bus_type bus_type = e1000_bus_type_unknown;
1118
1119         DEBUGFUNC("e1000_init_hw");
1120
1121         /* Set the media type and TBI compatibility */
1122         e1000_set_media_type(hw);
1123
1124         /* Disabling VLAN filtering. */
1125         DEBUGOUT("Initializing the IEEE VLAN\n");
1126         E1000_WRITE_REG(hw, VET, 0);
1127         
1128         e1000_clear_vfta(hw);
1129         
1130         /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
1131         if(hw->mac_type == e1000_82542_rev2_0) {
1132                 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
1133                 e1000_pci_clear_mwi(hw);
1134                 E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
1135                 E1000_WRITE_FLUSH(hw);
1136                 mdelay(5);
1137         }
1138         
1139         /* Setup the receive address. This involves initializing all of the Receive
1140          * Address Registers (RARs 0 - 15).
1141          */
1142         e1000_init_rx_addrs(hw);
1143         
1144         /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
1145         if(hw->mac_type == e1000_82542_rev2_0) {
1146                 E1000_WRITE_REG(hw, RCTL, 0);
1147                 E1000_WRITE_FLUSH(hw);
1148                 mdelay(1);
1149 #ifdef LINUX_DRIVER
1150                 if(hw->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
1151 #endif
1152                         e1000_pci_set_mwi(hw);
1153         }
1154         
1155         /* Zero out the Multicast HASH table */
1156         DEBUGOUT("Zeroing the MTA\n");
1157         for(i = 0; i < E1000_MC_TBL_SIZE; i++)
1158                 E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
1159         
1160 #if 0
1161         /* Set the PCI priority bit correctly in the CTRL register.  This
1162          * determines if the adapter gives priority to receives, or if it
1163          * gives equal priority to transmits and receives.
1164          */
1165         if(hw->dma_fairness) {
1166                 ctrl = E1000_READ_REG(hw, CTRL);
1167                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PRIOR);
1168         }
1169 #endif
1170
1171         switch(hw->mac_type) {
1172                 case e1000_82545_rev_3:
1173                 case e1000_82546_rev_3:
1174                         break;
1175                 default:
1176                         if (hw->mac_type >= e1000_82543) {
1177                                 /* See e1000_get_bus_info() of the Linux driver */
1178                                 status = E1000_READ_REG(hw, STATUS);
1179                                 bus_type = (status & E1000_STATUS_PCIX_MODE) ?
1180                                         e1000_bus_type_pcix : e1000_bus_type_pci;
1181                         }
1182
1183                         /* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
1184                         if(bus_type == e1000_bus_type_pcix) {
1185                                 pci_read_config_word(hw->pdev, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
1186                                 pci_read_config_word(hw->pdev, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
1187                                 cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1188                                         PCIX_COMMAND_MMRBC_SHIFT;
1189                                 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1190                                         PCIX_STATUS_HI_MMRBC_SHIFT;
1191                                 if(stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1192                                         stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1193                                 if(cmd_mmrbc > stat_mmrbc) {
1194                                         pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1195                                         pcix_cmd_word |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1196                                         pci_write_config_word(hw->pdev, PCIX_COMMAND_REGISTER, pcix_cmd_word);
1197                                 }
1198                         }
1199                         break;
1200         }
1201
1202         /* Call a subroutine to configure the link and setup flow control. */
1203         ret_val = e1000_setup_link(hw);
1204         
1205         /* Set the transmit descriptor write-back policy */
1206         if(hw->mac_type > e1000_82544) {
1207                 ctrl = E1000_READ_REG(hw, TXDCTL);
1208                 ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) | E1000_TXDCTL_FULL_TX_DESC_WB;
1209                 E1000_WRITE_REG(hw, TXDCTL, ctrl);
1210         }
1211
1212 #if 0
1213         /* Clear all of the statistics registers (clear on read).  It is
1214          * important that we do this after we have tried to establish link
1215          * because the symbol error count will increment wildly if there
1216          * is no link.
1217          */
1218         e1000_clear_hw_cntrs(hw);
1219 #endif
1220
1221         return ret_val;
1222 }
1223
1224 /******************************************************************************
1225  * Adjust SERDES output amplitude based on EEPROM setting.
1226  *
1227  * hw - Struct containing variables accessed by shared code.
1228  *****************************************************************************/
1229 static int32_t
1230 e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
1231 {
1232         uint16_t eeprom_data;
1233         int32_t  ret_val;
1234
1235         DEBUGFUNC("e1000_adjust_serdes_amplitude");
1236
1237         if(hw->media_type != e1000_media_type_internal_serdes)
1238                 return E1000_SUCCESS;
1239
1240         switch(hw->mac_type) {
1241                 case e1000_82545_rev_3:
1242                 case e1000_82546_rev_3:
1243                         break;
1244                 default:
1245                         return E1000_SUCCESS;
1246         }
1247
1248         if ((ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1,
1249                                         &eeprom_data))) {
1250                 return ret_val;
1251         }
1252
1253         if(eeprom_data != EEPROM_RESERVED_WORD) {
1254                 /* Adjust SERDES output amplitude only. */
1255                 eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
1256                 if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL,
1257                                                   eeprom_data)))
1258                         return ret_val;
1259         }
1260
1261         return E1000_SUCCESS;
1262 }
1263                                                                    
1264 /******************************************************************************
1265  * Configures flow control and link settings.
1266  * 
1267  * hw - Struct containing variables accessed by shared code
1268  * 
1269  * Determines which flow control settings to use. Calls the apropriate media-
1270  * specific link configuration function. Configures the flow control settings.
1271  * Assuming the adapter has a valid link partner, a valid link should be
1272  * established. Assumes the hardware has previously been reset and the 
1273  * transmitter and receiver are not enabled.
1274  *****************************************************************************/
1275 static int
1276 e1000_setup_link(struct e1000_hw *hw)
1277 {
1278         uint32_t ctrl_ext;
1279         int32_t ret_val;
1280         uint16_t eeprom_data;
1281
1282         DEBUGFUNC("e1000_setup_link");
1283         
1284         /* Read and store word 0x0F of the EEPROM. This word contains bits
1285          * that determine the hardware's default PAUSE (flow control) mode,
1286          * a bit that determines whether the HW defaults to enabling or
1287          * disabling auto-negotiation, and the direction of the
1288          * SW defined pins. If there is no SW over-ride of the flow
1289          * control setting, then the variable hw->fc will
1290          * be initialized based on a value in the EEPROM.
1291          */
1292         if(e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG, 1, &eeprom_data) < 0) {
1293                 DEBUGOUT("EEPROM Read Error\n");
1294                 return -E1000_ERR_EEPROM;
1295         }
1296         
1297         if(hw->fc == e1000_fc_default) {
1298                 if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1299                         hw->fc = e1000_fc_none;
1300                 else if((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 
1301                         EEPROM_WORD0F_ASM_DIR)
1302                         hw->fc = e1000_fc_tx_pause;
1303                 else
1304                         hw->fc = e1000_fc_full;
1305         }
1306         
1307         /* We want to save off the original Flow Control configuration just
1308          * in case we get disconnected and then reconnected into a different
1309          * hub or switch with different Flow Control capabilities.
1310          */
1311         if(hw->mac_type == e1000_82542_rev2_0)
1312                 hw->fc &= (~e1000_fc_tx_pause);
1313
1314 #if 0
1315         /* See e1000_sw_init() of the Linux driver */
1316         if((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1317 #else
1318         if((hw->mac_type < e1000_82543) && (hw->mac_type >= e1000_82543))
1319 #endif
1320                 hw->fc &= (~e1000_fc_rx_pause);
1321         
1322 #if 0
1323         hw->original_fc = hw->fc;
1324 #endif
1325
1326         DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1327         
1328         /* Take the 4 bits from EEPROM word 0x0F that determine the initial
1329          * polarity value for the SW controlled pins, and setup the
1330          * Extended Device Control reg with that info.
1331          * This is needed because one of the SW controlled pins is used for
1332          * signal detection.  So this should be done before e1000_setup_pcs_link()
1333          * or e1000_phy_setup() is called.
1334          */
1335         if(hw->mac_type == e1000_82543) {
1336                 ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) << 
1337                         SWDPIO__EXT_SHIFT);
1338                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1339         }
1340         
1341         /* Call the necessary subroutine to configure the link. */
1342         ret_val = (hw->media_type == e1000_media_type_copper) ?
1343                 e1000_setup_copper_link(hw) :
1344                 e1000_setup_fiber_serdes_link(hw);
1345         if (ret_val < 0) {
1346                 return ret_val;
1347         }
1348         
1349         /* Initialize the flow control address, type, and PAUSE timer
1350          * registers to their default values.  This is done even if flow
1351          * control is disabled, because it does not hurt anything to
1352          * initialize these registers.
1353          */
1354         DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1355         
1356         E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1357         E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1358         E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1359 #if 0
1360         E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1361 #else
1362         E1000_WRITE_REG(hw, FCTTV, FC_DEFAULT_TX_TIMER);
1363 #endif
1364         
1365         /* Set the flow control receive threshold registers.  Normally,
1366          * these registers will be set to a default threshold that may be
1367          * adjusted later by the driver's runtime code.  However, if the
1368          * ability to transmit pause frames in not enabled, then these
1369          * registers will be set to 0. 
1370          */
1371         if(!(hw->fc & e1000_fc_tx_pause)) {
1372                 E1000_WRITE_REG(hw, FCRTL, 0);
1373                 E1000_WRITE_REG(hw, FCRTH, 0);
1374         } else {
1375                 /* We need to set up the Receive Threshold high and low water marks
1376                  * as well as (optionally) enabling the transmission of XON frames.
1377                  */
1378 #if 0
1379                 if(hw->fc_send_xon) {
1380                         E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water | E1000_FCRTL_XONE));
1381                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1382                 } else {
1383                         E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1384                         E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1385                 }
1386 #else
1387                 E1000_WRITE_REG(hw, FCRTL, (FC_DEFAULT_LO_THRESH | E1000_FCRTL_XONE));
1388                 E1000_WRITE_REG(hw, FCRTH, FC_DEFAULT_HI_THRESH);
1389 #endif
1390         }
1391         return ret_val;
1392 }
1393
1394 /******************************************************************************
1395  * Sets up link for a fiber based or serdes based adapter
1396  *
1397  * hw - Struct containing variables accessed by shared code
1398  *
1399  * Manipulates Physical Coding Sublayer functions in order to configure
1400  * link. Assumes the hardware has been previously reset and the transmitter
1401  * and receiver are not enabled.
1402  *****************************************************************************/
1403 static int
1404 e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1405 {
1406         uint32_t ctrl;
1407         uint32_t status;
1408         uint32_t txcw = 0;
1409         uint32_t i;
1410         uint32_t signal = 0;
1411         int32_t ret_val;
1412
1413         DEBUGFUNC("e1000_setup_fiber_serdes_link");
1414
1415         /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 
1416          * set when the optics detect a signal. On older adapters, it will be 
1417          * cleared when there is a signal.  This applies to fiber media only.
1418          * If we're on serdes media, adjust the output amplitude to value set in
1419          * the EEPROM.
1420          */
1421         ctrl = E1000_READ_REG(hw, CTRL);
1422         if(hw->media_type == e1000_media_type_fiber)
1423                 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1424
1425         if((ret_val = e1000_adjust_serdes_amplitude(hw)))
1426                 return ret_val;
1427
1428         /* Take the link out of reset */
1429         ctrl &= ~(E1000_CTRL_LRST);
1430
1431 #if 0
1432         /* Adjust VCO speed to improve BER performance */
1433         if((ret_val = e1000_set_vco_speed(hw)))
1434                 return ret_val;
1435 #endif
1436
1437         e1000_config_collision_dist(hw);
1438         
1439         /* Check for a software override of the flow control settings, and setup
1440          * the device accordingly.  If auto-negotiation is enabled, then software
1441          * will have to set the "PAUSE" bits to the correct value in the Tranmsit
1442          * Config Word Register (TXCW) and re-start auto-negotiation.  However, if
1443          * auto-negotiation is disabled, then software will have to manually 
1444          * configure the two flow control enable bits in the CTRL register.
1445          *
1446          * The possible values of the "fc" parameter are:
1447          *      0:  Flow control is completely disabled
1448          *      1:  Rx flow control is enabled (we can receive pause frames, but 
1449          *          not send pause frames).
1450          *      2:  Tx flow control is enabled (we can send pause frames but we do
1451          *          not support receiving pause frames).
1452          *      3:  Both Rx and TX flow control (symmetric) are enabled.
1453          */
1454         switch (hw->fc) {
1455         case e1000_fc_none:
1456                 /* Flow control is completely disabled by a software over-ride. */
1457                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1458                 break;
1459         case e1000_fc_rx_pause:
1460                 /* RX Flow control is enabled and TX Flow control is disabled by a 
1461                  * software over-ride. Since there really isn't a way to advertise 
1462                  * that we are capable of RX Pause ONLY, we will advertise that we
1463                  * support both symmetric and asymmetric RX PAUSE. Later, we will
1464                  *  disable the adapter's ability to send PAUSE frames.
1465                  */
1466                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1467                 break;
1468         case e1000_fc_tx_pause:
1469                 /* TX Flow control is enabled, and RX Flow control is disabled, by a 
1470                  * software over-ride.
1471                  */
1472                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1473                 break;
1474         case e1000_fc_full:
1475                 /* Flow control (both RX and TX) is enabled by a software over-ride. */
1476                 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1477                 break;
1478         default:
1479                 DEBUGOUT("Flow control param set incorrectly\n");
1480                 return -E1000_ERR_CONFIG;
1481                 break;
1482         }
1483         
1484         /* Since auto-negotiation is enabled, take the link out of reset (the link
1485          * will be in reset, because we previously reset the chip). This will
1486          * restart auto-negotiation.  If auto-neogtiation is successful then the
1487          * link-up status bit will be set and the flow control enable bits (RFCE
1488          * and TFCE) will be set according to their negotiated value.
1489          */
1490         DEBUGOUT("Auto-negotiation enabled\n");
1491         
1492         E1000_WRITE_REG(hw, TXCW, txcw);
1493         E1000_WRITE_REG(hw, CTRL, ctrl);
1494         E1000_WRITE_FLUSH(hw);
1495         
1496         hw->txcw = txcw;
1497         mdelay(1);
1498         
1499         /* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1500          * indication in the Device Status Register.  Time-out if a link isn't 
1501          * seen in 500 milliseconds seconds (Auto-negotiation should complete in 
1502          * less than 500 milliseconds even if the other end is doing it in SW).
1503          * For internal serdes, we just assume a signal is present, then poll.
1504          */
1505         if(hw->media_type == e1000_media_type_internal_serdes ||
1506            (E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1507                 DEBUGOUT("Looking for Link\n");
1508                 for(i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1509                         mdelay(10);
1510                         status = E1000_READ_REG(hw, STATUS);
1511                         if(status & E1000_STATUS_LU) break;
1512                 }
1513                 if(i == (LINK_UP_TIMEOUT / 10)) {
1514                         DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1515                         hw->autoneg_failed = 1;
1516                         /* AutoNeg failed to achieve a link, so we'll call 
1517                          * e1000_check_for_link. This routine will force the link up if
1518                          * we detect a signal. This will allow us to communicate with
1519                          * non-autonegotiating link partners.
1520                          */
1521                         if((ret_val = e1000_check_for_link(hw))) {
1522                                 DEBUGOUT("Error while checking for link\n");
1523                                 return ret_val;
1524                         }
1525                         hw->autoneg_failed = 0;
1526                 } else {
1527                         hw->autoneg_failed = 0;
1528                         DEBUGOUT("Valid Link Found\n");
1529                 }
1530         } else {
1531                 DEBUGOUT("No Signal Detected\n");
1532         }
1533         return E1000_SUCCESS;
1534 }
1535
1536 /******************************************************************************
1537 * Detects which PHY is present and the speed and duplex
1538 *
1539 * hw - Struct containing variables accessed by shared code
1540 ******************************************************************************/
1541 static int
1542 e1000_setup_copper_link(struct e1000_hw *hw)
1543 {
1544         uint32_t ctrl;
1545         int32_t ret_val;
1546         uint16_t i;
1547         uint16_t phy_data;
1548         
1549         DEBUGFUNC("e1000_setup_copper_link");
1550         
1551         ctrl = E1000_READ_REG(hw, CTRL);
1552         /* With 82543, we need to force speed and duplex on the MAC equal to what
1553          * the PHY speed and duplex configuration is. In addition, we need to
1554          * perform a hardware reset on the PHY to take it out of reset.
1555          */
1556         if(hw->mac_type > e1000_82543) {
1557                 ctrl |= E1000_CTRL_SLU;
1558                 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1559                 E1000_WRITE_REG(hw, CTRL, ctrl);
1560         } else {
1561                 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX | E1000_CTRL_SLU);
1562                 E1000_WRITE_REG(hw, CTRL, ctrl);
1563                 e1000_phy_hw_reset(hw);
1564         }
1565         
1566         /* Make sure we have a valid PHY */
1567         if((ret_val = e1000_detect_gig_phy(hw))) {
1568                 DEBUGOUT("Error, did not detect valid phy.\n");
1569                 return ret_val;
1570         }
1571         DEBUGOUT1("Phy ID = %x \n", hw->phy_id);
1572
1573         if(hw->mac_type <= e1000_82543 ||
1574            hw->mac_type == e1000_82541 || hw->mac_type == e1000_82547 ||
1575 #if 0
1576            hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2)
1577                 hw->phy_reset_disable = FALSE;
1578
1579         if(!hw->phy_reset_disable) {
1580 #else
1581            hw->mac_type == e1000_82541_rev_2 || hw->mac_type == e1000_82547_rev_2) {
1582 #endif
1583         if (hw->phy_type == e1000_phy_igp) {
1584
1585                 if((ret_val = e1000_phy_reset(hw))) {
1586                         DEBUGOUT("Error Resetting the PHY\n");
1587                         return ret_val;
1588                 }
1589
1590                 /* Wait 10ms for MAC to configure PHY from eeprom settings */
1591                 mdelay(15);
1592
1593 #if 0
1594                 /* disable lplu d3 during driver init */
1595                 if((ret_val = e1000_set_d3_lplu_state(hw, FALSE))) {
1596                         DEBUGOUT("Error Disabling LPLU D3\n");
1597                         return ret_val;
1598                 }
1599
1600                 /* Configure mdi-mdix settings */
1601                 if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1602                                                  &phy_data)))
1603                         return ret_val;
1604
1605                 if((hw->mac_type == e1000_82541) || (hw->mac_type == e1000_82547)) {
1606                         hw->dsp_config_state = e1000_dsp_config_disabled;
1607                         /* Force MDI for IGP B-0 PHY */
1608                         phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX |
1609                                       IGP01E1000_PSCR_FORCE_MDI_MDIX);
1610                         hw->mdix = 1;
1611
1612                 } else {
1613                         hw->dsp_config_state = e1000_dsp_config_enabled;
1614                         phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1615
1616                         switch (hw->mdix) {
1617                         case 1:
1618                                 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1619                                 break;
1620                         case 2:
1621                                 phy_data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1622                                 break;
1623                         case 0:
1624                         default:
1625                                 phy_data |= IGP01E1000_PSCR_AUTO_MDIX;
1626                                 break;
1627                         }
1628                 }
1629                 if((ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL,
1630                                                   phy_data)))
1631                         return ret_val;
1632
1633                 /* set auto-master slave resolution settings */
1634                 e1000_ms_type phy_ms_setting = hw->master_slave;
1635
1636                 if(hw->ffe_config_state == e1000_ffe_config_active)
1637                         hw->ffe_config_state = e1000_ffe_config_enabled;
1638
1639                 if(hw->dsp_config_state == e1000_dsp_config_activated)
1640                         hw->dsp_config_state = e1000_dsp_config_enabled;
1641 #endif
1642
1643                 /* when autonegotiation advertisment is only 1000Mbps then we
1644                  * should disable SmartSpeed and enable Auto MasterSlave
1645                  * resolution as hardware default. */
1646                 if(hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1647                         /* Disable SmartSpeed */
1648                         if((ret_val = e1000_read_phy_reg(hw,
1649                                                          IGP01E1000_PHY_PORT_CONFIG,
1650                                                          &phy_data)))
1651                                 return ret_val;
1652                         phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1653                         if((ret_val = e1000_write_phy_reg(hw,
1654                                                           IGP01E1000_PHY_PORT_CONFIG,
1655                                                           phy_data)))
1656                                 return ret_val;
1657                         /* Set auto Master/Slave resolution process */
1658                         if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
1659                                                          &phy_data)))
1660                                 return ret_val;
1661                         phy_data &= ~CR_1000T_MS_ENABLE;
1662                         if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1663                                                           phy_data)))
1664                                 return ret_val;
1665                 }
1666
1667                 if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL,
1668                                                  &phy_data)))
1669                         return ret_val;
1670
1671 #if 0
1672                 /* load defaults for future use */
1673                 hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1674                                             ((phy_data & CR_1000T_MS_VALUE) ?
1675                                              e1000_ms_force_master :
1676                                              e1000_ms_force_slave) :
1677                                              e1000_ms_auto;
1678
1679                 switch (phy_ms_setting) {
1680                 case e1000_ms_force_master:
1681                         phy_data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1682                         break;
1683                 case e1000_ms_force_slave:
1684                         phy_data |= CR_1000T_MS_ENABLE;
1685                         phy_data &= ~(CR_1000T_MS_VALUE);
1686                         break;
1687                 case e1000_ms_auto:
1688                         phy_data &= ~CR_1000T_MS_ENABLE;
1689                 default:
1690                         break;
1691                 }
1692 #endif
1693
1694                 if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL,
1695                                                   phy_data)))
1696                         return ret_val;
1697         } else {
1698                 /* Enable CRS on TX. This must be set for half-duplex operation. */
1699                 if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1700                                                  &phy_data)))
1701                         return ret_val;
1702
1703                 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1704
1705                 /* Options:
1706                  *   MDI/MDI-X = 0 (default)
1707                  *   0 - Auto for all speeds
1708                  *   1 - MDI mode
1709                  *   2 - MDI-X mode
1710                  *   3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1711                  */
1712 #if 0
1713                 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1714
1715                 switch (hw->mdix) {
1716                 case 1:
1717                         phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
1718                         break;
1719                 case 2:
1720                         phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
1721                         break;
1722                 case 3:
1723                         phy_data |= M88E1000_PSCR_AUTO_X_1000T;
1724                         break;
1725                 case 0:
1726                 default:
1727 #endif
1728                         phy_data |= M88E1000_PSCR_AUTO_X_MODE;
1729 #if 0
1730                         break;
1731                 }
1732 #endif
1733
1734                 /* Options:
1735                  *   disable_polarity_correction = 0 (default)
1736                  *       Automatic Correction for Reversed Cable Polarity
1737                  *   0 - Disabled
1738                  *   1 - Enabled
1739                  */
1740                 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1741                 if((ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL,
1742                                                   phy_data)))
1743                         return ret_val;
1744
1745                 /* Force TX_CLK in the Extended PHY Specific Control Register
1746                  * to 25MHz clock.
1747                  */
1748                 if((ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
1749                                                  &phy_data)))
1750                         return ret_val;
1751
1752                 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1753
1754 #ifdef LINUX_DRIVER
1755                 if (hw->phy_revision < M88E1011_I_REV_4) {
1756 #endif
1757                         /* Configure Master and Slave downshift values */
1758                         phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
1759                                 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1760                         phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
1761                                 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1762                         if((ret_val = e1000_write_phy_reg(hw,
1763                                                           M88E1000_EXT_PHY_SPEC_CTRL,
1764                                                           phy_data)))
1765                                 return ret_val;
1766                 }
1767         
1768                 /* SW Reset the PHY so all changes take effect */
1769                 if((ret_val = e1000_phy_reset(hw))) {
1770                         DEBUGOUT("Error Resetting the PHY\n");
1771                         return ret_val;
1772 #ifdef LINUX_DRIVER
1773                 }
1774 #endif
1775         }
1776         
1777         /* Options:
1778          *   autoneg = 1 (default)
1779          *      PHY will advertise value(s) parsed from
1780          *      autoneg_advertised and fc
1781          *   autoneg = 0
1782          *      PHY will be set to 10H, 10F, 100H, or 100F
1783          *      depending on value parsed from forced_speed_duplex.
1784          */
1785         
1786         /* Is autoneg enabled?  This is enabled by default or by software
1787          * override.  If so, call e1000_phy_setup_autoneg routine to parse the
1788          * autoneg_advertised and fc options. If autoneg is NOT enabled, then
1789          * the user should have provided a speed/duplex override.  If so, then
1790          * call e1000_phy_force_speed_duplex to parse and set this up.
1791          */
1792         /* Perform some bounds checking on the hw->autoneg_advertised
1793          * parameter.  If this variable is zero, then set it to the default.
1794          */
1795         hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1796         
1797         /* If autoneg_advertised is zero, we assume it was not defaulted
1798          * by the calling code so we set to advertise full capability.
1799          */
1800         if(hw->autoneg_advertised == 0)
1801                 hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1802         
1803         DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1804         if((ret_val = e1000_phy_setup_autoneg(hw))) {
1805                 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1806                 return ret_val;
1807         }
1808         DEBUGOUT("Restarting Auto-Neg\n");
1809         
1810         /* Restart auto-negotiation by setting the Auto Neg Enable bit and
1811          * the Auto Neg Restart bit in the PHY control register.
1812          */
1813         if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
1814                 return ret_val;
1815
1816         phy_data |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1817         if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
1818                 return ret_val;
1819
1820 #if 0   
1821         /* Does the user want to wait for Auto-Neg to complete here, or
1822          * check at a later time (for example, callback routine).
1823          */
1824         if(hw->wait_autoneg_complete) {
1825                 if((ret_val = e1000_wait_autoneg(hw))) {
1826                         DEBUGOUT("Error while waiting for autoneg to complete\n");
1827                         return ret_val;
1828                 }
1829         }
1830 #else
1831         /* If we do not wait for autonegotiation to complete I 
1832          * do not see a valid link status.
1833          */
1834         if((ret_val = e1000_wait_autoneg(hw))) {
1835                 DEBUGOUT("Error while waiting for autoneg to complete\n");
1836                 return ret_val;
1837         }
1838 #endif
1839         } /* !hw->phy_reset_disable */
1840         
1841         /* Check link status. Wait up to 100 microseconds for link to become
1842          * valid.
1843          */
1844         for(i = 0; i < 10; i++) {
1845                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1846                         return ret_val;
1847                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
1848                         return ret_val;
1849
1850                 if(phy_data & MII_SR_LINK_STATUS) {
1851                         /* We have link, so we need to finish the config process:
1852                          *   1) Set up the MAC to the current PHY speed/duplex
1853                          *      if we are on 82543.  If we
1854                          *      are on newer silicon, we only need to configure
1855                          *      collision distance in the Transmit Control Register.
1856                          *   2) Set up flow control on the MAC to that established with
1857                          *      the link partner.
1858                          */
1859                         if(hw->mac_type >= e1000_82544) {
1860                                 e1000_config_collision_dist(hw);
1861                         } else {
1862                                 if((ret_val = e1000_config_mac_to_phy(hw))) {
1863                                         DEBUGOUT("Error configuring MAC to PHY settings\n");
1864                                         return ret_val;
1865                                 }
1866                         }
1867                         if((ret_val = e1000_config_fc_after_link_up(hw))) {
1868                                 DEBUGOUT("Error Configuring Flow Control\n");
1869                                 return ret_val;
1870                         }
1871 #if 0
1872                         if(hw->phy_type == e1000_phy_igp) {
1873                                 if((ret_val = e1000_config_dsp_after_link_change(hw, TRUE))) {
1874                                         DEBUGOUT("Error Configuring DSP after link up\n");
1875                                         return ret_val;
1876                                 }
1877                         }
1878 #endif
1879                         DEBUGOUT("Valid link established!!!\n");
1880                         return E1000_SUCCESS;
1881                 }
1882                 udelay(10);
1883         }
1884         
1885         DEBUGOUT("Unable to establish link!!!\n");
1886         return -E1000_ERR_NOLINK;
1887 }
1888
1889 /******************************************************************************
1890 * Configures PHY autoneg and flow control advertisement settings
1891 *
1892 * hw - Struct containing variables accessed by shared code
1893 ******************************************************************************/
1894 static int
1895 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1896 {
1897         int32_t ret_val;
1898         uint16_t mii_autoneg_adv_reg;
1899         uint16_t mii_1000t_ctrl_reg;
1900
1901         DEBUGFUNC("e1000_phy_setup_autoneg");
1902         
1903         /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1904         if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
1905                                          &mii_autoneg_adv_reg)))
1906                 return ret_val;
1907
1908         /* Read the MII 1000Base-T Control Register (Address 9). */
1909         if((ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg)))
1910                 return ret_val;
1911
1912         /* Need to parse both autoneg_advertised and fc and set up
1913          * the appropriate PHY registers.  First we will parse for
1914          * autoneg_advertised software override.  Since we can advertise
1915          * a plethora of combinations, we need to check each bit
1916          * individually.
1917          */
1918         
1919         /* First we clear all the 10/100 mb speed bits in the Auto-Neg
1920          * Advertisement Register (Address 4) and the 1000 mb speed bits in
1921          * the  1000Base-T Control Register (Address 9).
1922          */
1923         mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
1924         mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
1925
1926         DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
1927
1928         /* Do we want to advertise 10 Mb Half Duplex? */
1929         if(hw->autoneg_advertised & ADVERTISE_10_HALF) {
1930                 DEBUGOUT("Advertise 10mb Half duplex\n");
1931                 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1932         }
1933
1934         /* Do we want to advertise 10 Mb Full Duplex? */
1935         if(hw->autoneg_advertised & ADVERTISE_10_FULL) {
1936                 DEBUGOUT("Advertise 10mb Full duplex\n");
1937                 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1938         }
1939
1940         /* Do we want to advertise 100 Mb Half Duplex? */
1941         if(hw->autoneg_advertised & ADVERTISE_100_HALF) {
1942                 DEBUGOUT("Advertise 100mb Half duplex\n");
1943                 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1944         }
1945
1946         /* Do we want to advertise 100 Mb Full Duplex? */
1947         if(hw->autoneg_advertised & ADVERTISE_100_FULL) {
1948                 DEBUGOUT("Advertise 100mb Full duplex\n");
1949                 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1950         }
1951
1952         /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1953         if(hw->autoneg_advertised & ADVERTISE_1000_HALF) {
1954                 DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
1955         }
1956
1957         /* Do we want to advertise 1000 Mb Full Duplex? */
1958         if(hw->autoneg_advertised & ADVERTISE_1000_FULL) {
1959                 DEBUGOUT("Advertise 1000mb Full duplex\n");
1960                 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1961         }
1962
1963         /* Check for a software override of the flow control settings, and
1964          * setup the PHY advertisement registers accordingly.  If
1965          * auto-negotiation is enabled, then software will have to set the
1966          * "PAUSE" bits to the correct value in the Auto-Negotiation
1967          * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
1968          *
1969          * The possible values of the "fc" parameter are:
1970          *      0:  Flow control is completely disabled
1971          *      1:  Rx flow control is enabled (we can receive pause frames
1972          *          but not send pause frames).
1973          *      2:  Tx flow control is enabled (we can send pause frames
1974          *          but we do not support receiving pause frames).
1975          *      3:  Both Rx and TX flow control (symmetric) are enabled.
1976          *  other:  No software override.  The flow control configuration
1977          *          in the EEPROM is used.
1978          */
1979         switch (hw->fc) {
1980         case e1000_fc_none: /* 0 */
1981                 /* Flow control (RX & TX) is completely disabled by a
1982                  * software over-ride.
1983                  */
1984                 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1985                 break;
1986         case e1000_fc_rx_pause: /* 1 */
1987                 /* RX Flow control is enabled, and TX Flow control is
1988                  * disabled, by a software over-ride.
1989                  */
1990                 /* Since there really isn't a way to advertise that we are
1991                  * capable of RX Pause ONLY, we will advertise that we
1992                  * support both symmetric and asymmetric RX PAUSE.  Later
1993                  * (in e1000_config_fc_after_link_up) we will disable the
1994                  *hw's ability to send PAUSE frames.
1995                  */
1996                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1997                 break;
1998         case e1000_fc_tx_pause: /* 2 */
1999                 /* TX Flow control is enabled, and RX Flow control is
2000                  * disabled, by a software over-ride.
2001                  */
2002                 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
2003                 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
2004                 break;
2005         case e1000_fc_full: /* 3 */
2006                 /* Flow control (both RX and TX) is enabled by a software
2007                  * over-ride.
2008                  */
2009                 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
2010                 break;
2011         default:
2012                 DEBUGOUT("Flow control param set incorrectly\n");
2013                 return -E1000_ERR_CONFIG;
2014         }
2015
2016         if((ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV,
2017                                mii_autoneg_adv_reg)))
2018                 return ret_val;
2019
2020         DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
2021
2022         if((ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg)))
2023                 return ret_val;
2024
2025         return E1000_SUCCESS;
2026 }
2027
2028 /******************************************************************************
2029 * Sets the collision distance in the Transmit Control register
2030 *
2031 * hw - Struct containing variables accessed by shared code
2032 *
2033 * Link should have been established previously. Reads the speed and duplex
2034 * information from the Device Status register.
2035 ******************************************************************************/
2036 static void
2037 e1000_config_collision_dist(struct e1000_hw *hw)
2038 {
2039         uint32_t tctl;
2040
2041         tctl = E1000_READ_REG(hw, TCTL);
2042         
2043         tctl &= ~E1000_TCTL_COLD;
2044         tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
2045         
2046         E1000_WRITE_REG(hw, TCTL, tctl);
2047         E1000_WRITE_FLUSH(hw);
2048 }
2049
2050 /******************************************************************************
2051 * Sets MAC speed and duplex settings to reflect the those in the PHY
2052 *
2053 * hw - Struct containing variables accessed by shared code
2054 * mii_reg - data to write to the MII control register
2055 *
2056 * The contents of the PHY register containing the needed information need to
2057 * be passed in.
2058 ******************************************************************************/
2059 static int
2060 e1000_config_mac_to_phy(struct e1000_hw *hw)
2061 {
2062         uint32_t ctrl;
2063         int32_t ret_val;
2064         uint16_t phy_data;
2065
2066         DEBUGFUNC("e1000_config_mac_to_phy");
2067
2068         /* Read the Device Control Register and set the bits to Force Speed
2069          * and Duplex.
2070          */
2071         ctrl = E1000_READ_REG(hw, CTRL);
2072         ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
2073         ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
2074
2075         /* Set up duplex in the Device Control and Transmit Control
2076          * registers depending on negotiated values.
2077          */
2078         if (hw->phy_type == e1000_phy_igp) {
2079                 if((ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
2080                                                  &phy_data)))
2081                         return ret_val;
2082
2083                 if(phy_data & IGP01E1000_PSSR_FULL_DUPLEX) ctrl |= E1000_CTRL_FD;
2084                 else ctrl &= ~E1000_CTRL_FD;
2085
2086                 e1000_config_collision_dist(hw);
2087
2088                 /* Set up speed in the Device Control register depending on
2089                  * negotiated values.
2090                  */
2091                 if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
2092                    IGP01E1000_PSSR_SPEED_1000MBPS)
2093                         ctrl |= E1000_CTRL_SPD_1000;
2094                 else if((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
2095                         IGP01E1000_PSSR_SPEED_100MBPS)
2096                         ctrl |= E1000_CTRL_SPD_100;
2097         } else {
2098                 if((ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
2099                                                  &phy_data)))
2100                         return ret_val;
2101                 
2102                 if(phy_data & M88E1000_PSSR_DPLX) ctrl |= E1000_CTRL_FD;
2103                 else ctrl &= ~E1000_CTRL_FD;
2104
2105                 e1000_config_collision_dist(hw);
2106
2107                 /* Set up speed in the Device Control register depending on
2108                  * negotiated values.
2109                  */
2110                 if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2111                         ctrl |= E1000_CTRL_SPD_1000;
2112                 else if((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2113                         ctrl |= E1000_CTRL_SPD_100;
2114         }
2115         /* Write the configured values back to the Device Control Reg. */
2116         E1000_WRITE_REG(hw, CTRL, ctrl);
2117         return E1000_SUCCESS;
2118 }
2119
2120 /******************************************************************************
2121  * Forces the MAC's flow control settings.
2122  * 
2123  * hw - Struct containing variables accessed by shared code
2124  *
2125  * Sets the TFCE and RFCE bits in the device control register to reflect
2126  * the adapter settings. TFCE and RFCE need to be explicitly set by
2127  * software when a Copper PHY is used because autonegotiation is managed
2128  * by the PHY rather than the MAC. Software must also configure these
2129  * bits when link is forced on a fiber connection.
2130  *****************************************************************************/
2131 static int
2132 e1000_force_mac_fc(struct e1000_hw *hw)
2133 {
2134         uint32_t ctrl;
2135         
2136         DEBUGFUNC("e1000_force_mac_fc");
2137         
2138         /* Get the current configuration of the Device Control Register */
2139         ctrl = E1000_READ_REG(hw, CTRL);
2140         
2141         /* Because we didn't get link via the internal auto-negotiation
2142          * mechanism (we either forced link or we got link via PHY
2143          * auto-neg), we have to manually enable/disable transmit an
2144          * receive flow control.
2145          *
2146          * The "Case" statement below enables/disable flow control
2147          * according to the "hw->fc" parameter.
2148          *
2149          * The possible values of the "fc" parameter are:
2150          *      0:  Flow control is completely disabled
2151          *      1:  Rx flow control is enabled (we can receive pause
2152          *          frames but not send pause frames).
2153          *      2:  Tx flow control is enabled (we can send pause frames
2154          *          frames but we do not receive pause frames).
2155          *      3:  Both Rx and TX flow control (symmetric) is enabled.
2156          *  other:  No other values should be possible at this point.
2157          */
2158         
2159         switch (hw->fc) {
2160         case e1000_fc_none:
2161                 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
2162                 break;
2163         case e1000_fc_rx_pause:
2164                 ctrl &= (~E1000_CTRL_TFCE);
2165                 ctrl |= E1000_CTRL_RFCE;
2166                 break;
2167         case e1000_fc_tx_pause:
2168                 ctrl &= (~E1000_CTRL_RFCE);
2169                 ctrl |= E1000_CTRL_TFCE;
2170                 break;
2171         case e1000_fc_full:
2172                 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
2173                 break;
2174         default:
2175                 DEBUGOUT("Flow control param set incorrectly\n");
2176                 return -E1000_ERR_CONFIG;
2177         }
2178         
2179         /* Disable TX Flow Control for 82542 (rev 2.0) */
2180         if(hw->mac_type == e1000_82542_rev2_0)
2181                 ctrl &= (~E1000_CTRL_TFCE);
2182         
2183         E1000_WRITE_REG(hw, CTRL, ctrl);
2184         return E1000_SUCCESS;
2185 }
2186
2187 /******************************************************************************
2188  * Configures flow control settings after link is established
2189  * 
2190  * hw - Struct containing variables accessed by shared code
2191  *
2192  * Should be called immediately after a valid link has been established.
2193  * Forces MAC flow control settings if link was forced. When in MII/GMII mode
2194  * and autonegotiation is enabled, the MAC flow control settings will be set
2195  * based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2196  * and RFCE bits will be automaticaly set to the negotiated flow control mode.
2197  *****************************************************************************/
2198 static int
2199 e1000_config_fc_after_link_up(struct e1000_hw *hw)
2200 {
2201         int32_t ret_val;
2202         uint16_t mii_status_reg;
2203         uint16_t mii_nway_adv_reg;
2204         uint16_t mii_nway_lp_ability_reg;
2205         uint16_t speed;
2206         uint16_t duplex;
2207         
2208         DEBUGFUNC("e1000_config_fc_after_link_up");
2209         
2210         /* Check for the case where we have fiber media and auto-neg failed
2211          * so we had to force link.  In this case, we need to force the
2212          * configuration of the MAC to match the "fc" parameter.
2213          */
2214         if(((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) ||
2215            ((hw->media_type == e1000_media_type_internal_serdes) && (hw->autoneg_failed))) { 
2216                 if((ret_val = e1000_force_mac_fc(hw))) {
2217                         DEBUGOUT("Error forcing flow control settings\n");
2218                         return ret_val;
2219                 }
2220         }
2221         
2222         /* Check for the case where we have copper media and auto-neg is
2223          * enabled.  In this case, we need to check and see if Auto-Neg
2224          * has completed, and if so, how the PHY and link partner has
2225          * flow control configured.
2226          */
2227         if(hw->media_type == e1000_media_type_copper) {
2228                 /* Read the MII Status Register and check to see if AutoNeg
2229                  * has completed.  We read this twice because this reg has
2230                  * some "sticky" (latched) bits.
2231                  */
2232                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
2233                         return ret_val;
2234                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg)))
2235                         return ret_val;
2236                 
2237                 if(mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2238                         /* The AutoNeg process has completed, so we now need to
2239                          * read both the Auto Negotiation Advertisement Register
2240                          * (Address 4) and the Auto_Negotiation Base Page Ability
2241                          * Register (Address 5) to determine how flow control was
2242                          * negotiated.
2243                          */
2244                         if((ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2245                                                          &mii_nway_adv_reg)))
2246                                 return ret_val;
2247                         if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2248                                                          &mii_nway_lp_ability_reg)))
2249                                 return ret_val;
2250
2251                         /* Two bits in the Auto Negotiation Advertisement Register
2252                          * (Address 4) and two bits in the Auto Negotiation Base
2253                          * Page Ability Register (Address 5) determine flow control
2254                          * for both the PHY and the link partner.  The following
2255                          * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2256                          * 1999, describes these PAUSE resolution bits and how flow
2257                          * control is determined based upon these settings.
2258                          * NOTE:  DC = Don't Care
2259                          *
2260                          *   LOCAL DEVICE  |   LINK PARTNER
2261                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
2262                          *-------|---------|-------|---------|--------------------
2263                          *   0   |    0    |  DC   |   DC    | e1000_fc_none
2264                          *   0   |    1    |   0   |   DC    | e1000_fc_none
2265                          *   0   |    1    |   1   |    0    | e1000_fc_none
2266                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
2267                          *   1   |    0    |   0   |   DC    | e1000_fc_none
2268                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
2269                          *   1   |    1    |   0   |    0    | e1000_fc_none
2270                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
2271                          *
2272                          */
2273                         /* Are both PAUSE bits set to 1?  If so, this implies
2274                          * Symmetric Flow Control is enabled at both ends.  The
2275                          * ASM_DIR bits are irrelevant per the spec.
2276                          *
2277                          * For Symmetric Flow Control:
2278                          *
2279                          *   LOCAL DEVICE  |   LINK PARTNER
2280                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2281                          *-------|---------|-------|---------|--------------------
2282                          *   1   |   DC    |   1   |   DC    | e1000_fc_full
2283                          *
2284                          */
2285                         if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2286                                 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2287                                 /* Now we need to check if the user selected RX ONLY
2288                                  * of pause frames.  In this case, we had to advertise
2289                                  * FULL flow control because we could not advertise RX
2290                                  * ONLY. Hence, we must now check to see if we need to
2291                                  * turn OFF  the TRANSMISSION of PAUSE frames.
2292                                  */
2293 #if 0
2294                                 if(hw->original_fc == e1000_fc_full) {
2295                                         hw->fc = e1000_fc_full;
2296 #else
2297                                 if(hw->fc == e1000_fc_full) {
2298 #endif
2299                                         DEBUGOUT("Flow Control = FULL.\r\n");
2300                                 } else {
2301                                         hw->fc = e1000_fc_rx_pause;
2302                                         DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2303                                 }
2304                         }
2305                         /* For receiving PAUSE frames ONLY.
2306                          *
2307                          *   LOCAL DEVICE  |   LINK PARTNER
2308                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2309                          *-------|---------|-------|---------|--------------------
2310                          *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
2311                          *
2312                          */
2313                         else if(!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2314                                 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2315                                 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2316                                 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2317                                 hw->fc = e1000_fc_tx_pause;
2318                                 DEBUGOUT("Flow Control = TX PAUSE frames only.\r\n");
2319                         }
2320                         /* For transmitting PAUSE frames ONLY.
2321                          *
2322                          *   LOCAL DEVICE  |   LINK PARTNER
2323                          * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
2324                          *-------|---------|-------|---------|--------------------
2325                          *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
2326                          *
2327                          */
2328                         else if((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2329                                 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2330                                 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2331                                 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2332                                 hw->fc = e1000_fc_rx_pause;
2333                                 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2334                         }
2335                         /* Per the IEEE spec, at this point flow control should be
2336                          * disabled.  However, we want to consider that we could
2337                          * be connected to a legacy switch that doesn't advertise
2338                          * desired flow control, but can be forced on the link
2339                          * partner.  So if we advertised no flow control, that is
2340                          * what we will resolve to.  If we advertised some kind of
2341                          * receive capability (Rx Pause Only or Full Flow Control)
2342                          * and the link partner advertised none, we will configure
2343                          * ourselves to enable Rx Flow Control only.  We can do
2344                          * this safely for two reasons:  If the link partner really
2345                          * didn't want flow control enabled, and we enable Rx, no
2346                          * harm done since we won't be receiving any PAUSE frames
2347                          * anyway.  If the intent on the link partner was to have
2348                          * flow control enabled, then by us enabling RX only, we
2349                          * can at least receive pause frames and process them.
2350                          * This is a good idea because in most cases, since we are
2351                          * predominantly a server NIC, more times than not we will
2352                          * be asked to delay transmission of packets than asking
2353                          * our link partner to pause transmission of frames.
2354                          */
2355 #if 0
2356                         else if(hw->original_fc == e1000_fc_none ||
2357                                 hw->original_fc == e1000_fc_tx_pause) {
2358 #else
2359                         else if(hw->fc == e1000_fc_none)
2360                                 DEBUGOUT("Flow Control = NONE.\r\n");
2361                         else if(hw->fc == e1000_fc_tx_pause) {
2362 #endif
2363                                 hw->fc = e1000_fc_none;
2364                                 DEBUGOUT("Flow Control = NONE.\r\n");
2365                         } else {
2366                                 hw->fc = e1000_fc_rx_pause;
2367                                 DEBUGOUT("Flow Control = RX PAUSE frames only.\r\n");
2368                         }
2369                         
2370                         /* Now we need to do one last check...  If we auto-
2371                          * negotiated to HALF DUPLEX, flow control should not be
2372                          * enabled per IEEE 802.3 spec.
2373                          */
2374                         e1000_get_speed_and_duplex(hw, &speed, &duplex);
2375                         
2376                         if(duplex == HALF_DUPLEX)
2377                                 hw->fc = e1000_fc_none;
2378                         
2379                         /* Now we call a subroutine to actually force the MAC
2380                          * controller to use the correct flow control settings.
2381                          */
2382                         if((ret_val = e1000_force_mac_fc(hw))) {
2383                                 DEBUGOUT("Error forcing flow control settings\n");
2384                                 return ret_val;
2385                         }
2386                 } else {
2387                         DEBUGOUT("Copper PHY and Auto Neg has not completed.\r\n");
2388                 }
2389         }
2390         return E1000_SUCCESS;
2391 }
2392
2393 /******************************************************************************
2394  * Checks to see if the link status of the hardware has changed.
2395  *
2396  * hw - Struct containing variables accessed by shared code
2397  *
2398  * Called by any function that needs to check the link status of the adapter.
2399  *****************************************************************************/
2400 static int
2401 e1000_check_for_link(struct e1000_hw *hw)
2402 {
2403         uint32_t rxcw;
2404         uint32_t ctrl;
2405         uint32_t status;
2406         uint32_t rctl;
2407         uint32_t signal = 0;
2408         int32_t ret_val;
2409         uint16_t phy_data;
2410         uint16_t lp_capability;
2411         
2412         DEBUGFUNC("e1000_check_for_link");
2413         
2414         /* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be 
2415          * set when the optics detect a signal. On older adapters, it will be 
2416          * cleared when there is a signal.  This applies to fiber media only.
2417          */
2418         if(hw->media_type == e1000_media_type_fiber)
2419                 signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2420
2421         ctrl = E1000_READ_REG(hw, CTRL);
2422         status = E1000_READ_REG(hw, STATUS);
2423         rxcw = E1000_READ_REG(hw, RXCW);
2424         
2425         /* If we have a copper PHY then we only want to go out to the PHY
2426          * registers to see if Auto-Neg has completed and/or if our link
2427          * status has changed.  The get_link_status flag will be set if we
2428          * receive a Link Status Change interrupt or we have Rx Sequence
2429          * Errors.
2430          */
2431 #if 0
2432         if((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2433 #else
2434         if(hw->media_type == e1000_media_type_copper) {
2435 #endif
2436                 /* First we want to see if the MII Status Register reports
2437                  * link.  If so, then we want to get the current speed/duplex
2438                  * of the PHY.
2439                  * Read the register twice since the link bit is sticky.
2440                  */
2441                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2442                         return ret_val;
2443                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2444                         return ret_val;
2445                 
2446                 if(phy_data & MII_SR_LINK_STATUS) {
2447 #if 0
2448                         hw->get_link_status = FALSE;
2449 #endif
2450                 } else {
2451                         /* No link detected */
2452                         return -E1000_ERR_NOLINK;
2453                 }
2454
2455                 /* We have a M88E1000 PHY and Auto-Neg is enabled.  If we
2456                  * have Si on board that is 82544 or newer, Auto
2457                  * Speed Detection takes care of MAC speed/duplex
2458                  * configuration.  So we only need to configure Collision
2459                  * Distance in the MAC.  Otherwise, we need to force
2460                  * speed/duplex on the MAC to the current PHY speed/duplex
2461                  * settings.
2462                  */
2463                 if(hw->mac_type >= e1000_82544)
2464                         e1000_config_collision_dist(hw);
2465                 else {
2466                         if((ret_val = e1000_config_mac_to_phy(hw))) {
2467                                 DEBUGOUT("Error configuring MAC to PHY settings\n");
2468                                 return ret_val;
2469                         }
2470                 }
2471                 
2472                 /* Configure Flow Control now that Auto-Neg has completed. First, we 
2473                  * need to restore the desired flow control settings because we may
2474                  * have had to re-autoneg with a different link partner.
2475                  */
2476                 if((ret_val = e1000_config_fc_after_link_up(hw))) {
2477                         DEBUGOUT("Error configuring flow control\n");
2478                         return ret_val;
2479                 }
2480                 
2481                 /* At this point we know that we are on copper and we have
2482                  * auto-negotiated link.  These are conditions for checking the link
2483                  * parter capability register.  We use the link partner capability to
2484                  * determine if TBI Compatibility needs to be turned on or off.  If
2485                  * the link partner advertises any speed in addition to Gigabit, then
2486                  * we assume that they are GMII-based, and TBI compatibility is not
2487                  * needed. If no other speeds are advertised, we assume the link
2488                  * partner is TBI-based, and we turn on TBI Compatibility.
2489                  */
2490                 if(hw->tbi_compatibility_en) {
2491                         if((ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2492                                                          &lp_capability)))
2493                                 return ret_val;
2494                         if(lp_capability & (NWAY_LPAR_10T_HD_CAPS |
2495                                 NWAY_LPAR_10T_FD_CAPS |
2496                                 NWAY_LPAR_100TX_HD_CAPS |
2497                                 NWAY_LPAR_100TX_FD_CAPS |
2498                                 NWAY_LPAR_100T4_CAPS)) {
2499                                 /* If our link partner advertises anything in addition to 
2500                                  * gigabit, we do not need to enable TBI compatibility.
2501                                  */
2502                                 if(hw->tbi_compatibility_on) {
2503                                         /* If we previously were in the mode, turn it off. */
2504                                         rctl = E1000_READ_REG(hw, RCTL);
2505                                         rctl &= ~E1000_RCTL_SBP;
2506                                         E1000_WRITE_REG(hw, RCTL, rctl);
2507                                         hw->tbi_compatibility_on = FALSE;
2508                                 }
2509                         } else {
2510                                 /* If TBI compatibility is was previously off, turn it on. For
2511                                  * compatibility with a TBI link partner, we will store bad
2512                                  * packets. Some frames have an additional byte on the end and
2513                                  * will look like CRC errors to to the hardware.
2514                                  */
2515                                 if(!hw->tbi_compatibility_on) {
2516                                         hw->tbi_compatibility_on = TRUE;
2517                                         rctl = E1000_READ_REG(hw, RCTL);
2518                                         rctl |= E1000_RCTL_SBP;
2519                                         E1000_WRITE_REG(hw, RCTL, rctl);
2520                                 }
2521                         }
2522                 }
2523         }
2524         /* If we don't have link (auto-negotiation failed or link partner cannot
2525          * auto-negotiate), the cable is plugged in (we have signal), and our
2526          * link partner is not trying to auto-negotiate with us (we are receiving
2527          * idles or data), we need to force link up. We also need to give
2528          * auto-negotiation time to complete, in case the cable was just plugged
2529          * in. The autoneg_failed flag does this.
2530          */
2531         else if((((hw->media_type == e1000_media_type_fiber) &&
2532                 ((ctrl & E1000_CTRL_SWDPIN1) == signal)) ||
2533                 (hw->media_type == e1000_media_type_internal_serdes)) &&
2534                 (!(status & E1000_STATUS_LU)) &&
2535                 (!(rxcw & E1000_RXCW_C))) {
2536                 if(hw->autoneg_failed == 0) {
2537                         hw->autoneg_failed = 1;
2538                         return 0;
2539                 }
2540                 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\r\n");
2541                 
2542                 /* Disable auto-negotiation in the TXCW register */
2543                 E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
2544                 
2545                 /* Force link-up and also force full-duplex. */
2546                 ctrl = E1000_READ_REG(hw, CTRL);
2547                 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
2548                 E1000_WRITE_REG(hw, CTRL, ctrl);
2549                 
2550                 /* Configure Flow Control after forcing link up. */
2551                 if((ret_val = e1000_config_fc_after_link_up(hw))) {
2552                         DEBUGOUT("Error configuring flow control\n");
2553                         return ret_val;
2554                 }
2555         }
2556         /* If we are forcing link and we are receiving /C/ ordered sets, re-enable
2557          * auto-negotiation in the TXCW register and disable forced link in the
2558          * Device Control register in an attempt to auto-negotiate with our link
2559          * partner.
2560          */
2561         else if(((hw->media_type == e1000_media_type_fiber)  ||
2562                  (hw->media_type == e1000_media_type_internal_serdes)) &&
2563                 (ctrl & E1000_CTRL_SLU) &&
2564                 (rxcw & E1000_RXCW_C)) {
2565                 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\r\n");
2566                 E1000_WRITE_REG(hw, TXCW, hw->txcw);
2567                 E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
2568         }
2569 #if 0
2570         /* If we force link for non-auto-negotiation switch, check link status
2571          * based on MAC synchronization for internal serdes media type.
2572          */
2573         else if((hw->media_type == e1000_media_type_internal_serdes) &&
2574                         !(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
2575                 /* SYNCH bit and IV bit are sticky. */
2576                 udelay(10);
2577                 if(E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
2578                         if(!(rxcw & E1000_RXCW_IV)) {
2579                                 hw->serdes_link_down = FALSE;
2580                                 DEBUGOUT("SERDES: Link is up.\n");
2581                         }
2582                 } else {
2583                         hw->serdes_link_down = TRUE;
2584                         DEBUGOUT("SERDES: Link is down.\n");
2585                 }
2586         }
2587 #endif
2588         return E1000_SUCCESS;
2589 }
2590
2591 /******************************************************************************
2592  * Detects the current speed and duplex settings of the hardware.
2593  *
2594  * hw - Struct containing variables accessed by shared code
2595  * speed - Speed of the connection
2596  * duplex - Duplex setting of the connection
2597  *****************************************************************************/
2598 static void 
2599 e1000_get_speed_and_duplex(struct e1000_hw *hw,
2600                            uint16_t *speed,
2601                            uint16_t *duplex)
2602 {
2603         uint32_t status;
2604         
2605         DEBUGFUNC("e1000_get_speed_and_duplex");
2606         
2607         if(hw->mac_type >= e1000_82543) {
2608                 status = E1000_READ_REG(hw, STATUS);
2609                 if(status & E1000_STATUS_SPEED_1000) {
2610                         *speed = SPEED_1000;
2611                         DEBUGOUT("1000 Mbs, ");
2612                 } else if(status & E1000_STATUS_SPEED_100) {
2613                         *speed = SPEED_100;
2614                         DEBUGOUT("100 Mbs, ");
2615                 } else {
2616                         *speed = SPEED_10;
2617                         DEBUGOUT("10 Mbs, ");
2618                 }
2619                 
2620                 if(status & E1000_STATUS_FD) {
2621                         *duplex = FULL_DUPLEX;
2622                         DEBUGOUT("Full Duplex\r\n");
2623                 } else {
2624                         *duplex = HALF_DUPLEX;
2625                         DEBUGOUT(" Half Duplex\r\n");
2626                 }
2627         } else {
2628                 DEBUGOUT("1000 Mbs, Full Duplex\r\n");
2629                 *speed = SPEED_1000;
2630                 *duplex = FULL_DUPLEX;
2631         }
2632 }
2633
2634 /******************************************************************************
2635 * Blocks until autoneg completes or times out (~4.5 seconds)
2636 *
2637 * hw - Struct containing variables accessed by shared code
2638 ******************************************************************************/
2639 static int
2640 e1000_wait_autoneg(struct e1000_hw *hw)
2641 {
2642         int32_t ret_val;
2643         uint16_t i;
2644         uint16_t phy_data;
2645         
2646         DEBUGFUNC("e1000_wait_autoneg");
2647         DEBUGOUT("Waiting for Auto-Neg to complete.\n");
2648         
2649         /* We will wait for autoneg to complete or 4.5 seconds to expire. */
2650         for(i = PHY_AUTO_NEG_TIME; i > 0; i--) {
2651                 /* Read the MII Status Register and wait for Auto-Neg
2652                  * Complete bit to be set.
2653                  */
2654                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2655                         return ret_val;
2656                 if((ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data)))
2657                         return ret_val;
2658                 if(phy_data & MII_SR_AUTONEG_COMPLETE) {
2659                         DEBUGOUT("Auto-Neg complete.\n");
2660                         return E1000_SUCCESS;
2661                 }
2662                 mdelay(100);
2663         }
2664         DEBUGOUT("Auto-Neg timedout.\n");
2665         return -E1000_ERR_TIMEOUT;
2666 }
2667
2668 /******************************************************************************
2669 * Raises the Management Data Clock
2670 *
2671 * hw - Struct containing variables accessed by shared code
2672 * ctrl - Device control register's current value
2673 ******************************************************************************/
2674 static void
2675 e1000_raise_mdi_clk(struct e1000_hw *hw,
2676                     uint32_t *ctrl)
2677 {
2678         /* Raise the clock input to the Management Data Clock (by setting the MDC
2679          * bit), and then delay 10 microseconds.
2680          */
2681         E1000_WRITE_REG(hw, CTRL, (*ctrl | E1000_CTRL_MDC));
2682         E1000_WRITE_FLUSH(hw);
2683         udelay(10);
2684 }
2685
2686 /******************************************************************************
2687 * Lowers the Management Data Clock
2688 *
2689 * hw - Struct containing variables accessed by shared code
2690 * ctrl - Device control register's current value
2691 ******************************************************************************/
2692 static void
2693 e1000_lower_mdi_clk(struct e1000_hw *hw,
2694                     uint32_t *ctrl)
2695 {
2696         /* Lower the clock input to the Management Data Clock (by clearing the MDC
2697          * bit), and then delay 10 microseconds.
2698          */
2699         E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
2700         E1000_WRITE_FLUSH(hw);
2701         udelay(10);
2702 }
2703
2704 /******************************************************************************
2705 * Shifts data bits out to the PHY
2706 *
2707 * hw - Struct containing variables accessed by shared code
2708 * data - Data to send out to the PHY
2709 * count - Number of bits to shift out
2710 *
2711 * Bits are shifted out in MSB to LSB order.
2712 ******************************************************************************/
2713 static void
2714 e1000_shift_out_mdi_bits(struct e1000_hw *hw,
2715                          uint32_t data,
2716                          uint16_t count)
2717 {
2718         uint32_t ctrl;
2719         uint32_t mask;
2720
2721         /* We need to shift "count" number of bits out to the PHY. So, the value
2722          * in the "data" parameter will be shifted out to the PHY one bit at a 
2723          * time. In order to do this, "data" must be broken down into bits.
2724          */
2725         mask = 0x01;
2726         mask <<= (count - 1);
2727         
2728         ctrl = E1000_READ_REG(hw, CTRL);
2729         
2730         /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
2731         ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
2732         
2733         while(mask) {
2734                 /* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
2735                  * then raising and lowering the Management Data Clock. A "0" is
2736                  * shifted out to the PHY by setting the MDIO bit to "0" and then
2737                  * raising and lowering the clock.
2738                  */
2739                 if(data & mask) ctrl |= E1000_CTRL_MDIO;
2740                 else ctrl &= ~E1000_CTRL_MDIO;
2741                 
2742                 E1000_WRITE_REG(hw, CTRL, ctrl);
2743                 E1000_WRITE_FLUSH(hw);
2744                 
2745                 udelay(10);
2746
2747                 e1000_raise_mdi_clk(hw, &ctrl);
2748                 e1000_lower_mdi_clk(hw, &ctrl);
2749
2750                 mask = mask >> 1;
2751         }
2752 }
2753
2754 /******************************************************************************
2755 * Shifts data bits in from the PHY
2756 *
2757 * hw - Struct containing variables accessed by shared code
2758 *
2759 * Bits are shifted in in MSB to LSB order. 
2760 ******************************************************************************/
2761 static uint16_t
2762 e1000_shift_in_mdi_bits(struct e1000_hw *hw)
2763 {
2764         uint32_t ctrl;
2765         uint16_t data = 0;
2766         uint8_t i;
2767
2768         /* In order to read a register from the PHY, we need to shift in a total
2769          * of 18 bits from the PHY. The first two bit (turnaround) times are used
2770          * to avoid contention on the MDIO pin when a read operation is performed.
2771          * These two bits are ignored by us and thrown away. Bits are "shifted in"
2772          * by raising the input to the Management Data Clock (setting the MDC bit),
2773          * and then reading the value of the MDIO bit.
2774          */ 
2775         ctrl = E1000_READ_REG(hw, CTRL);
2776         
2777         /* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
2778         ctrl &= ~E1000_CTRL_MDIO_DIR;
2779         ctrl &= ~E1000_CTRL_MDIO;
2780         
2781         E1000_WRITE_REG(hw, CTRL, ctrl);
2782         E1000_WRITE_FLUSH(hw);
2783         
2784         /* Raise and Lower the clock before reading in the data. This accounts for
2785          * the turnaround bits. The first clock occurred when we clocked out the
2786          * last bit of the Register Address.
2787          */
2788         e1000_raise_mdi_clk(hw, &ctrl);
2789         e1000_lower_mdi_clk(hw, &ctrl);
2790         
2791         for(data = 0, i = 0; i < 16; i++) {
2792                 data = data << 1;
2793                 e1000_raise_mdi_clk(hw, &ctrl);
2794                 ctrl = E1000_READ_REG(hw, CTRL);
2795                 /* Check to see if we shifted in a "1". */
2796                 if(ctrl & E1000_CTRL_MDIO) data |= 1;
2797                 e1000_lower_mdi_clk(hw, &ctrl);
2798         }
2799         
2800         e1000_raise_mdi_clk(hw, &ctrl);
2801         e1000_lower_mdi_clk(hw, &ctrl);
2802         
2803         return data;
2804 }
2805
2806 /*****************************************************************************
2807 * Reads the value from a PHY register, if the value is on a specific non zero
2808 * page, sets the page first.
2809 *
2810 * hw - Struct containing variables accessed by shared code
2811 * reg_addr - address of the PHY register to read
2812 ******************************************************************************/
2813 static int
2814 e1000_read_phy_reg(struct e1000_hw *hw,
2815                    uint32_t reg_addr,
2816                    uint16_t *phy_data)
2817 {
2818         uint32_t ret_val;
2819
2820         DEBUGFUNC("e1000_read_phy_reg");
2821
2822         if(hw->phy_type == e1000_phy_igp &&
2823            (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2824                 if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2825                                                      (uint16_t)reg_addr)))
2826                         return ret_val;
2827         }
2828
2829         ret_val = e1000_read_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2830                                         phy_data);
2831
2832         return ret_val;
2833 }
2834
2835 static int
2836 e1000_read_phy_reg_ex(struct e1000_hw *hw,
2837                       uint32_t reg_addr,
2838                       uint16_t *phy_data)
2839 {
2840         uint32_t i;
2841         uint32_t mdic = 0;
2842         const uint32_t phy_addr = 1;
2843
2844         DEBUGFUNC("e1000_read_phy_reg_ex");
2845         
2846         if(reg_addr > MAX_PHY_REG_ADDRESS) {
2847                 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2848                 return -E1000_ERR_PARAM;
2849         }
2850         
2851         if(hw->mac_type > e1000_82543) {
2852                 /* Set up Op-code, Phy Address, and register address in the MDI
2853                  * Control register.  The MAC will take care of interfacing with the
2854                  * PHY to retrieve the desired data.
2855                  */
2856                 mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) |
2857                         (phy_addr << E1000_MDIC_PHY_SHIFT) | 
2858                         (E1000_MDIC_OP_READ));
2859                 
2860                 E1000_WRITE_REG(hw, MDIC, mdic);
2861
2862                 /* Poll the ready bit to see if the MDI read completed */
2863                 for(i = 0; i < 64; i++) {
2864                         udelay(50);
2865                         mdic = E1000_READ_REG(hw, MDIC);
2866                         if(mdic & E1000_MDIC_READY) break;
2867                 }
2868                 if(!(mdic & E1000_MDIC_READY)) {
2869                         DEBUGOUT("MDI Read did not complete\n");
2870                         return -E1000_ERR_PHY;
2871                 }
2872                 if(mdic & E1000_MDIC_ERROR) {
2873                         DEBUGOUT("MDI Error\n");
2874                         return -E1000_ERR_PHY;
2875                 }
2876                 *phy_data = (uint16_t) mdic;
2877         } else {
2878                 /* We must first send a preamble through the MDIO pin to signal the
2879                  * beginning of an MII instruction.  This is done by sending 32
2880                  * consecutive "1" bits.
2881                  */
2882                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2883                 
2884                 /* Now combine the next few fields that are required for a read
2885                  * operation.  We use this method instead of calling the
2886                  * e1000_shift_out_mdi_bits routine five different times. The format of
2887                  * a MII read instruction consists of a shift out of 14 bits and is
2888                  * defined as follows:
2889                  *    <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
2890                  * followed by a shift in of 18 bits.  This first two bits shifted in
2891                  * are TurnAround bits used to avoid contention on the MDIO pin when a
2892                  * READ operation is performed.  These two bits are thrown away
2893                  * followed by a shift in of 16 bits which contains the desired data.
2894                  */
2895                 mdic = ((reg_addr) | (phy_addr << 5) | 
2896                         (PHY_OP_READ << 10) | (PHY_SOF << 12));
2897                 
2898                 e1000_shift_out_mdi_bits(hw, mdic, 14);
2899                 
2900                 /* Now that we've shifted out the read command to the MII, we need to
2901                  * "shift in" the 16-bit value (18 total bits) of the requested PHY
2902                  * register address.
2903                  */
2904                 *phy_data = e1000_shift_in_mdi_bits(hw);
2905         }
2906         return E1000_SUCCESS;
2907 }
2908
2909 /******************************************************************************
2910 * Writes a value to a PHY register
2911 *
2912 * hw - Struct containing variables accessed by shared code
2913 * reg_addr - address of the PHY register to write
2914 * data - data to write to the PHY
2915 ******************************************************************************/
2916 static int 
2917 e1000_write_phy_reg(struct e1000_hw *hw,
2918                     uint32_t reg_addr,
2919                     uint16_t phy_data)
2920 {
2921         uint32_t ret_val;
2922
2923         DEBUGFUNC("e1000_write_phy_reg");
2924
2925         if(hw->phy_type == e1000_phy_igp &&
2926            (reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
2927                 if((ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
2928                                                      (uint16_t)reg_addr)))
2929                         return ret_val;
2930         }
2931
2932         ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT & reg_addr,
2933                                          phy_data);
2934
2935         return ret_val;
2936 }
2937
2938 static int
2939 e1000_write_phy_reg_ex(struct e1000_hw *hw,
2940                        uint32_t reg_addr,
2941                        uint16_t phy_data)
2942 {
2943         uint32_t i;
2944         uint32_t mdic = 0;
2945         const uint32_t phy_addr = 1;
2946         
2947         DEBUGFUNC("e1000_write_phy_reg_ex");
2948         
2949         if(reg_addr > MAX_PHY_REG_ADDRESS) {
2950                 DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
2951                 return -E1000_ERR_PARAM;
2952         }
2953         
2954         if(hw->mac_type > e1000_82543) {
2955                 /* Set up Op-code, Phy Address, register address, and data intended
2956                  * for the PHY register in the MDI Control register.  The MAC will take
2957                  * care of interfacing with the PHY to send the desired data.
2958                  */
2959                 mdic = (((uint32_t) phy_data) |
2960                         (reg_addr << E1000_MDIC_REG_SHIFT) |
2961                         (phy_addr << E1000_MDIC_PHY_SHIFT) | 
2962                         (E1000_MDIC_OP_WRITE));
2963                 
2964                 E1000_WRITE_REG(hw, MDIC, mdic);
2965                 
2966                 /* Poll the ready bit to see if the MDI read completed */
2967                 for(i = 0; i < 640; i++) {
2968                         udelay(5);
2969                         mdic = E1000_READ_REG(hw, MDIC);
2970                         if(mdic & E1000_MDIC_READY) break;
2971                 }
2972                 if(!(mdic & E1000_MDIC_READY)) {
2973                         DEBUGOUT("MDI Write did not complete\n");
2974                         return -E1000_ERR_PHY;
2975                 }
2976         } else {
2977                 /* We'll need to use the SW defined pins to shift the write command
2978                  * out to the PHY. We first send a preamble to the PHY to signal the
2979                  * beginning of the MII instruction.  This is done by sending 32 
2980                  * consecutive "1" bits.
2981                  */
2982                 e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
2983                 
2984                 /* Now combine the remaining required fields that will indicate a 
2985                  * write operation. We use this method instead of calling the
2986                  * e1000_shift_out_mdi_bits routine for each field in the command. The
2987                  * format of a MII write instruction is as follows:
2988                  * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
2989                  */
2990                 mdic = ((PHY_TURNAROUND) | (reg_addr << 2) | (phy_addr << 7) |
2991                         (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
2992                 mdic <<= 16;
2993                 mdic |= (uint32_t) phy_data;
2994                 
2995                 e1000_shift_out_mdi_bits(hw, mdic, 32);
2996         }
2997
2998         return E1000_SUCCESS;
2999 }
3000
3001 /******************************************************************************
3002 * Returns the PHY to the power-on reset state
3003 *
3004 * hw - Struct containing variables accessed by shared code
3005 ******************************************************************************/
3006 static void
3007 e1000_phy_hw_reset(struct e1000_hw *hw)
3008 {
3009         uint32_t ctrl, ctrl_ext;
3010
3011         DEBUGFUNC("e1000_phy_hw_reset");
3012         
3013         DEBUGOUT("Resetting Phy...\n");
3014         
3015         if(hw->mac_type > e1000_82543) {
3016                 /* Read the device control register and assert the E1000_CTRL_PHY_RST
3017                  * bit. Then, take it out of reset.
3018                  */
3019                 ctrl = E1000_READ_REG(hw, CTRL);
3020                 E1000_WRITE_REG(hw, CTRL, ctrl | E1000_CTRL_PHY_RST);
3021                 E1000_WRITE_FLUSH(hw);
3022                 mdelay(10);
3023                 E1000_WRITE_REG(hw, CTRL, ctrl);
3024                 E1000_WRITE_FLUSH(hw);
3025         } else {
3026                 /* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3027                  * bit to put the PHY into reset. Then, take it out of reset.
3028                  */
3029                 ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
3030                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
3031                 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3032                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3033                 E1000_WRITE_FLUSH(hw);
3034                 mdelay(10);
3035                 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
3036                 E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3037                 E1000_WRITE_FLUSH(hw);
3038         }
3039         udelay(150);
3040 }
3041
3042 /******************************************************************************
3043 * Resets the PHY
3044 *
3045 * hw - Struct containing variables accessed by shared code
3046 *
3047 * Sets bit 15 of the MII Control regiser
3048 ******************************************************************************/
3049 static int 
3050 e1000_phy_reset(struct e1000_hw *hw)
3051 {
3052         int32_t ret_val;
3053         uint16_t phy_data;
3054
3055         DEBUGFUNC("e1000_phy_reset");
3056
3057         if(hw->mac_type != e1000_82541_rev_2) {
3058                 if((ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data)))
3059                         return ret_val;
3060                 
3061                 phy_data |= MII_CR_RESET;
3062                 if((ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data)))
3063                         return ret_val;
3064                 
3065                 udelay(1);
3066         } else e1000_phy_hw_reset(hw);
3067
3068         if(hw->phy_type == e1000_phy_igp)
3069                 e1000_phy_init_script(hw);
3070
3071         return E1000_SUCCESS;
3072 }
3073
3074 /******************************************************************************
3075 * Probes the expected PHY address for known PHY IDs
3076 *
3077 * hw - Struct containing variables accessed by shared code
3078 ******************************************************************************/
3079 static int
3080 e1000_detect_gig_phy(struct e1000_hw *hw)
3081 {
3082         int32_t phy_init_status, ret_val;
3083         uint16_t phy_id_high, phy_id_low;
3084         boolean_t match = FALSE;
3085
3086         DEBUGFUNC("e1000_detect_gig_phy");
3087         
3088         /* Read the PHY ID Registers to identify which PHY is onboard. */
3089         if((ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high)))
3090                 return ret_val;
3091
3092         hw->phy_id = (uint32_t) (phy_id_high << 16);
3093         udelay(20);
3094         if((ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low)))
3095                 return ret_val;
3096         
3097         hw->phy_id |= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
3098 #ifdef LINUX_DRIVER
3099         hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
3100 #endif
3101         
3102         switch(hw->mac_type) {
3103         case e1000_82543:
3104                 if(hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
3105                 break;
3106         case e1000_82544:
3107                 if(hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
3108                 break;
3109         case e1000_82540:
3110         case e1000_82545:
3111         case e1000_82545_rev_3:
3112         case e1000_82546:
3113         case e1000_82546_rev_3:
3114                 if(hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
3115                 break;
3116         case e1000_82541:
3117         case e1000_82541_rev_2:
3118         case e1000_82547:
3119         case e1000_82547_rev_2:
3120                 if(hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
3121                 break;
3122         default:
3123                 DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
3124                 return -E1000_ERR_CONFIG;
3125         }
3126         phy_init_status = e1000_set_phy_type(hw);
3127
3128         if ((match) && (phy_init_status == E1000_SUCCESS)) {
3129                 DEBUGOUT1("PHY ID 0x%X detected\n", hw->phy_id);
3130                 return E1000_SUCCESS;
3131         }
3132         DEBUGOUT1("Invalid PHY ID 0x%X\n", hw->phy_id);
3133         return -E1000_ERR_PHY;
3134 }
3135
3136 /******************************************************************************
3137  * Sets up eeprom variables in the hw struct.  Must be called after mac_type
3138  * is configured.
3139  *
3140  * hw - Struct containing variables accessed by shared code
3141  *****************************************************************************/
3142 static void
3143 e1000_init_eeprom_params(struct e1000_hw *hw)
3144 {
3145         struct e1000_eeprom_info *eeprom = &hw->eeprom;
3146         uint32_t eecd = E1000_READ_REG(hw, EECD);
3147         uint16_t eeprom_size;
3148
3149         DEBUGFUNC("e1000_init_eeprom_params");
3150
3151         switch (hw->mac_type) {
3152         case e1000_82542_rev2_0:
3153         case e1000_82542_rev2_1:
3154         case e1000_82543:
3155         case e1000_82544:
3156                 eeprom->type = e1000_eeprom_microwire;
3157                 eeprom->word_size = 64;
3158                 eeprom->opcode_bits = 3;
3159                 eeprom->address_bits = 6;
3160                 eeprom->delay_usec = 50;
3161                 break;
3162         case e1000_82540:
3163         case e1000_82545:
3164         case e1000_82545_rev_3:
3165         case e1000_82546:
3166         case e1000_82546_rev_3:
3167                 eeprom->type = e1000_eeprom_microwire;
3168                 eeprom->opcode_bits = 3;
3169                 eeprom->delay_usec = 50;
3170                 if(eecd & E1000_EECD_SIZE) {
3171                         eeprom->word_size = 256;
3172                         eeprom->address_bits = 8;
3173                 } else {
3174                         eeprom->word_size = 64;
3175                         eeprom->address_bits = 6;
3176                 }
3177                 break;
3178         case e1000_82541:
3179         case e1000_82541_rev_2:
3180         case e1000_82547:
3181         case e1000_82547_rev_2:
3182                 if (eecd & E1000_EECD_TYPE) {
3183                         eeprom->type = e1000_eeprom_spi;
3184                         if (eecd & E1000_EECD_ADDR_BITS) {
3185                                 eeprom->page_size = 32;
3186                                 eeprom->address_bits = 16;
3187                         } else {
3188                                 eeprom->page_size = 8;
3189                                 eeprom->address_bits = 8;
3190                         }
3191                 } else {
3192                         eeprom->type = e1000_eeprom_microwire;
3193                         eeprom->opcode_bits = 3;
3194                         eeprom->delay_usec = 50;
3195                         if (eecd & E1000_EECD_ADDR_BITS) {
3196                                 eeprom->word_size = 256;
3197                                 eeprom->address_bits = 8;
3198                         } else {
3199                                 eeprom->word_size = 64;
3200                                 eeprom->address_bits = 6;
3201                         }
3202                 }
3203                 break;
3204         default:
3205                 eeprom->type = e1000_eeprom_spi;
3206                 if (eecd & E1000_EECD_ADDR_BITS) {
3207                         eeprom->page_size = 32;
3208                         eeprom->address_bits = 16;
3209                 } else {
3210                         eeprom->page_size = 8;
3211                         eeprom->address_bits = 8;
3212                 }
3213                 break;
3214         }
3215
3216         if (eeprom->type == e1000_eeprom_spi) {
3217                 eeprom->opcode_bits = 8;
3218                 eeprom->delay_usec = 1;
3219                 eeprom->word_size = 64;
3220                 if (e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size) == 0) {
3221                         eeprom_size &= EEPROM_SIZE_MASK;
3222
3223                         switch (eeprom_size) {
3224                         case EEPROM_SIZE_16KB:
3225                                 eeprom->word_size = 8192;
3226                                 break;
3227                         case EEPROM_SIZE_8KB:
3228                                 eeprom->word_size = 4096;
3229                                 break;
3230                         case EEPROM_SIZE_4KB:
3231                                 eeprom->word_size = 2048;
3232                                 break;
3233                         case EEPROM_SIZE_2KB:
3234                                 eeprom->word_size = 1024;
3235                                 break;
3236                         case EEPROM_SIZE_1KB:
3237                                 eeprom->word_size = 512;
3238                                 break;
3239                         case EEPROM_SIZE_512B:
3240                                 eeprom->word_size = 256;
3241                                 break;
3242                         case EEPROM_SIZE_128B:
3243                         default:
3244                                 break;
3245                         }
3246                 }
3247         }
3248 }
3249
3250 /**
3251  * e1000_reset - Reset the adapter
3252  */
3253
3254 static int
3255 e1000_reset(struct e1000_hw *hw)
3256 {
3257         uint32_t pba;
3258         /* Repartition Pba for greater than 9k mtu
3259          * To take effect CTRL.RST is required.
3260          */
3261
3262         if(hw->mac_type < e1000_82547) {
3263                 pba = E1000_PBA_48K;
3264         } else {
3265                 pba = E1000_PBA_30K;
3266         }
3267         E1000_WRITE_REG(hw, PBA, pba);
3268
3269         /* flow control settings */
3270 #if 0
3271         hw->fc_high_water = FC_DEFAULT_HI_THRESH;
3272         hw->fc_low_water = FC_DEFAULT_LO_THRESH;
3273         hw->fc_pause_time = FC_DEFAULT_TX_TIMER;
3274         hw->fc_send_xon = 1;
3275         hw->fc = hw->original_fc;
3276 #endif
3277         
3278         e1000_reset_hw(hw);
3279         if(hw->mac_type >= e1000_82544)
3280                 E1000_WRITE_REG(hw, WUC, 0);
3281         return e1000_init_hw(hw);
3282 }
3283
3284 /**
3285  * e1000_sw_init - Initialize general software structures (struct e1000_adapter)
3286  * @adapter: board private structure to initialize
3287  *
3288  * e1000_sw_init initializes the Adapter private data structure.
3289  * Fields are initialized based on PCI device information and
3290  * OS network device settings (MTU size).
3291  **/
3292
3293 static int 
3294 e1000_sw_init(struct pci_device *pdev, struct e1000_hw *hw)
3295 {
3296         int result;
3297
3298         /* PCI config space info */
3299         pci_read_config_word(pdev, PCI_VENDOR_ID, &hw->vendor_id);
3300         pci_read_config_word(pdev, PCI_DEVICE_ID, &hw->device_id);
3301         pci_read_config_byte(pdev, PCI_REVISION, &hw->revision_id);
3302 #if 0
3303         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID,
3304                              &hw->subsystem_vendor_id);
3305         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &hw->subsystem_id);
3306 #endif
3307
3308         pci_read_config_word(pdev, PCI_COMMAND, &hw->pci_cmd_word);
3309
3310         /* identify the MAC */
3311
3312         result = e1000_set_mac_type(hw);
3313         if (result) {
3314                 E1000_ERR("Unknown MAC Type\n");
3315                 return result;
3316         }
3317
3318         /* initialize eeprom parameters */
3319
3320         e1000_init_eeprom_params(hw);
3321
3322 #if 0
3323         if((hw->mac_type == e1000_82541) ||
3324            (hw->mac_type == e1000_82547) ||
3325            (hw->mac_type == e1000_82541_rev_2) ||
3326            (hw->mac_type == e1000_82547_rev_2))
3327                 hw->phy_init_script = 1;
3328 #endif
3329
3330         e1000_set_media_type(hw);
3331
3332 #if 0
3333         if(hw->mac_type < e1000_82543)
3334                 hw->report_tx_early = 0;
3335         else
3336                 hw->report_tx_early = 1;
3337
3338         hw->wait_autoneg_complete = FALSE;
3339 #endif
3340         hw->tbi_compatibility_en = TRUE;
3341 #if 0
3342         hw->adaptive_ifs = TRUE;
3343
3344         /* Copper options */
3345
3346         if(hw->media_type == e1000_media_type_copper) {
3347                 hw->mdix = AUTO_ALL_MODES;
3348                 hw->disable_polarity_correction = FALSE;
3349                 hw->master_slave = E1000_MASTER_SLAVE;
3350         }
3351 #endif
3352         return E1000_SUCCESS;
3353 }
3354
3355 static void fill_rx (void)
3356 {
3357         struct e1000_rx_desc *rd;
3358         rx_last = rx_tail;
3359         rd = rx_base + rx_tail;
3360         rx_tail = (rx_tail + 1) % 8;
3361         memset (rd, 0, 16);
3362         rd->buffer_addr = virt_to_bus(&packet);
3363         E1000_WRITE_REG (&hw, RDT, rx_tail);
3364 }
3365
3366 static void init_descriptor (void)
3367 {
3368         unsigned long ptr;
3369         unsigned long tctl;
3370
3371         ptr = virt_to_phys(tx_pool);
3372         if (ptr & 0xf)
3373                 ptr = (ptr + 0x10) & (~0xf);
3374
3375         tx_base = phys_to_virt(ptr);
3376
3377         E1000_WRITE_REG (&hw, TDBAL, virt_to_bus(tx_base));
3378         E1000_WRITE_REG (&hw, TDBAH, 0);
3379         E1000_WRITE_REG (&hw, TDLEN, 128);
3380
3381         /* Setup the HW Tx Head and Tail descriptor pointers */
3382
3383         E1000_WRITE_REG (&hw, TDH, 0);
3384         E1000_WRITE_REG (&hw, TDT, 0);
3385         tx_tail = 0;
3386
3387         /* Program the Transmit Control Register */
3388
3389 #ifdef LINUX_DRIVER_TCTL
3390         tctl = E1000_READ_REG(&hw, TCTL);
3391
3392         tctl &= ~E1000_TCTL_CT;
3393         tctl |= E1000_TCTL_EN | E1000_TCTL_PSP |
3394                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
3395 #else
3396         tctl = E1000_TCTL_PSP | E1000_TCTL_EN |
3397                 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT) | 
3398                 (E1000_HDX_COLLISION_DISTANCE << E1000_COLD_SHIFT);
3399 #endif
3400
3401         E1000_WRITE_REG (&hw, TCTL, tctl);
3402
3403         e1000_config_collision_dist(&hw);
3404
3405
3406         rx_tail = 0;
3407         /* disable receive */
3408         E1000_WRITE_REG (&hw, RCTL, 0);
3409         ptr = virt_to_phys(rx_pool);
3410         if (ptr & 0xf)
3411                 ptr = (ptr + 0x10) & (~0xf);
3412         rx_base = phys_to_virt(ptr);
3413
3414         /* Setup the Base and Length of the Rx Descriptor Ring */
3415
3416         E1000_WRITE_REG (&hw, RDBAL, virt_to_bus(rx_base));
3417         E1000_WRITE_REG (&hw, RDBAH, 0);
3418
3419         E1000_WRITE_REG (&hw, RDLEN, 128);
3420
3421         /* Setup the HW Rx Head and Tail Descriptor Pointers */
3422         E1000_WRITE_REG (&hw, RDH, 0);
3423         E1000_WRITE_REG (&hw, RDT, 0);
3424
3425         E1000_WRITE_REG (&hw, RCTL, 
3426                 E1000_RCTL_EN | 
3427                 E1000_RCTL_BAM | 
3428                 E1000_RCTL_SZ_2048 | 
3429                 E1000_RCTL_MPE);
3430         fill_rx();
3431 }
3432
3433
3434
3435 /**************************************************************************
3436 POLL - Wait for a frame
3437 ***************************************************************************/
3438 static int
3439 e1000_poll (struct nic *nic, int retrieve)
3440 {
3441         /* return true if there's an ethernet packet ready to read */
3442         /* nic->packet should contain data on return */
3443         /* nic->packetlen should contain length of data */
3444         struct e1000_rx_desc *rd;
3445         uint32_t icr;
3446
3447         rd = rx_base + rx_last;
3448         if (!rd->status & E1000_RXD_STAT_DD)
3449                 return 0;
3450
3451         if ( ! retrieve ) return 1;
3452
3453         //      printf("recv: packet %! -> %! len=%d \n", packet+6, packet,rd->Length);
3454         memcpy (nic->packet, packet, rd->length);
3455         nic->packetlen = rd->length;
3456         fill_rx ();
3457
3458         /* Acknowledge interrupt. */
3459         icr = E1000_READ_REG(&hw, ICR);
3460
3461         return 1;
3462 }
3463
3464 /**************************************************************************
3465 TRANSMIT - Transmit a frame
3466 ***************************************************************************/
3467 static void
3468 e1000_transmit (struct nic *nic, const char *d, /* Destination */
3469                     unsigned int type,  /* Type */
3470                     unsigned int size,  /* size */
3471                     const char *p)      /* Packet */
3472 {
3473         /* send the packet to destination */
3474         struct eth_hdr {
3475                 unsigned char dst_addr[ETH_ALEN];
3476                 unsigned char src_addr[ETH_ALEN];
3477                 unsigned short type;
3478         } hdr;
3479         struct e1000_tx_desc *txhd;     /* header */
3480         struct e1000_tx_desc *txp;      /* payload */
3481         DEBUGFUNC("send");
3482
3483         memcpy (&hdr.dst_addr, d, ETH_ALEN);
3484         memcpy (&hdr.src_addr, nic->node_addr, ETH_ALEN);
3485
3486         hdr.type = htons (type);
3487         txhd = tx_base + tx_tail;
3488         tx_tail = (tx_tail + 1) % 8;
3489         txp = tx_base + tx_tail;
3490         tx_tail = (tx_tail + 1) % 8;
3491
3492         txhd->buffer_addr = virt_to_bus (&hdr);
3493         txhd->lower.data = sizeof (hdr);
3494         txhd->upper.data = 0;
3495
3496         txp->buffer_addr = virt_to_bus(p);
3497         txp->lower.data = E1000_TXD_CMD_RPS | E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS | size;
3498         txp->upper.data = 0;
3499
3500         E1000_WRITE_REG (&hw, TDT, tx_tail);
3501         while (!(txp->upper.data & E1000_TXD_STAT_DD)) {
3502                 udelay(10);     /* give the nic a chance to write to the register */
3503                 poll_interruptions();
3504         }
3505         DEBUGFUNC("send end");
3506 }
3507
3508
3509 /**************************************************************************
3510 DISABLE - Turn off ethernet interface
3511 ***************************************************************************/
3512 static void e1000_disable (struct dev *dev __unused)
3513 {
3514         /* Clear the transmit ring */
3515         E1000_WRITE_REG (&hw, TDH, 0);
3516         E1000_WRITE_REG (&hw, TDT, 0);
3517
3518         /* Clear the receive ring */
3519         E1000_WRITE_REG (&hw, RDH, 0);
3520         E1000_WRITE_REG (&hw, RDT, 0);
3521
3522         /* put the card in its initial state */
3523         switch(hw.mac_type) {
3524                 case e1000_82544:
3525                 case e1000_82540:
3526                 case e1000_82545:
3527                 case e1000_82546:
3528                 case e1000_82541:
3529                 case e1000_82541_rev_2:
3530                         /* These controllers can't ack the 64-bit write when issuing the
3531              &