Adding support for BeagleBoard.
authorAJFISH <AJFISH@de2fecce-e211-0410-80a6-f3fac2684e05>
Sun, 6 Dec 2009 01:57:05 +0000 (01:57 +0000)
committerAJFISH <AJFISH@de2fecce-e211-0410-80a6-f3fac2684e05>
Sun, 6 Dec 2009 01:57:05 +0000 (01:57 +0000)
ArmPkg - Supoprt for ARM specific things that can change as the architecture changes. Plus semihosting JTAG drivers.
EmbeddedPkg - Generic support for an embeddded platform. Including a light weight command line shell.
BeagleBoardPkg - Platform specifics for BeagleBoard. SD Card works, but USB has issues. Looks like a bug in the open source USB stack (Our internal stack works fine).

git-svn-id: https://edk2.tianocore.org/svn/edk2/trunk@9518 de2fecce-e211-0410-80a6-f3fac2684e05

294 files changed:
edk2/ArmPkg/ArmPkg.dec [new file with mode: 0644]
edk2/ArmPkg/ArmPkg.dsc [new file with mode: 0644]
edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.c [new file with mode: 0644]
edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.h [new file with mode: 0644]
edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.inf [new file with mode: 0644]
edk2/ArmPkg/Drivers/CpuDxe/DebugSupport.c [new file with mode: 0644]
edk2/ArmPkg/Drivers/CpuDxe/Exception.c [new file with mode: 0644]
edk2/ArmPkg/Drivers/CpuDxe/ExceptionSupport.S [new file with mode: 0755]
edk2/ArmPkg/Drivers/CpuDxe/ExceptionSupport.asm [new file with mode: 0755]
edk2/ArmPkg/Drivers/DebugSupportDxe/DebugSupport.c [new file with mode: 0644]
edk2/ArmPkg/Drivers/DebugSupportDxe/DebugSupportDxe.inf [new file with mode: 0644]
edk2/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.c [new file with mode: 0644]
edk2/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.h [new file with mode: 0644]
edk2/ArmPkg/Filesystem/SemihostFs/SemihostFs.inf [new file with mode: 0644]
edk2/ArmPkg/Include/AsmMacroIoLib.h [new file with mode: 0644]
edk2/ArmPkg/Include/AsmMacroIoLib.inc [new file with mode: 0644]
edk2/ArmPkg/Include/Chipset/ARM1176JZ-S.h [new file with mode: 0644]
edk2/ArmPkg/Include/Chipset/ARM926EJ-S.h [new file with mode: 0644]
edk2/ArmPkg/Include/Chipset/Cortex-A8.h [new file with mode: 0644]
edk2/ArmPkg/Include/Library/ArmLib.h [new file with mode: 0644]
edk2/ArmPkg/Include/Library/SemihostLib.h [new file with mode: 0644]
edk2/ArmPkg/Include/Library/UncachedMemoryAllocationLib.h [new file with mode: 0644]
edk2/ArmPkg/Include/Protocol/TimerDebugSupport.h [new file with mode: 0644]
edk2/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c [new file with mode: 0644]
edk2/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf [new file with mode: 0644]
edk2/ArmPkg/Library/ArmLib/Arm11/Arm11ArmLib.inf [new file with mode: 0644]
edk2/ArmPkg/Library/ArmLib/Arm11/Arm11ArmLibPrePi.inf [new file with mode: 0644]
edk2/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c [new file with mode: 0644]
edk2/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S [new file with mode: 0644]
edk2/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm [new file with mode: 0644]
edk2/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf [new file with mode: 0644]
edk2/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf [new file with mode: 0755]
edk2/ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c [new file with mode: 0644]
edk2/ArmPkg/Library/ArmLib/Arm9/Arm9Lib.c [new file with mode: 0644]
edk2/ArmPkg/Library/ArmLib/Arm9/Arm9Support.S [new file with mode: 0644]
edk2/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm [new file with mode: 0644]
edk2/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexALib.c [new file with mode: 0644]
edk2/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexALib.h [new file with mode: 0644]
edk2/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexASupport.S [new file with mode: 0644]
edk2/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexASupport.asm [new file with mode: 0644]
edk2/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLib.inf [new file with mode: 0644]
edk2/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLibPrePi.inf [new file with mode: 0644]
edk2/ArmPkg/Library/ArmLib/Common/ArmLib.c [new file with mode: 0644]
edk2/ArmPkg/Library/ArmLib/Common/ArmLibPrivate.h [new file with mode: 0644]
edk2/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S [new file with mode: 0644]
edk2/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm [new file with mode: 0644]
edk2/ArmPkg/Library/ArmLib/Null/NullArmCacheInformation.c [new file with mode: 0644]
edk2/ArmPkg/Library/ArmLib/Null/NullArmLib.c [new file with mode: 0644]
edk2/ArmPkg/Library/ArmLib/Null/NullArmLib.inf [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/Llvm_int_lib.h [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashldi3.S [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashldi3.c [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashrdi3.S [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashrdi3.c [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/clzsi2.c [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ctzsi2.c [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/div.asm [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divdi3.S [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divdi3.c [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divsi3.S [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divsi3.c [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lasr.asm [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.asm [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsl.asm [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsr.asm [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lshrdi3.S [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lshrdi3.c [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy.S [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy.asm [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memcpy4.asm [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/memset.S [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/moddi3.S [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/moddi3.c [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/modsi3.S [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/modsi3.c [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/muldi3.S [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/muldi3.c [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/mullu.asm [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch.asm [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch16.S [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch32.S [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switch8.S [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/switchu8.S [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ucmpdi2.c [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivdi3.S [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivdi3.c [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivmoddi4.S [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivmoddi4.c [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivsi3.S [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/udivsi3.c [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uldiv.asm [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/umoddi3.S [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/umoddi3.c [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/umodsi3.S [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/umodsi3.c [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uread.asm [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/uwrite.asm [new file with mode: 0644]
edk2/ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf [new file with mode: 0644]
edk2/ArmPkg/Library/SemiHostingDebugLib/DebugLib.c [new file with mode: 0644]
edk2/ArmPkg/Library/SemiHostingDebugLib/SemiHostingDebugLib.inf [new file with mode: 0644]
edk2/ArmPkg/Library/SemiHostingSerialPortLib/SemiHostingSerialPortLib.inf [new file with mode: 0644]
edk2/ArmPkg/Library/SemiHostingSerialPortLib/SerialPortLib.c [new file with mode: 0644]
edk2/ArmPkg/Library/SemihostLib/Arm/SemihostLib.c [new file with mode: 0644]
edk2/ArmPkg/Library/SemihostLib/Arm/SemihostPrivate.h [new file with mode: 0644]
edk2/ArmPkg/Library/SemihostLib/SemihostLib.inf [new file with mode: 0644]
edk2/ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.c [new file with mode: 0644]
edk2/ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf [new file with mode: 0644]
edk2/BeagleBoardPkg/AppleBeagleBoardPkg.dsc [new file with mode: 0644]
edk2/BeagleBoardPkg/AppleBeagleBoardPkg.fdf [new file with mode: 0644]
edk2/BeagleBoardPkg/Bds/Bds.inf [new file with mode: 0644]
edk2/BeagleBoardPkg/Bds/BdsEntry.c [new file with mode: 0644]
edk2/BeagleBoardPkg/Bds/BdsEntry.h [new file with mode: 0644]
edk2/BeagleBoardPkg/Bds/FirmwareVolume.c [new file with mode: 0644]
edk2/BeagleBoardPkg/BeagleBoardPkg.dec [new file with mode: 0644]
edk2/BeagleBoardPkg/BeagleBoardPkg.dsc [new file with mode: 0644]
edk2/BeagleBoardPkg/BeagleBoardPkg.fdf [new file with mode: 0644]
edk2/BeagleBoardPkg/ConfigurationHeader.dat [new file with mode: 0644]
edk2/BeagleBoardPkg/Debugger_scripts/rvi_boot_from_ram.inc [new file with mode: 0644]
edk2/BeagleBoardPkg/Debugger_scripts/rvi_convert_symbols.sh [new file with mode: 0755]
edk2/BeagleBoardPkg/Debugger_scripts/rvi_dummy.axf [new file with mode: 0755]
edk2/BeagleBoardPkg/Debugger_scripts/rvi_hw_setup.inc [new file with mode: 0644]
edk2/BeagleBoardPkg/Debugger_scripts/rvi_load_symbols.inc [new file with mode: 0644]
edk2/BeagleBoardPkg/Debugger_scripts/rvi_symbols_macros.inc [new file with mode: 0755]
edk2/BeagleBoardPkg/Debugger_scripts/rvi_unload_symbols.inc [new file with mode: 0755]
edk2/BeagleBoardPkg/Debugger_scripts/trace32_load_symbols.cmm [new file with mode: 0644]
edk2/BeagleBoardPkg/Debugger_scripts/trace32_load_symbols_cygwin.cmm [new file with mode: 0644]
edk2/BeagleBoardPkg/Flash/Flash.c [new file with mode: 0644]
edk2/BeagleBoardPkg/Flash/Flash.h [new file with mode: 0644]
edk2/BeagleBoardPkg/Flash/Flash.inf [new file with mode: 0644]
edk2/BeagleBoardPkg/Gpio/Gpio.c [new file with mode: 0644]
edk2/BeagleBoardPkg/Gpio/Gpio.inf [new file with mode: 0644]
edk2/BeagleBoardPkg/Include/Library/BeagleBoardSystemLib.h [new file with mode: 0644]
edk2/BeagleBoardPkg/Include/Library/OmapLib.h [new file with mode: 0644]
edk2/BeagleBoardPkg/Include/Omap3530/Omap3530.h [new file with mode: 0644]
edk2/BeagleBoardPkg/Include/Omap3530/Omap3530Gpio.h [new file with mode: 0644]
edk2/BeagleBoardPkg/Include/Omap3530/Omap3530Gpmc.h [new file with mode: 0644]
edk2/BeagleBoardPkg/Include/Omap3530/Omap3530I2c.h [new file with mode: 0644]
edk2/BeagleBoardPkg/Include/Omap3530/Omap3530Interrupt.h [new file with mode: 0644]
edk2/BeagleBoardPkg/Include/Omap3530/Omap3530MMCHS.h [new file with mode: 0755]
edk2/BeagleBoardPkg/Include/Omap3530/Omap3530PadConfiguration.h [new file with mode: 0644]
edk2/BeagleBoardPkg/Include/Omap3530/Omap3530Prcm.h [new file with mode: 0644]
edk2/BeagleBoardPkg/Include/Omap3530/Omap3530Timer.h [new file with mode: 0644]
edk2/BeagleBoardPkg/Include/Omap3530/Omap3530Uart.h [new file with mode: 0644]
edk2/BeagleBoardPkg/Include/Omap3530/Omap3530Usb.h [new file with mode: 0644]
edk2/BeagleBoardPkg/Include/TPS65950.h [new file with mode: 0644]
edk2/BeagleBoardPkg/InterruptDxe/HardwareInterrupt.c [new file with mode: 0644]
edk2/BeagleBoardPkg/InterruptDxe/InterruptDxe.inf [new file with mode: 0644]
edk2/BeagleBoardPkg/Library/BeagleBoardSystemLib/BeagleBoardSystemLib.c [new file with mode: 0644]
edk2/BeagleBoardPkg/Library/BeagleBoardSystemLib/BeagleBoardSystemLib.inf [new file with mode: 0644]
edk2/BeagleBoardPkg/Library/BeagleBoardSystemLib/GoLittleEndian.S [new file with mode: 0644]
edk2/BeagleBoardPkg/Library/BeagleBoardSystemLib/GoLittleEndian.asm [new file with mode: 0755]
edk2/BeagleBoardPkg/Library/BeagleBoardTimerLib/BeagleBoardTimerLib.inf [new file with mode: 0644]
edk2/BeagleBoardPkg/Library/BeagleBoardTimerLib/TimerLib.c [new file with mode: 0755]
edk2/BeagleBoardPkg/Library/EblCmdLib/EblCmdLib.c [new file with mode: 0644]
edk2/BeagleBoardPkg/Library/EblCmdLib/EblCmdLib.inf [new file with mode: 0644]
edk2/BeagleBoardPkg/Library/GdbSerialLib/GdbSerialLib.c [new file with mode: 0644]
edk2/BeagleBoardPkg/Library/GdbSerialLib/GdbSerialLib.inf [new file with mode: 0644]
edk2/BeagleBoardPkg/Library/OmapLib/OmapLib.c [new file with mode: 0644]
edk2/BeagleBoardPkg/Library/OmapLib/OmapLib.inf [new file with mode: 0644]
edk2/BeagleBoardPkg/Library/ResetSystemLib/ResetSystemLib.c [new file with mode: 0644]
edk2/BeagleBoardPkg/Library/ResetSystemLib/ResetSystemLib.inf [new file with mode: 0644]
edk2/BeagleBoardPkg/Library/SerialPortLib/SerialPortLib.c [new file with mode: 0644]
edk2/BeagleBoardPkg/Library/SerialPortLib/SerialPortLib.inf [new file with mode: 0644]
edk2/BeagleBoardPkg/MMCHSDxe/MMCHS.c [new file with mode: 0644]
edk2/BeagleBoardPkg/MMCHSDxe/MMCHS.h [new file with mode: 0755]
edk2/BeagleBoardPkg/MMCHSDxe/MMCHS.inf [new file with mode: 0644]
edk2/BeagleBoardPkg/PciEmulation/PciEmulation.c [new file with mode: 0644]
edk2/BeagleBoardPkg/PciEmulation/PciEmulation.h [new file with mode: 0644]
edk2/BeagleBoardPkg/PciEmulation/PciEmulation.inf [new file with mode: 0644]
edk2/BeagleBoardPkg/PciEmulation/PciRootBridgeIo.c [new file with mode: 0644]
edk2/BeagleBoardPkg/Sec/Arm/Macro.inc [new file with mode: 0755]
edk2/BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.S [new file with mode: 0755]
edk2/BeagleBoardPkg/Sec/Arm/ModuleEntryPoint.asm [new file with mode: 0755]
edk2/BeagleBoardPkg/Sec/Cache.c [new file with mode: 0755]
edk2/BeagleBoardPkg/Sec/Clock.c [new file with mode: 0644]
edk2/BeagleBoardPkg/Sec/PadConfiguration.c [new file with mode: 0644]
edk2/BeagleBoardPkg/Sec/Sec.c [new file with mode: 0755]
edk2/BeagleBoardPkg/Sec/Sec.inf [new file with mode: 0755]
edk2/BeagleBoardPkg/SmbusDxe/Smbus.c [new file with mode: 0644]
edk2/BeagleBoardPkg/SmbusDxe/Smbus.inf [new file with mode: 0644]
edk2/BeagleBoardPkg/TPS65950Dxe/TPS65950.c [new file with mode: 0644]
edk2/BeagleBoardPkg/TPS65950Dxe/TPS65950.inf [new file with mode: 0644]
edk2/BeagleBoardPkg/TimerDxe/Timer.c [new file with mode: 0644]
edk2/BeagleBoardPkg/TimerDxe/TimerDxe.inf [new file with mode: 0644]
edk2/BeagleBoardPkg/Tools/GNUmakefile [new file with mode: 0644]
edk2/BeagleBoardPkg/Tools/generate_image.c [new file with mode: 0644]
edk2/BeagleBoardPkg/build.sh [new file with mode: 0755]
edk2/BeagleBoardPkg/readme.txt [new file with mode: 0644]
edk2/EmbeddedPkg/DebugSupportDxe/DebugSupport.c [new file with mode: 0644]
edk2/EmbeddedPkg/DebugSupportDxe/DebugSupportDxe.inf [new file with mode: 0644]
edk2/EmbeddedPkg/Ebl/CmdTemplate.c [new file with mode: 0644]
edk2/EmbeddedPkg/Ebl/Command.c [new file with mode: 0644]
edk2/EmbeddedPkg/Ebl/Dir.c [new file with mode: 0644]
edk2/EmbeddedPkg/Ebl/Ebl.h [new file with mode: 0644]
edk2/EmbeddedPkg/Ebl/Ebl.inf [new file with mode: 0644]
edk2/EmbeddedPkg/Ebl/EfiDevice.c [new file with mode: 0644]
edk2/EmbeddedPkg/Ebl/Hob.c [new file with mode: 0644]
edk2/EmbeddedPkg/Ebl/HwDebug.c [new file with mode: 0644]
edk2/EmbeddedPkg/Ebl/HwIoDebug.c [new file with mode: 0644]
edk2/EmbeddedPkg/Ebl/Main.c [new file with mode: 0644]
edk2/EmbeddedPkg/Ebl/Network.c [new file with mode: 0644]
edk2/EmbeddedPkg/Ebl/Script.c [new file with mode: 0644]
edk2/EmbeddedPkg/EblExternCmd/EntryPointGlue.c [new file with mode: 0644]
edk2/EmbeddedPkg/EblExternCmd/Main.c [new file with mode: 0644]
edk2/EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.c [new file with mode: 0644]
edk2/EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf [new file with mode: 0644]
edk2/EmbeddedPkg/EmbeddedPkg.dec [new file with mode: 0644]
edk2/EmbeddedPkg/EmbeddedPkg.dsc [new file with mode: 0644]
edk2/EmbeddedPkg/EmbeddedPkg.fdf [new file with mode: 0644]
edk2/EmbeddedPkg/GdbStub/Arm/Processor.c [new file with mode: 0644]
edk2/EmbeddedPkg/GdbStub/GdbStub.c [new file with mode: 0644]
edk2/EmbeddedPkg/GdbStub/GdbStub.inf [new file with mode: 0644]
edk2/EmbeddedPkg/GdbStub/GdbStubInternal.h [new file with mode: 0644]
edk2/EmbeddedPkg/GdbStub/Ia32/Processor.c [new file with mode: 0644]
edk2/EmbeddedPkg/GdbStub/SerialIo.c [new file with mode: 0644]
edk2/EmbeddedPkg/GdbStub/X64/Processor.c [new file with mode: 0644]
edk2/EmbeddedPkg/Include/Library/EblAddExternalCommandLib.h [new file with mode: 0644]
edk2/EmbeddedPkg/Include/Library/EblCmdLib.h [new file with mode: 0644]
edk2/EmbeddedPkg/Include/Library/EblNetworkLib.h [new file with mode: 0644]
edk2/EmbeddedPkg/Include/Library/EfiFileLib.h [new file with mode: 0644]
edk2/EmbeddedPkg/Include/Library/EfiResetSystemLib.h [new file with mode: 0644]
edk2/EmbeddedPkg/Include/Library/GdbSerialLib.h [new file with mode: 0644]
edk2/EmbeddedPkg/Include/Library/HalRuntimeServicesLib.h [new file with mode: 0644]
edk2/EmbeddedPkg/Include/Library/PrePiLib.h [new file with mode: 0644]
edk2/EmbeddedPkg/Include/Library/RealTimeClockLib.h [new file with mode: 0644]
edk2/EmbeddedPkg/Include/Protocol/DebugSupportPeriodicCallback.h [new file with mode: 0644]
edk2/EmbeddedPkg/Include/Protocol/EblAddCommand.h [new file with mode: 0644]
edk2/EmbeddedPkg/Include/Protocol/EmbeddedDevice.h [new file with mode: 0644]
edk2/EmbeddedPkg/Include/Protocol/EmbeddedExternalDevice.h [new file with mode: 0644]
edk2/EmbeddedPkg/Include/Protocol/EmbeddedGpio.h [new file with mode: 0644]
edk2/EmbeddedPkg/Include/Protocol/HardwareInterrupt.h [new file with mode: 0644]
edk2/EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.c [new file with mode: 0644]
edk2/EmbeddedPkg/Library/EblAddExternalCommandLib/EblAddExternalCommandLib.inf [new file with mode: 0644]
edk2/EmbeddedPkg/Library/EblCmdLibNull/EblCmdLibNull.c [new file with mode: 0644]
edk2/EmbeddedPkg/Library/EblCmdLibNull/EblCmdLibNull.inf [new file with mode: 0644]
edk2/EmbeddedPkg/Library/EblNetworkLib/EblNetworkLib.c [new file with mode: 0644]
edk2/EmbeddedPkg/Library/EblNetworkLib/EblNetworkLib.inf [new file with mode: 0644]
edk2/EmbeddedPkg/Library/EfiFileLib/EfiFileLib.c [new file with mode: 0644]
edk2/EmbeddedPkg/Library/EfiFileLib/EfiFileLib.inf [new file with mode: 0644]
edk2/EmbeddedPkg/Library/GdbSerialDebugPortLib/GdbSerialDebugPortLib.c [new file with mode: 0644]
edk2/EmbeddedPkg/Library/GdbSerialDebugPortLib/GdbSerialDebugPortLib.inf [new file with mode: 0644]
edk2/EmbeddedPkg/Library/GdbSerialLib/GdbSerialLib.c [new file with mode: 0644]
edk2/EmbeddedPkg/Library/GdbSerialLib/GdbSerialLib.inf [new file with mode: 0644]
edk2/EmbeddedPkg/Library/HalRuntimeServicesExampleLib/Capsule.c [new file with mode: 0644]
edk2/EmbeddedPkg/Library/HalRuntimeServicesExampleLib/Mtc.c [new file with mode: 0644]
edk2/EmbeddedPkg/Library/HalRuntimeServicesExampleLib/ReportStatusCode.c [new file with mode: 0644]
edk2/EmbeddedPkg/Library/HalRuntimeServicesExampleLib/Reset.c [new file with mode: 0644]
edk2/EmbeddedPkg/Library/HalRuntimeServicesExampleLib/Rtc.c [new file with mode: 0644]
edk2/EmbeddedPkg/Library/HalRuntimeServicesExampleLib/Variable.c [new file with mode: 0644]
edk2/EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.c [new file with mode: 0644]
edk2/EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf [new file with mode: 0644]
edk2/EmbeddedPkg/Library/PrePiLib/FwVol.c [new file with mode: 0644]
edk2/EmbeddedPkg/Library/PrePiLib/Hob.c [new file with mode: 0644]
edk2/EmbeddedPkg/Library/PrePiLib/Memory.c [new file with mode: 0644]
edk2/EmbeddedPkg/Library/PrePiLib/PrePi.h [new file with mode: 0644]
edk2/EmbeddedPkg/Library/PrePiLib/PrePiLib.c [new file with mode: 0644]
edk2/EmbeddedPkg/Library/PrePiLib/PrePiLib.inf [new file with mode: 0644]
edk2/EmbeddedPkg/Library/PrePiLib/ReportStatusCode.c [new file with mode: 0644]
edk2/EmbeddedPkg/Library/SemiHostingDebugLib/DebugLib.c [new file with mode: 0644]
edk2/EmbeddedPkg/Library/SemiHostingDebugLib/SemiHostingDebugLib.inf [new file with mode: 0644]
edk2/EmbeddedPkg/Library/SemiHostingSerialPortLib/SemiHostingSerialPortLib.inf [new file with mode: 0644]
edk2/EmbeddedPkg/Library/SemiHostingSerialPortLib/SerialPortLib.c [new file with mode: 0644]
edk2/EmbeddedPkg/Library/TemplateRealTimeClockLib/RealTimeClockLib.c [new file with mode: 0644]
edk2/EmbeddedPkg/Library/TemplateRealTimeClockLib/TemplateRealTimeClockLib.inf [new file with mode: 0644]
edk2/EmbeddedPkg/Library/TemplateResetSystemLib/ResetSystemLib.c [new file with mode: 0644]
edk2/EmbeddedPkg/Library/TemplateResetSystemLib/TemplateResetSystemLib.inf [new file with mode: 0644]
edk2/EmbeddedPkg/Library/TemplateSerialPortLib/TemplateSerialPortLib.c [new file with mode: 0644]
edk2/EmbeddedPkg/Library/TemplateSerialPortLib/TemplateSerialPortLib.inf [new file with mode: 0644]
edk2/EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClock.c [new file with mode: 0644]
edk2/EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf [new file with mode: 0644]
edk2/EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf [new file with mode: 0644]
edk2/EmbeddedPkg/ResetRuntimeDxe/reset.c [new file with mode: 0644]
edk2/EmbeddedPkg/SerialDxe/SerialDxe.inf [new file with mode: 0644]
edk2/EmbeddedPkg/SerialDxe/SerialIo.c [new file with mode: 0644]
edk2/EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOut.c [new file with mode: 0644]
edk2/EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf [new file with mode: 0644]
edk2/EmbeddedPkg/TemplateBds/BdsEntry.c [new file with mode: 0644]
edk2/EmbeddedPkg/TemplateBds/BdsEntry.h [new file with mode: 0644]
edk2/EmbeddedPkg/TemplateBds/FirmwareVolume.c [new file with mode: 0644]
edk2/EmbeddedPkg/TemplateBds/TemplateBds.inf [new file with mode: 0644]
edk2/EmbeddedPkg/TemplateCpuDxe/Arm/Exception.c [new file with mode: 0644]
edk2/EmbeddedPkg/TemplateCpuDxe/Arm/Exceptions.S [new file with mode: 0755]
edk2/EmbeddedPkg/TemplateCpuDxe/Arm/Exceptions.asm [new file with mode: 0755]
edk2/EmbeddedPkg/TemplateCpuDxe/CpuDxe.c [new file with mode: 0644]
edk2/EmbeddedPkg/TemplateCpuDxe/CpuDxe.h [new file with mode: 0644]
edk2/EmbeddedPkg/TemplateCpuDxe/IA32/Exception.c [new file with mode: 0644]
edk2/EmbeddedPkg/TemplateCpuDxe/TemplateCpuDxe.inf [new file with mode: 0644]
edk2/EmbeddedPkg/TemplateCpuDxe/X64/Exception.c [new file with mode: 0644]
edk2/EmbeddedPkg/TemplateMetronomeDxe/Metronome.c [new file with mode: 0644]
edk2/EmbeddedPkg/TemplateMetronomeDxe/TemplateMetronomeDxe.inf [new file with mode: 0644]
edk2/EmbeddedPkg/TemplateSec/TemplateSec.c [new file with mode: 0644]
edk2/EmbeddedPkg/TemplateSec/TemplateSec.inf [new file with mode: 0644]
edk2/EmbeddedPkg/TemplateTimerDxe/TemplateTimerDxe.inf [new file with mode: 0644]
edk2/EmbeddedPkg/TemplateTimerDxe/Timer.c [new file with mode: 0644]

diff --git a/edk2/ArmPkg/ArmPkg.dec b/edk2/ArmPkg/ArmPkg.dec
new file mode 100644 (file)
index 0000000..9773f45
--- /dev/null
@@ -0,0 +1,36 @@
+#%HEADER%\r
+[Defines]\r
+  DEC_SPECIFICATION              = 0x00010005\r
+  PACKAGE_NAME                   = ArmPkg\r
+  PACKAGE_GUID                   = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F\r
+  PACKAGE_VERSION                = 0.1\r
+\r
+################################################################################\r
+#\r
+# Include Section - list of Include Paths that are provided by this package.\r
+#                   Comments are used for Keywords and Module Types.\r
+#\r
+# Supported Module Types:\r
+#  BASE SEC PEI_CORE PEIM DXE_CORE DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER UEFI_APPLICATION\r
+#\r
+################################################################################\r
+[Includes.common]\r
+  Include                        # Root include for the package\r
+\r
+[LibraryClasses.common]\r
+  SemihostLib|Include/Library/Semihosting.h\r
+\r
+[Guids.common]\r
+  gArmTokenSpaceGuid       = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }\r
+\r
+[Protocols.common]\r
+  gTimerDebugSupportProtocolGuid = { 0x68300561, 0x0197, 0x465d, { 0xb5, 0xa1, 0x28, 0xeb, 0xa1, 0x98, 0xdd, 0x0b } }\r
+\r
+[PcdsFeatureFlag.common]\r
+  gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport|FALSE|BOOLEAN|0x00000001\r
+\r
+[PcdsFixedAtBuild.common]\r
+  gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000080000000|UINT64|0x00000002\r
+  gArmTokenSpaceGuid.PcdArmCacheOperationThreshold|1024|UINT32|0x00000003\r
+  gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xfff00000|UINT32|0x00000004\r
+  gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005\r
diff --git a/edk2/ArmPkg/ArmPkg.dsc b/edk2/ArmPkg/ArmPkg.dsc
new file mode 100644 (file)
index 0000000..ca4f4fa
--- /dev/null
@@ -0,0 +1,61 @@
+#%HEADER%
+#/** @file
+#
+# ARM Package
+#
+#**/
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = ArmPkg
+  PLATFORM_GUID                  = 5CFBD99E-3C43-4E7F-8054-9CDEAFF7710F
+  PLATFORM_VERSION               = 0.1
+  DSC_SPECIFICATION              = 0x00010005
+  OUTPUT_DIRECTORY               = Build/Arm
+  SUPPORTED_ARCHITECTURES        = ARM
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+
+
+[LibraryClasses.common]
+  BaseLib|MdePkg/Library/BaseLib/BaseLib.inf
+  BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
+  CacheMaintenanceLib|ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+  DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+  MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+  PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+  PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+  TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
+  UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+  UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+  UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+  DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+  UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+
+  ArmLib|ArmPkg/Library/ArmLib/Null/NullArmLib.inf
+  SemihostLib|ArmPkg/Library/SemihostLib/SemihostLib.inf
+  UncachedMemoryAllocationLib|ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+
+
+[Components.common]
+  ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
+  ArmPkg/Library/ArmLib/Arm11/Arm11ArmLib.inf
+  ArmPkg/Library/ArmLib/Arm11/Arm11ArmLibPrePi.inf
+  ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf
+  ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf
+  ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLib.inf
+  ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLibPrePi.inf
+  ArmPkg/Library/ArmLib/Null/NullArmLib.inf
+  ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
+  ArmPkg/Library/SemiHostingDebugLib/SemiHostingDebugLib.inf
+  ArmPkg/Library/SemiHostingSerialPortLib/SemiHostingSerialPortLib.inf
+  ArmPkg/Library/SemihostLib/SemihostLib.inf
+  ArmPkg/Library/UncachedMemoryAllocationLib/UncachedMemoryAllocationLib.inf
+
+  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  ArmPkg/Drivers/DebugSupportDxe/DebugSupportDxe.inf
+  ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
diff --git a/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.c b/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.c
new file mode 100644 (file)
index 0000000..c57dac2
--- /dev/null
@@ -0,0 +1,154 @@
+/** @file\r
+\r
+  Copyright (c) 2008-2009, Apple Inc. All rights reserved.\r
+  \r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "CpuDxe.h"\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+CpuFlushCpuDataCache (\r
+  IN EFI_CPU_ARCH_PROTOCOL           *This,\r
+  IN EFI_PHYSICAL_ADDRESS            Start,\r
+  IN UINT64                          Length,\r
+  IN EFI_CPU_FLUSH_TYPE              FlushType\r
+  )\r
+{\r
+  switch (FlushType) {\r
+    case EfiCpuFlushTypeWriteBack:\r
+      WriteBackDataCacheRange((VOID *)(UINTN)Start, (UINTN)Length);\r
+      break;\r
+    case EfiCpuFlushTypeInvalidate:\r
+      InvalidateDataCacheRange((VOID *)(UINTN)Start, (UINTN)Length);\r
+      break;\r
+    case EfiCpuFlushTypeWriteBackInvalidate:\r
+      WriteBackInvalidateDataCacheRange((VOID *)(UINTN)Start, (UINTN)Length);\r
+      break;\r
+    default:\r
+      return EFI_INVALID_PARAMETER;\r
+  }\r
+  \r
+  return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+CpuEnableInterrupt (\r
+  IN EFI_CPU_ARCH_PROTOCOL          *This\r
+  )\r
+{\r
+  if (ArmProcessorMode() != ARM_PROCESSOR_MODE_IRQ) {\r
+    ArmEnableInterrupts(); \r
+  }\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+CpuDisableInterrupt (\r
+  IN EFI_CPU_ARCH_PROTOCOL          *This\r
+  )\r
+{\r
+  if (ArmProcessorMode() != ARM_PROCESSOR_MODE_IRQ) {\r
+    ArmDisableInterrupts();\r
+  }\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+CpuGetInterruptState (\r
+  IN  EFI_CPU_ARCH_PROTOCOL         *This,\r
+  OUT BOOLEAN                       *State\r
+  )\r
+{\r
+  if (State == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  *State = ArmGetInterruptState();\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+CpuInit (\r
+  IN EFI_CPU_ARCH_PROTOCOL           *This,\r
+  IN EFI_CPU_INIT_TYPE               InitType\r
+  )\r
+{\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+CpuRegisterInterruptHandler (\r
+  IN EFI_CPU_ARCH_PROTOCOL          *This,\r
+  IN EFI_EXCEPTION_TYPE             InterruptType,\r
+  IN EFI_CPU_INTERRUPT_HANDLER      InterruptHandler\r
+  )\r
+{\r
+  return RegisterInterruptHandler(InterruptType, InterruptHandler);\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+CpuGetTimerValue (\r
+  IN  EFI_CPU_ARCH_PROTOCOL          *This,\r
+  IN  UINT32                         TimerIndex,\r
+  OUT UINT64                         *TimerValue,\r
+  OUT UINT64                         *TimerPeriod   OPTIONAL\r
+  )\r
+{\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+CpuSetMemoryAttributes (\r
+  IN EFI_CPU_ARCH_PROTOCOL     *This,\r
+  IN EFI_PHYSICAL_ADDRESS      BaseAddress,\r
+  IN UINT64                    Length,\r
+  IN UINT64                    Attributes\r
+  )\r
+{\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+//\r
+// Globals used to initialize the protocol\r
+//\r
+EFI_HANDLE            mCpuHandle = NULL;\r
+EFI_CPU_ARCH_PROTOCOL mCpu = {\r
+  CpuFlushCpuDataCache,\r
+  CpuEnableInterrupt,\r
+  CpuDisableInterrupt,\r
+  CpuGetInterruptState,\r
+  CpuInit,\r
+  CpuRegisterInterruptHandler,\r
+  CpuGetTimerValue,\r
+  CpuSetMemoryAttributes,\r
+  0,          // NumberOfTimers\r
+  4,          // DmaBufferAlignment\r
+};\r
+\r
+EFI_STATUS\r
+CpuDxeInitialize (\r
+  IN EFI_HANDLE         ImageHandle,\r
+  IN EFI_SYSTEM_TABLE   *SystemTable\r
+  )\r
+{\r
+  InitializeExceptions(&mCpu);  \r
+  return gBS->InstallMultipleProtocolInterfaces(&mCpuHandle, &gEfiCpuArchProtocolGuid, &mCpu, NULL);\r
+}\r
+\r
diff --git a/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.h b/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.h
new file mode 100644 (file)
index 0000000..36133e1
--- /dev/null
@@ -0,0 +1,91 @@
+/** @file\r
+\r
+  Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>\r
+\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __CPU_DXE_ARM_EXCEPTION_H__\r
+#define __CPU_DXE_ARM_EXCEPTION_H__\r
+\r
+#include <Uefi.h>\r
+\r
+#include <Library/ArmLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/CacheMaintenanceLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+\r
+#include <Protocol/Cpu.h>\r
+#include <Protocol/DebugSupport.h>\r
+#include <Protocol/DebugSupportPeriodicCallback.h>\r
+\r
+\r
+/**\r
+  This function registers and enables the handler specified by InterruptHandler for a processor \r
+  interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the \r
+  handler for the processor interrupt or exception type specified by InterruptType is uninstalled. \r
+  The installed handler is called once for each processor interrupt or exception.\r
+\r
+  @param  InterruptType    A pointer to the processor's current interrupt state. Set to TRUE if interrupts\r
+                           are enabled and FALSE if interrupts are disabled.\r
+  @param  InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called\r
+                           when a processor interrupt occurs. If this parameter is NULL, then the handler\r
+                           will be uninstalled.\r
+\r
+  @retval EFI_SUCCESS           The handler for the processor interrupt was successfully installed or uninstalled.\r
+  @retval EFI_ALREADY_STARTED   InterruptHandler is not NULL, and a handler for InterruptType was\r
+                                previously installed.\r
+  @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not\r
+                                previously installed.\r
+  @retval EFI_UNSUPPORTED       The interrupt specified by InterruptType is not supported.\r
+\r
+**/\r
+EFI_STATUS\r
+RegisterInterruptHandler (\r
+  IN EFI_EXCEPTION_TYPE             InterruptType,\r
+  IN EFI_CPU_INTERRUPT_HANDLER      InterruptHandler\r
+  );\r
+\r
+\r
+/**\r
+  This function registers and enables the handler specified by InterruptHandler for a processor \r
+  interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the \r
+  handler for the processor interrupt or exception type specified by InterruptType is uninstalled. \r
+  The installed handler is called once for each processor interrupt or exception.\r
+\r
+  @param  InterruptType    A pointer to the processor's current interrupt state. Set to TRUE if interrupts\r
+                           are enabled and FALSE if interrupts are disabled.\r
+  @param  InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called\r
+                           when a processor interrupt occurs. If this parameter is NULL, then the handler\r
+                           will be uninstalled.\r
+\r
+  @retval EFI_SUCCESS           The handler for the processor interrupt was successfully installed or uninstalled.\r
+  @retval EFI_ALREADY_STARTED   InterruptHandler is not NULL, and a handler for InterruptType was\r
+                                previously installed.\r
+  @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not\r
+                                previously installed.\r
+  @retval EFI_UNSUPPORTED       The interrupt specified by InterruptType is not supported.\r
+\r
+**/\r
+EFI_STATUS\r
+RegisterDebuggerInterruptHandler (\r
+  IN EFI_EXCEPTION_TYPE             InterruptType,\r
+  IN EFI_CPU_INTERRUPT_HANDLER      InterruptHandler\r
+  );\r
+\r
+\r
+EFI_STATUS\r
+InitializeExceptions (\r
+       IN EFI_CPU_ARCH_PROTOCOL    *Cpu\r
+       );\r
+\r
+#endif // __CPU_DXE_ARM_EXCEPTION_H__\r
diff --git a/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.inf b/edk2/ArmPkg/Drivers/CpuDxe/CpuDxe.inf
new file mode 100644 (file)
index 0000000..314965c
--- /dev/null
@@ -0,0 +1,56 @@
+#%HEADER%\r
+#/** @file\r
+#  \r
+#  DXE CPU driver\r
+#  \r
+#  Copyright (c) 2009, Apple Inc. <BR>\r
+#  All rights reserved. This program and the accompanying materials\r
+#  are licensed and made available under the terms and conditions of the BSD License\r
+#  which accompanies this distribution.  The full text of the license may be found at\r
+#  http://opensource.org/licenses/bsd-license.php\r
+#  \r
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#  \r
+#**/\r
+\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = ArmCpuDxe\r
+  FILE_GUID                      = B8D9777E-D72A-451F-9BDB-BAFB52A68415\r
+  MODULE_TYPE                    = DXE_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+\r
+  ENTRY_POINT                    = CpuDxeInitialize\r
+\r
+[Sources.ARM]\r
+  CpuDxe.c\r
+  CpuDxe.h\r
+  DebugSupport.c\r
+  Exception.c\r
+  ExceptionSupport.asm | RVCT\r
+  ExceptionSupport.S   | GCC\r
+\r
+[Packages]\r
+  ArmPkg/ArmPkg.dec\r
+  EmbeddedPkg/EmbeddedPkg.dec\r
+  MdePkg/MdePkg.dec\r
+\r
+[LibraryClasses]\r
+  BaseMemoryLib\r
+  CacheMaintenanceLib\r
+  UefiDriverEntryPoint\r
+  ArmLib\r
+\r
+[Protocols]\r
+  gEfiCpuArchProtocolGuid\r
+  gEfiDebugSupportPeriodicCallbackProtocolGuid\r
+\r
+[Pcd.common]\r
+  gArmTokenSpaceGuid.PcdCpuVectorBaseAddress\r
+  \r
+[FeaturePcd.common]\r
+  gArmTokenSpaceGuid.PcdCpuDxeProduceDebugSupport\r
+\r
+[depex]\r
+  gHardwareInterruptProtocolGuid\r
diff --git a/edk2/ArmPkg/Drivers/CpuDxe/DebugSupport.c b/edk2/ArmPkg/Drivers/CpuDxe/DebugSupport.c
new file mode 100644 (file)
index 0000000..b8a5584
--- /dev/null
@@ -0,0 +1,247 @@
+/** @file\r
+\r
+  Copyright (c) 2008-2009, Apple Inc. All rights reserved.\r
+  \r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+/** @file\r
+  DXE Cpu Driver.\r
+  \r
+  May need some porting work for platform specifics.\r
+\r
+  Copyright (c) 2008, Apple Inc                                                        \r
+  All rights reserved. This program and the accompanying materials                          \r
+  are licensed and made available under the terms and conditions of the BSD License         \r
+  which accompanies this distribution.  The full text of the license may be found at        \r
+  http://opensource.org/licenses/bsd-license.php                                            \r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+\r
+**/\r
+\r
+#include "CpuDxe.h"\r
+\r
+EFI_PERIODIC_CALLBACK   gPeriodicCallBack = (EFI_PERIODIC_CALLBACK)NULL;\r
+\r
+EFI_DEBUG_SUPPORT_PERIODIC_CALLBACK_PROTOCOL *gDebugSupportCallback = NULL;\r
+\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+DebugSupportGetMaximumProcessorIndex (\r
+  IN EFI_DEBUG_SUPPORT_PROTOCOL       *This,\r
+  OUT UINTN                           *MaxProcessorIndex\r
+  )\r
+/*++\r
+\r
+Routine Description: This is a DebugSupport protocol member function.\r
+\r
+Arguments:\r
+  This              - The DebugSupport instance\r
+  MaxProcessorIndex - The maximuim supported processor index\r
+\r
+Returns:\r
+  Always returns EFI_SUCCESS with *MaxProcessorIndex set to 0\r
+\r
+--*/\r
+{\r
+  *MaxProcessorIndex = 0;\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+DebugSupportRegisterPeriodicCallback (\r
+  IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
+  IN UINTN                      ProcessorIndex,\r
+  IN EFI_PERIODIC_CALLBACK      PeriodicCallback\r
+  )\r
+/*++\r
+\r
+Routine Description: This is a DebugSupport protocol member function.\r
+\r
+Arguments:\r
+  This             - The DebugSupport instance\r
+  ProcessorIndex   - Which processor the callback applies to.\r
+  PeriodicCallback - Callback function\r
+\r
+Returns:\r
+\r
+  EFI_SUCCESS\r
+  EFI_INVALID_PARAMETER - requested uninstalling a handler from a vector that has\r
+                          no handler registered for it\r
+  EFI_ALREADY_STARTED   - requested install to a vector that already has a handler registered.\r
+\r
+  Other possible return values are passed through from UnHookEntry and HookEntry.\r
+\r
+--*/\r
+{\r
+  if (ProcessorIndex != 0) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+  \r
+  if ((gPeriodicCallBack != (EFI_PERIODIC_CALLBACK)NULL) && (PeriodicCallback != (EFI_PERIODIC_CALLBACK)NULL)) {\r
+    return EFI_ALREADY_STARTED;\r
+  }\r
+  \r
+  gPeriodicCallBack = PeriodicCallback;\r
+  \r
+  if (gDebugSupportCallback != NULL) {\r
+    //\r
+    // We can only update this protocol if the Register Protocol Notify has fired. If it fires \r
+    // after this call it will update with gPeriodicCallBack value.\r
+    //\r
+    gDebugSupportCallback->PeriodicCallback = gPeriodicCallBack;\r
+  }\r
+  \r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+DebugSupportRegisterExceptionCallback (\r
+  IN EFI_DEBUG_SUPPORT_PROTOCOL *This,\r
+  IN UINTN                      ProcessorIndex,\r
+  IN EFI_EXCEPTION_CALLBACK     NewCallback,\r
+  IN EFI_EXCEPTION_TYPE         ExceptionType\r
+  )\r
+/*++\r
+\r
+Routine Description:\r
+  This is a DebugSupport protocol member function.\r
+\r
+  This code executes in boot services context.\r
+\r
+Arguments:\r
+  This             - The DebugSupport instance\r
+  ProcessorIndex   - Which processor the callback applies to.\r
+  NewCallback      - Callback function\r
+  ExceptionType    - Which exception to hook\r
+\r
+Returns:\r
+\r
+  EFI_SUCCESS\r
+  EFI_INVALID_PARAMETER - requested uninstalling a handler from a vector that has\r
+                          no handler registered for it\r
+  EFI_ALREADY_STARTED   - requested install to a vector that already has a handler registered.\r
+\r
+  Other possible return values are passed through from UnHookEntry and HookEntry.\r
+\r
+--*/\r
+{\r
+  if (ProcessorIndex != 0) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  return RegisterDebuggerInterruptHandler (ExceptionType, NewCallback);\r
+}\r
+\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+DebugSupportInvalidateInstructionCache (\r
+  IN EFI_DEBUG_SUPPORT_PROTOCOL       *This,\r
+  IN UINTN                            ProcessorIndex,\r
+  IN VOID                             *Start,\r
+  IN UINT64                           Length\r
+  )\r
+/*++\r
+\r
+Routine Description:\r
+  This is a DebugSupport protocol member function.\r
+  Calls assembly routine to flush cache.\r
+\r
+Arguments:\r
+  This             - The DebugSupport instance\r
+  ProcessorIndex   - Which processor the callback applies to.\r
+  Start            - Physical base of the memory range to be invalidated\r
+  Length           - mininum number of bytes in instruction cache to invalidate\r
+\r
+Returns:\r
+\r
+  EFI_SUCCESS - always return success\r
+\r
+--*/\r
+{\r
+  if (ProcessorIndex != 0) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  InvalidateInstructionCache();\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+//\r
+// This is a global that is the actual interface\r
+//\r
+EFI_DEBUG_SUPPORT_PROTOCOL  gDebugSupportProtocolInterface = {\r
+  IsaArm, // Fixme to be more generic\r
+  DebugSupportGetMaximumProcessorIndex,\r
+  DebugSupportRegisterPeriodicCallback,\r
+  DebugSupportRegisterExceptionCallback,\r
+  DebugSupportInvalidateInstructionCache\r
+};\r
+\r
+\r
+VOID\r
+EFIAPI\r
+DebugSupportPeriodicCallbackEventProtocolNotify (\r
+  IN  EFI_EVENT       Event,\r
+  IN  VOID            *Context\r
+  )\r
+{\r
+  EFI_STATUS    Status;\r
+  \r
+  Status = gBS->LocateProtocol (&gEfiDebugSupportPeriodicCallbackProtocolGuid, NULL, (VOID **)&gDebugSupportCallback);\r
+  if (!EFI_ERROR (Status)) {\r
+    gDebugSupportCallback->PeriodicCallback = gPeriodicCallBack;\r
+  }\r
+}\r
+\r
+VOID *gRegistration = NULL;\r
+\r
+\r
+EFI_DEBUG_SUPPORT_PROTOCOL *\r
+InitilaizeDebugSupport (\r
+  VOID\r
+  )\r
+{\r
+  // RPN gEfiDebugSupportPeriodicCallbackProtocolGuid\r
+  EFI_STATUS    Status;\r
+  EFI_EVENT     Event;\r
+\r
+  if (!FeaturePcdGet (PcdCpuDxeProduceDebugSupport)) {\r
+    // Don't include this code unless Feature Flag is set\r
+    return NULL;\r
+  }\r
+  \r
+\r
+  Status = gBS->CreateEvent (\r
+                  EVT_NOTIFY_SIGNAL, \r
+                  TPL_CALLBACK, \r
+                  DebugSupportPeriodicCallbackEventProtocolNotify, \r
+                  NULL, \r
+                  &Event\r
+                  );\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  Status = gBS->RegisterProtocolNotify (&gEfiDebugSupportPeriodicCallbackProtocolGuid, Event, &gRegistration);\r
+  ASSERT_EFI_ERROR (Status);\r
+\r
+  //\r
+  // We assume the Timer must depend on our driver to register interrupts so we don't need to do\r
+  // a gBS->SignalEvent (Event) here to check to see if the protocol allready exists\r
+  //\r
+\r
+  return &gDebugSupportProtocolInterface;\r
+}\r
diff --git a/edk2/ArmPkg/Drivers/CpuDxe/Exception.c b/edk2/ArmPkg/Drivers/CpuDxe/Exception.c
new file mode 100644 (file)
index 0000000..fa256e6
--- /dev/null
@@ -0,0 +1,238 @@
+/** @file\r
+\r
+  Copyright (c) 2008-2009, Apple Inc. All rights reserved.\r
+  \r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "CpuDxe.h" \r
+#include <Library/CacheMaintenanceLib.h>\r
+\r
+VOID\r
+ExceptionHandlersStart (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+ExceptionHandlersEnd (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+CommonExceptionEntry (\r
+  VOID\r
+  );\r
+\r
+VOID\r
+AsmCommonExceptionEntry (\r
+  VOID\r
+  );\r
+\r
+\r
+EFI_EXCEPTION_CALLBACK  gExceptionHandlers[MAX_ARM_EXCEPTION + 1];\r
+EFI_EXCEPTION_CALLBACK  gDebuggerExceptionHandlers[MAX_ARM_EXCEPTION + 1];\r
+\r
+\r
+\r
+/**\r
+  This function registers and enables the handler specified by InterruptHandler for a processor \r
+  interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the \r
+  handler for the processor interrupt or exception type specified by InterruptType is uninstalled. \r
+  The installed handler is called once for each processor interrupt or exception.\r
+\r
+  @param  InterruptType    A pointer to the processor's current interrupt state. Set to TRUE if interrupts\r
+                           are enabled and FALSE if interrupts are disabled.\r
+  @param  InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called\r
+                           when a processor interrupt occurs. If this parameter is NULL, then the handler\r
+                           will be uninstalled.\r
+\r
+  @retval EFI_SUCCESS           The handler for the processor interrupt was successfully installed or uninstalled.\r
+  @retval EFI_ALREADY_STARTED   InterruptHandler is not NULL, and a handler for InterruptType was\r
+                                previously installed.\r
+  @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not\r
+                                previously installed.\r
+  @retval EFI_UNSUPPORTED       The interrupt specified by InterruptType is not supported.\r
+\r
+**/\r
+EFI_STATUS\r
+RegisterInterruptHandler (\r
+  IN EFI_EXCEPTION_TYPE             InterruptType,\r
+  IN EFI_CPU_INTERRUPT_HANDLER      InterruptHandler\r
+  )\r
+{\r
+  if (InterruptType > MAX_ARM_EXCEPTION) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  if ((InterruptHandler != NULL) && (gExceptionHandlers[InterruptType] != NULL)) {\r
+    return EFI_ALREADY_STARTED;\r
+  }\r
+\r
+  gExceptionHandlers[InterruptType] = InterruptHandler;\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+  This function registers and enables the handler specified by InterruptHandler for a processor \r
+  interrupt or exception type specified by InterruptType. If InterruptHandler is NULL, then the \r
+  handler for the processor interrupt or exception type specified by InterruptType is uninstalled. \r
+  The installed handler is called once for each processor interrupt or exception.\r
+\r
+  @param  InterruptType    A pointer to the processor's current interrupt state. Set to TRUE if interrupts\r
+                           are enabled and FALSE if interrupts are disabled.\r
+  @param  InterruptHandler A pointer to a function of type EFI_CPU_INTERRUPT_HANDLER that is called\r
+                           when a processor interrupt occurs. If this parameter is NULL, then the handler\r
+                           will be uninstalled.\r
+\r
+  @retval EFI_SUCCESS           The handler for the processor interrupt was successfully installed or uninstalled.\r
+  @retval EFI_ALREADY_STARTED   InterruptHandler is not NULL, and a handler for InterruptType was\r
+                                previously installed.\r
+  @retval EFI_INVALID_PARAMETER InterruptHandler is NULL, and a handler for InterruptType was not\r
+                                previously installed.\r
+  @retval EFI_UNSUPPORTED       The interrupt specified by InterruptType is not supported.\r
+\r
+**/\r
+EFI_STATUS\r
+RegisterDebuggerInterruptHandler (\r
+  IN EFI_EXCEPTION_TYPE             InterruptType,\r
+  IN EFI_CPU_INTERRUPT_HANDLER      InterruptHandler\r
+  )\r
+{\r
+  if (InterruptType > MAX_ARM_EXCEPTION) {\r
+    return EFI_UNSUPPORTED;\r
+  }\r
+\r
+  if ((InterruptHandler != NULL) && (gDebuggerExceptionHandlers[InterruptType] != NULL)) {\r
+    return EFI_ALREADY_STARTED;\r
+  }\r
+\r
+  gDebuggerExceptionHandlers[InterruptType] = InterruptHandler;\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+\r
+\r
+VOID\r
+EFIAPI\r
+CommonCExceptionHandler (\r
+  IN     EFI_EXCEPTION_TYPE           ExceptionType,\r
+  IN OUT EFI_SYSTEM_CONTEXT           SystemContext\r
+  )\r
+{\r
+  BOOLEAN Dispatched = FALSE;\r
+  \r
+  if (ExceptionType <= MAX_ARM_EXCEPTION) {\r
+    if (gDebuggerExceptionHandlers[ExceptionType]) {\r
+      //\r
+      // If DebugSupport hooked the interrupt call the handler. This does not disable \r
+      // the normal handler.\r
+      //\r
+      gDebuggerExceptionHandlers[ExceptionType] (ExceptionType, SystemContext);\r
+      Dispatched = TRUE;\r
+    }\r
+    if (gExceptionHandlers[ExceptionType]) {\r
+      gExceptionHandlers[ExceptionType] (ExceptionType, SystemContext);\r
+      Dispatched = TRUE;\r
+    }\r
+  }\r
+\r
+  if (Dispatched) {\r
+    //\r
+    // We did work so this was an expected ExceptionType\r
+    //\r
+    return;\r
+  }\r
+  \r
+  if (ExceptionType == EXCEPT_ARM_SOFTWARE_INTERRUPT) {\r
+    //\r
+    // ARM JTAG debuggers some times use this vector, so it is not an error to get one\r
+    //\r
+    return;\r
+  }\r
+\r
+  //\r
+  // Code after here is the default exception handler...\r
+  //\r
+  DEBUG ((EFI_D_ERROR, "Exception %d from %08x\n", ExceptionType, SystemContext.SystemContextArm->PC));\r
+  ASSERT (FALSE);\r
+\r
+}\r
+\r
+\r
+\r
+EFI_STATUS\r
+InitializeExceptions (\r
+  IN EFI_CPU_ARCH_PROTOCOL    *Cpu\r
+  )\r
+{\r
+  EFI_STATUS           Status;\r
+  UINTN                Offset;\r
+  UINTN                Length;\r
+  UINTN                Index;\r
+  BOOLEAN              Enabled;\r
+  EFI_PHYSICAL_ADDRESS Base;\r
+\r
+  //\r
+  // Disable interrupts\r
+  //\r
+  Cpu->GetInterruptState (Cpu, &Enabled);\r
+  Cpu->DisableInterrupt (Cpu);\r
+\r
+  //\r
+  // Initialize the C entry points for interrupts\r
+  //\r
+  for (Index = 0; Index <= MAX_ARM_EXCEPTION; Index++) {\r
+    Status = RegisterInterruptHandler (Index, NULL);\r
+    ASSERT_EFI_ERROR (Status);\r
+    \r
+    Status = RegisterDebuggerInterruptHandler (Index, NULL);\r
+    ASSERT_EFI_ERROR (Status);\r
+  }\r
+  \r
+  //\r
+  // Copy an implementation of the ARM exception vectors to 0x0.\r
+  //\r
+  Length = (UINTN)ExceptionHandlersEnd - (UINTN)ExceptionHandlersStart;\r
+\r
+  //\r
+  // Reserve space for the exception handlers\r
+  //\r
+  Base = (EFI_PHYSICAL_ADDRESS)PcdGet32 (PcdCpuVectorBaseAddress);\r
+  Status = gBS->AllocatePages (AllocateAddress, EfiBootServicesCode, EFI_SIZE_TO_PAGES (Length), &Base);\r
+  // If the request was for memory that's not in the memory map (which is often the case for 0x00000000\r
+  // on embedded systems, for example, we don't want to hang up.  So we'll check here for a status of \r
+  // EFI_NOT_FOUND, and continue in that case.\r
+  if (EFI_ERROR(Status) && (Status != EFI_NOT_FOUND)) {\r
+  ASSERT_EFI_ERROR (Status);\r
+  }\r
+\r
+  CopyMem ((VOID *)(UINTN)PcdGet32 (PcdCpuVectorBaseAddress), (VOID *)ExceptionHandlersStart, Length);\r
+\r
+  //\r
+  // Patch in the common Assembly exception handler\r
+  //\r
+  Offset = (UINTN)CommonExceptionEntry - (UINTN)ExceptionHandlersStart;\r
+  *(UINTN *) ((UINT8 *)(UINTN)PcdGet32 (PcdCpuVectorBaseAddress) + Offset) = (UINTN)AsmCommonExceptionEntry;\r
+\r
+  // Flush Caches since we updated executable stuff\r
+  InvalidateInstructionCacheRange((VOID *)PcdGet32(PcdCpuVectorBaseAddress), Length);\r
+\r
+  if (Enabled) {\r
+    // \r
+    // Restore interrupt state\r
+    //\r
+    Status = Cpu->EnableInterrupt (Cpu);\r
+  }\r
+\r
+  return Status;\r
+}\r
diff --git a/edk2/ArmPkg/Drivers/CpuDxe/ExceptionSupport.S b/edk2/ArmPkg/Drivers/CpuDxe/ExceptionSupport.S
new file mode 100755 (executable)
index 0000000..8574af6
--- /dev/null
@@ -0,0 +1,152 @@
+#------------------------------------------------------------------------------ 
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+.text
+.align 3
+
+.globl ASM_PFX(ExceptionHandlersStart)
+.globl ASM_PFX(ExceptionHandlersEnd)
+.globl ASM_PFX(CommonExceptionEntry)
+.globl ASM_PFX(AsmCommonExceptionEntry)
+.globl ASM_PFX(CommonCExceptionHandler)
+
+ASM_PFX(ExceptionHandlersStart):
+
+ASM_PFX(Reset):
+  b ASM_PFX(ResetEntry)
+
+ASM_PFX(UndefinedInstruction):
+  b ASM_PFX(UndefinedInstructionEntry)
+
+ASM_PFX(SoftwareInterrupt):
+  b ASM_PFX(SoftwareInterruptEntry)
+
+ASM_PFX(PrefetchAbort):
+  b ASM_PFX(PrefetchAbortEntry)
+
+ASM_PFX(DataAbort):
+  b ASM_PFX(DataAbortEntry)
+
+ASM_PFX(ReservedException):
+  b ASM_PFX(ReservedExceptionEntry)
+
+ASM_PFX(Irq):
+  b ASM_PFX(IrqEntry)
+
+ASM_PFX(Fiq):
+  b ASM_PFX(FiqEntry)
+
+ASM_PFX(ResetEntry):
+  stmfd     sp!,{r0-r1}
+  mov       r0,#0
+  ldr       r1,ASM_PFX(CommonExceptionEntry)
+  bx        r1
+
+ASM_PFX(UndefinedInstructionEntry):
+  stmfd     sp!,{r0-r1}
+  mov       r0,#1
+  ldr       r1,ASM_PFX(CommonExceptionEntry)
+  bx        r1
+
+ASM_PFX(SoftwareInterruptEntry):
+  stmfd     sp!,{r0-r1}
+  mov       r0,#2
+  ldr       r1,ASM_PFX(CommonExceptionEntry)
+  bx        r1
+
+ASM_PFX(PrefetchAbortEntry):
+  stmfd     sp!,{r0-r1}
+  mov       r0,#3
+  sub       lr,lr,#4
+  ldr       r1,ASM_PFX(CommonExceptionEntry)
+  bx        r1
+
+ASM_PFX(DataAbortEntry):
+  stmfd     sp!,{r0-r1}
+  mov       r0,#4
+  sub       lr,lr,#8
+  ldr       r1,ASM_PFX(CommonExceptionEntry)
+  bx        r1
+
+ASM_PFX(ReservedExceptionEntry):
+  stmfd     sp!,{r0-r1}
+  mov       r0,#5
+  ldr       r1,ASM_PFX(CommonExceptionEntry)
+  bx        r1
+
+ASM_PFX(IrqEntry):
+  stmfd     sp!,{r0-r1}
+  mov       r0,#6
+  sub       lr,lr,#4
+  ldr       r1,ASM_PFX(CommonExceptionEntry)
+  bx        r1
+
+ASM_PFX(FiqEntry):
+  stmfd     sp!,{r0-r1}
+  mov       r0,#7
+  sub       lr,lr,#4
+  ldr       r1,ASM_PFX(CommonExceptionEntry)
+  bx        r1
+
+ASM_PFX(CommonExceptionEntry):
+  .byte       0x12
+  .byte       0x34
+  .byte       0x56
+  .byte       0x78
+
+ASM_PFX(ExceptionHandlersEnd):
+
+ASM_PFX(AsmCommonExceptionEntry):
+  mrc       p15, 0, r1, c6, c0, 2   @ Read IFAR
+  stmfd     sp!,{r1}                @ Store the IFAR
+  
+  mrc       p15, 0, r1, c5, c0, 1   @ Read IFSR
+  stmfd     sp!,{r1}                @ Store the IFSR
+  
+  mrc       p15, 0, r1, c6, c0, 0   @ Read DFAR
+  stmfd     sp!,{r1}                @ Store the DFAR
+  
+  mrc       p15, 0, r1, c5, c0, 0   @ Read DFSR
+  stmfd     sp!,{r1}                @ Store the DFSR
+  
+  mrs       r1,spsr                 @ Read SPSR (which is the pre-exception CPSR)
+  stmfd     sp!,{r1}                @ Store the SPSR
+  
+  stmfd     sp!,{lr}                @ Store the link register (which is the pre-exception PC)
+  stmfd     sp,{sp,lr}^             @ Store user/system mode stack pointer and link register
+  nop                               @ Required by ARM architecture
+  sub       sp,sp,#0x08             @ Adjust stack pointer
+  stmfd     sp!,{r2-r12}            @ Store general purpose registers
+  
+  ldr       r3,[sp,#0x50]           @ Read saved R1 from the stack (it was saved by the exception entry routine)
+  ldr       r2,[sp,#0x4C]           @ Read saved R0 from the stack (it was saved by the exception entry routine)
+  stmfd     sp!,{r2-r3}                    @ Store general purpose registers R0 and R1
+  
+  mov       r1,sp                   @ Prepare System Context pointer as an argument for the exception handler
+  
+  sub       sp,sp,#4                @ Adjust SP to preserve 8-byte alignment
+  bl        ASM_PFX(CommonCExceptionHandler) @ Call exception handler
+  add       sp,sp,#4                @ Adjust SP back to where we were
+  
+  ldr       r2,[sp,#0x40]           @ Load CPSR from context, in case it has changed
+  msr       SPSR_cxsf,r2            @ Store it back to the SPSR to be restored when exiting this handler
+
+  ldmfd     sp!,{r0-r12}            @ Restore general purpose registers
+  ldmia     sp,{sp,lr}^             @ Restore user/system mode stack pointer and link register
+  nop                               @ Required by ARM architecture
+  add       sp,sp,#0x08             @ Adjust stack pointer
+  ldmfd     sp!,{lr}                @ Restore the link register (which is the pre-exception PC)
+  add       sp,sp,#0x1C             @ Clear out the remaining stack space
+  movs      pc,lr                   @ Return from exception
+  
diff --git a/edk2/ArmPkg/Drivers/CpuDxe/ExceptionSupport.asm b/edk2/ArmPkg/Drivers/CpuDxe/ExceptionSupport.asm
new file mode 100755 (executable)
index 0000000..d91720c
--- /dev/null
@@ -0,0 +1,152 @@
+//------------------------------------------------------------------------------ 
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+  EXPORT  ExceptionHandlersStart
+  EXPORT  ExceptionHandlersEnd
+  EXPORT  CommonExceptionEntry
+  EXPORT  AsmCommonExceptionEntry
+  IMPORT  CommonCExceptionHandler
+
+  PRESERVE8
+  AREA  DxeExceptionHandlers, CODE, READONLY
+  
+ExceptionHandlersStart
+
+Reset
+  b   ResetEntry
+
+UndefinedInstruction
+  b   UndefinedInstructionEntry
+
+SoftwareInterrupt
+  b   SoftwareInterruptEntry
+
+PrefetchAbort
+  b   PrefetchAbortEntry
+
+DataAbort
+  b   DataAbortEntry
+
+ReservedException
+  b   ReservedExceptionEntry
+
+Irq
+  b   IrqEntry
+
+Fiq
+  b   FiqEntry
+
+ResetEntry
+  stmfd     SP!,{R0-R1}
+  mov       R0,#0
+  ldr       R1,CommonExceptionEntry
+  bx        R1
+
+UndefinedInstructionEntry
+  stmfd     SP!,{R0-R1}
+  mov       R0,#1
+  ldr       R1,CommonExceptionEntry
+  bx        R1
+
+SoftwareInterruptEntry
+  stmfd     SP!,{R0-R1}
+  mov       R0,#2
+  ldr       R1,CommonExceptionEntry
+  bx        R1
+
+PrefetchAbortEntry
+  stmfd     SP!,{R0-R1}
+  mov       R0,#3
+  SUB       LR,LR,#4
+  ldr       R1,CommonExceptionEntry
+  bx        R1
+
+DataAbortEntry
+  stmfd     SP!,{R0-R1}
+  mov       R0,#4
+  SUB       LR,LR,#8
+  ldr       R1,CommonExceptionEntry
+  bx        R1
+
+ReservedExceptionEntry
+  stmfd     SP!,{R0-R1}
+  mov       R0,#5
+  ldr       R1,CommonExceptionEntry
+  bx        R1
+
+IrqEntry
+  stmfd     SP!,{R0-R1}
+  mov       R0,#6
+  SUB       LR,LR,#4
+  ldr       R1,CommonExceptionEntry
+  bx        R1
+
+FiqEntry
+  stmfd     SP!,{R0-R1}
+  mov       R0,#7
+  SUB       LR,LR,#4
+  ldr       R1,CommonExceptionEntry
+  bx        R1
+
+CommonExceptionEntry
+  dcd       0x12345678
+
+ExceptionHandlersEnd
+
+AsmCommonExceptionEntry
+  mrc       p15, 0, r1, c6, c0, 2   ; Read IFAR
+  stmfd     SP!,{R1}                ; Store the IFAR
+  
+  mrc       p15, 0, r1, c5, c0, 1   ; Read IFSR
+  stmfd     SP!,{R1}                ; Store the IFSR
+  
+  mrc       p15, 0, r1, c6, c0, 0   ; Read DFAR
+  stmfd     SP!,{R1}                ; Store the DFAR
+  
+  mrc       p15, 0, r1, c5, c0, 0   ; Read DFSR
+  stmfd     SP!,{R1}                ; Store the DFSR
+  
+  mrs       R1,SPSR                 ; Read SPSR (which is the pre-exception CPSR)
+  stmfd     SP!,{R1}                ; Store the SPSR
+  
+  stmfd     SP!,{LR}                ; Store the link register (which is the pre-exception PC)
+  stmfd     SP,{SP,LR}^             ; Store user/system mode stack pointer and link register
+  nop                               ; Required by ARM architecture
+  SUB       SP,SP,#0x08             ; Adjust stack pointer
+  stmfd     SP!,{R2-R12}            ; Store general purpose registers
+  
+  ldr       R3,[SP,#0x50]           ; Read saved R1 from the stack (it was saved by the exception entry routine)
+  ldr       R2,[SP,#0x4C]           ; Read saved R0 from the stack (it was saved by the exception entry routine)
+  stmfd     SP!,{R2-R3}             ; Store general purpose registers R0 and R1
+  
+  mov       R1,SP                   ; Prepare System Context pointer as an argument for the exception handler
+  
+  sub       SP,SP,#4                ; Adjust SP to preserve 8-byte alignment
+  blx       CommonCExceptionHandler ; Call exception handler
+  add       SP,SP,#4                ; Adjust SP back to where we were
+  
+  ldr       R2,[SP,#0x40]           ; Load CPSR from context, in case it has changed
+  MSR       SPSR_cxsf,R2            ; Store it back to the SPSR to be restored when exiting this handler
+
+  ldmfd     SP!,{R0-R12}            ; Restore general purpose registers
+  ldm       SP,{SP,LR}^             ; Restore user/system mode stack pointer and link register
+  nop                               ; Required by ARM architecture
+  add       SP,SP,#0x08             ; Adjust stack pointer
+  ldmfd     SP!,{LR}                ; Restore the link register (which is the pre-exception PC)
+  add       SP,SP,#0x1C             ; Clear out the remaining stack space
+  movs      PC,LR                   ; Return from exception
+  
+  END
+
+
diff --git a/edk2/ArmPkg/Drivers/DebugSupportDxe/DebugSupport.c b/edk2/ArmPkg/Drivers/DebugSupportDxe/DebugSupport.c
new file mode 100644 (file)
index 0000000..26f4c38
--- /dev/null
@@ -0,0 +1,119 @@
+/** @file\r
+\r
+  Copyright (c) 2008-2009, Apple Inc. All rights reserved.\r
+  \r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Uefi.h>\r
+\r
+#include <Library/CacheMaintenanceLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+\r
+#include <Protocol/Cpu.h>\r
+#include <Protocol/DebugSupport.h>\r
+#include <Protocol/TimerDebugSupport.h>\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+DebugSupportGetMaximumProcessorIndex (\r
+  IN  EFI_DEBUG_SUPPORT_PROTOCOL  *This,\r
+  OUT UINTN                       *MaxProcessorIndex\r
+  )\r
+{\r
+  if (MaxProcessorIndex == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  *MaxProcessorIndex = 0;\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+DebugSupportRegisterPeriodicCallback (\r
+  IN  EFI_DEBUG_SUPPORT_PROTOCOL  *This,\r
+  IN  UINTN                       ProcessorIndex,\r
+  IN  EFI_PERIODIC_CALLBACK       PeriodicCallback\r
+  )\r
+{\r
+  TIMER_DEBUG_SUPPORT_PROTOCOL  *Timer;\r
+  EFI_STATUS                    Status;\r
+\r
+  Status = gBS->LocateProtocol(&gTimerDebugSupportProtocolGuid, NULL, (VOID **)&Timer);\r
+  if (EFI_ERROR(Status)) {\r
+    return Status;\r
+  }\r
+\r
+  Status = Timer->RegisterPeriodicCallback(Timer, PeriodicCallback);\r
+\r
+  return Status;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+DebugSupportRegisterExceptionCallback (\r
+  IN  EFI_DEBUG_SUPPORT_PROTOCOL  *This,\r
+  IN  UINTN                       ProcessorIndex,\r
+  IN  EFI_EXCEPTION_CALLBACK      ExceptionCallback,\r
+  IN  EFI_EXCEPTION_TYPE          ExceptionType\r
+  )\r
+{\r
+  EFI_CPU_ARCH_PROTOCOL *Cpu;\r
+  EFI_STATUS            Status;\r
+\r
+  Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&Cpu);\r
+  if (EFI_ERROR(Status)) {\r
+    return Status;\r
+  }\r
+\r
+  Status = Cpu->RegisterInterruptHandler(Cpu, ExceptionType, (EFI_CPU_INTERRUPT_HANDLER)ExceptionCallback);\r
+\r
+  return Status;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+DebugSupportInvalidateInstructionCache (\r
+  IN  EFI_DEBUG_SUPPORT_PROTOCOL  *This,\r
+  IN  UINTN                       ProcessorIndex,\r
+  IN  VOID                        *Start,\r
+  IN  UINT64                      Length\r
+  )\r
+{\r
+  InvalidateInstructionCacheRange(Start, Length);\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+EFI_DEBUG_SUPPORT_PROTOCOL  mDebugSupport = {\r
+  IsaArm,\r
+  DebugSupportGetMaximumProcessorIndex,\r
+  DebugSupportRegisterPeriodicCallback,\r
+  DebugSupportRegisterExceptionCallback,\r
+  DebugSupportInvalidateInstructionCache\r
+};\r
+\r
+EFI_STATUS\r
+DebugSupportDxeInitialize (\r
+  IN EFI_HANDLE         ImageHandle,\r
+  IN EFI_SYSTEM_TABLE   *SystemTable\r
+  )\r
+{\r
+  EFI_STATUS  Status;\r
+  EFI_HANDLE  Handle = NULL;\r
+\r
+  ASSERT_PROTOCOL_ALREADY_INSTALLED (NULL, &gEfiDebugSupportProtocolGuid);\r
+  Status = gBS->InstallMultipleProtocolInterfaces(&Handle, &gEfiDebugSupportProtocolGuid, &mDebugSupport, NULL);\r
+\r
+  return Status;\r
+}\r
+\r
diff --git a/edk2/ArmPkg/Drivers/DebugSupportDxe/DebugSupportDxe.inf b/edk2/ArmPkg/Drivers/DebugSupportDxe/DebugSupportDxe.inf
new file mode 100644 (file)
index 0000000..59f4487
--- /dev/null
@@ -0,0 +1,30 @@
+#%HEADER%\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = ArmDebugSupportDxe\r
+  FILE_GUID                      = 2e7c151b-cbd8-4df6-a0e3-cde660067c6a\r
+  MODULE_TYPE                    = DXE_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+\r
+  ENTRY_POINT                    = DebugSupportDxeInitialize\r
+\r
+[Sources.common]\r
+  DebugSupport.c\r
+\r
+[Packages]\r
+  ArmPkg/ArmPkg.dec\r
+  MdePkg/MdePkg.dec\r
+\r
+[LibraryClasses]\r
+  BaseMemoryLib\r
+  CacheMaintenanceLib\r
+  UefiDriverEntryPoint\r
+  ArmLib\r
+\r
+[Protocols]\r
+  gEfiCpuArchProtocolGuid\r
+  gEfiDebugSupportProtocolGuid\r
+  gTimerDebugSupportProtocolGuid\r
+  \r
+[Depex]\r
+  TRUE
\ No newline at end of file
diff --git a/edk2/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.c b/edk2/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.c
new file mode 100644 (file)
index 0000000..0f1da65
--- /dev/null
@@ -0,0 +1,526 @@
+/** @file\r
+  Support a Semi Host file system over a debuggers JTAG\r
+\r
+  Copyright (c) 2008-2009, Apple Inc. All rights reserved.\r
+  \r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Uefi.h>\r
+\r
+#include <Guid/FileInfo.h>\r
+#include <Guid/FileSystemInfo.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/BaseMemoryLib.h> \r
+#include <Library/DebugLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/SemihostLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiLib.h>\r
+\r
+#include <Protocol/DevicePath.h>\r
+#include <Protocol/SimpleFileSystem.h>\r
+\r
+#include "SemihostFs.h"\r
+\r
+\r
+EFI_SIMPLE_FILE_SYSTEM_PROTOCOL gSemihostFs = {\r
+  EFI_SIMPLE_FILE_SYSTEM_PROTOCOL_REVISION,\r
+  VolumeOpen\r
+};\r
+\r
+EFI_FILE gSemihostFsFile = {\r
+  EFI_FILE_PROTOCOL_REVISION,\r
+  FileOpen,\r
+  FileClose,\r
+  FileDelete,\r
+  FileRead,\r
+  FileWrite,\r
+  FileGetPosition,\r
+  FileSetPosition,\r
+  FileGetInfo,\r
+  FileSetInfo,\r
+  FileFlush\r
+};\r
+\r
+//\r
+// Device path for SemiHosting. It contains our autogened Caller ID GUID.\r
+//\r
+typedef struct {\r
+  VENDOR_DEVICE_PATH        Guid;\r
+  EFI_DEVICE_PATH_PROTOCOL  End;\r
+} SEMIHOST_DEVICE_PATH;\r
+\r
+SEMIHOST_DEVICE_PATH gDevicePath = {\r
+  {\r
+    { HARDWARE_DEVICE_PATH, HW_VENDOR_DP, sizeof (VENDOR_DEVICE_PATH), 0 },\r
+    EFI_CALLER_ID_GUID\r
+  },\r
+  { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, sizeof (EFI_DEVICE_PATH_PROTOCOL), 0}\r
+};\r
+\r
+typedef struct {\r
+  LIST_ENTRY  Link;\r
+  UINT64      Signature;\r
+  EFI_FILE    File;\r
+  CHAR8       *FileName;\r
+  UINT32      Position;\r
+  UINT32      SemihostHandle;\r
+  BOOLEAN     IsRoot;\r
+} SEMIHOST_FCB;\r
+\r
+#define SEMIHOST_FCB_SIGNATURE      SIGNATURE_32( 'S', 'H', 'F', 'C' )\r
+#define SEMIHOST_FCB_FROM_THIS(a)   CR(a, SEMIHOST_FCB, File, SEMIHOST_FCB_SIGNATURE)\r
+#define SEMIHOST_FCB_FROM_LINK(a)   CR(a, SEMIHOST_FCB, Link, SEMIHOST_FCB_SIGNATURE);\r
+\r
+EFI_HANDLE  gInstallHandle = NULL;\r
+LIST_ENTRY  gFileList = INITIALIZE_LIST_HEAD_VARIABLE (gFileList);\r
+\r
+SEMIHOST_FCB *\r
+AllocateFCB (\r
+  VOID\r
+  )\r
+{\r
+  SEMIHOST_FCB *Fcb = AllocateZeroPool (sizeof (SEMIHOST_FCB));\r
+\r
+  if (Fcb != NULL) {\r
+    CopyMem (&Fcb->File, &gSemihostFsFile, sizeof (gSemihostFsFile));\r
+    Fcb->Signature = SEMIHOST_FCB_SIGNATURE;\r
+  }\r
+\r
+  return Fcb;\r
+}\r
+\r
+VOID\r
+FreeFCB (\r
+  IN SEMIHOST_FCB *Fcb\r
+  )\r
+{\r
+  // Remove Fcb from gFileList.\r
+  RemoveEntryList (&Fcb->Link);\r
+\r
+  // To help debugging...\r
+  Fcb->Signature = 0;\r
+\r
+  FreePool (Fcb);\r
+}\r
+\r
+\r
+\r
+EFI_STATUS\r
+VolumeOpen (\r
+  IN  EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This,\r
+  OUT EFI_FILE                        **Root\r
+  )\r
+{\r
+  SEMIHOST_FCB *RootFcb = NULL;\r
+  \r
+  if (Root == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  RootFcb = AllocateFCB ();\r
+  if (RootFcb == NULL) {\r
+    return EFI_OUT_OF_RESOURCES;\r
+  }\r
+  \r
+  RootFcb->IsRoot = TRUE;\r
+\r
+  InsertTailList (&gFileList, &RootFcb->Link);\r
+\r
+  *Root = &RootFcb->File;\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+FileOpen (\r
+  IN  EFI_FILE    *File,\r
+  OUT EFI_FILE    **NewHandle,\r
+  IN  CHAR16      *FileName,\r
+  IN  UINT64      OpenMode,\r
+  IN  UINT64      Attributes\r
+  )\r
+{\r
+  SEMIHOST_FCB  *FileFcb = NULL;\r
+  EFI_STATUS    Status   = EFI_SUCCESS;\r
+  UINT32        SemihostHandle;\r
+  CHAR8         *AsciiFileName;\r
+  CHAR8         *AsciiPtr;\r
+  UINTN         Length;\r
+  UINT32        SemihostMode;\r
+  BOOLEAN       IsRoot;\r
+\r
+  if ((FileName == NULL) || (NewHandle == NULL)) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  // Semihost interface requires ASCII filesnames\r
+  Length = StrSize (FileName);\r
+\r
+  AsciiFileName = AllocatePool (Length);\r
+  if (AsciiFileName == NULL) {\r
+    return EFI_OUT_OF_RESOURCES;\r
+  }\r
+\r
+  AsciiPtr = AsciiFileName;\r
+\r
+  while (Length--) {\r
+    *AsciiPtr++ = *FileName++ & 0xFF;\r
+  }\r
+\r
+  if ((AsciiStrCmp (AsciiFileName, "\\") == 0) || (AsciiStrCmp (AsciiFileName, "/") == 0) || (AsciiStrCmp (AsciiFileName, "") == 0)) {\r
+    // Opening '/', '\', or the NULL pathname is trying to open the root directory\r
+    IsRoot = TRUE;\r
+\r
+    // Root directory node doesn't have a name.\r
+    FreePool (AsciiFileName);\r
+    AsciiFileName = NULL;\r
+  } else {\r
+    // Translate EFI_FILE_MODE into Semihosting mode\r
+    if (OpenMode & EFI_FILE_MODE_WRITE) {\r
+      SemihostMode = SEMIHOST_FILE_MODE_WRITE | SEMIHOST_FILE_MODE_BINARY;\r
+    } else if (OpenMode & EFI_FILE_MODE_READ) {\r
+      SemihostMode = SEMIHOST_FILE_MODE_READ  | SEMIHOST_FILE_MODE_BINARY;\r
+    } else {\r
+      return EFI_UNSUPPORTED;\r
+    }\r
+\r
+    // Add the creation flag if necessary\r
+    if (OpenMode & EFI_FILE_MODE_CREATE) {\r
+      SemihostMode |= SEMIHOST_FILE_MODE_CREATE;\r
+    }\r
+\r
+    // Call the semihosting interface to open the file.\r
+    Status = SemihostFileOpen (AsciiFileName, SemihostMode, &SemihostHandle);\r
+    if (EFI_ERROR(Status)) {\r
+      return Status;\r
+    }\r
+    \r
+    IsRoot = FALSE;\r
+  }\r
+\r
+  // Allocate a control block and fill it\r
+  FileFcb = AllocateFCB ();\r
+  if (FileFcb == NULL) {\r
+    return EFI_OUT_OF_RESOURCES;\r
+  }\r
+\r
+  FileFcb->FileName       = AsciiFileName;\r
+  FileFcb->SemihostHandle = SemihostHandle;\r
+  FileFcb->Position       = 0;\r
+  FileFcb->IsRoot         = IsRoot;\r
+\r
+  InsertTailList (&gFileList, &FileFcb->Link);\r
+\r
+  *NewHandle = &FileFcb->File;\r
+\r
+  return Status;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+FileClose (\r
+  IN EFI_FILE *File\r
+  )\r
+{\r
+  SEMIHOST_FCB *Fcb    = NULL;\r
+  EFI_STATUS   Status  = EFI_SUCCESS;\r
+\r
+  Fcb = SEMIHOST_FCB_FROM_THIS(File);\r
+\r
+  if (Fcb->IsRoot == TRUE) {\r
+    FreeFCB (Fcb);\r
+    Status = EFI_SUCCESS;\r
+  } else {\r
+    Status = SemihostFileClose (Fcb->SemihostHandle);\r
+    if (!EFI_ERROR(Status)) {\r
+      FreePool (Fcb->FileName);\r
+      FreeFCB (Fcb);\r
+    }\r
+  }\r
+  \r
+  return Status;\r
+}\r
+\r
+EFI_STATUS\r
+FileDelete (\r
+  IN EFI_FILE *File\r
+  )\r
+{\r
+  SEMIHOST_FCB *Fcb = NULL;\r
+  EFI_STATUS   Status;\r
+  CHAR8        *FileName;\r
+  UINTN        NameSize;\r
+\r
+  Fcb = SEMIHOST_FCB_FROM_THIS(File);\r
+\r
+  // Get the filename from the Fcb\r
+  NameSize = AsciiStrLen (Fcb->FileName);\r
+  FileName = AllocatePool (NameSize + 1);\r
+\r
+  AsciiStrCpy (FileName, Fcb->FileName);\r
+\r
+  // Close the file if it's open.  Disregard return status,\r
+  // since it might give an error if the file isn't open.\r
+  File->Close (File);\r
+    \r
+  // Call the semihost interface to delete the file.\r
+  Status = SemihostFileRemove (FileName);\r
+\r
+  return Status;\r
+}\r
+\r
+EFI_STATUS\r
+FileRead (\r
+  IN     EFI_FILE *File,\r
+  IN OUT UINTN    *BufferSize,\r
+  OUT    VOID     *Buffer\r
+  )\r
+{\r
+  SEMIHOST_FCB *Fcb = NULL;\r
+  EFI_STATUS   Status;\r
+\r
+  Fcb = SEMIHOST_FCB_FROM_THIS(File);\r
+\r
+  if (Fcb->IsRoot == TRUE) {\r
+    Status = EFI_UNSUPPORTED;\r
+  } else {\r
+    Status = SemihostFileRead (Fcb->SemihostHandle, BufferSize, Buffer);\r
+    if (!EFI_ERROR (Status)) {\r
+      Fcb->Position += *BufferSize;\r
+    }\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+EFI_STATUS\r
+FileWrite (\r
+  IN     EFI_FILE *File,\r
+  IN OUT UINTN    *BufferSize,\r
+  IN     VOID     *Buffer\r
+  )\r
+{\r
+  SEMIHOST_FCB *Fcb    = NULL;\r
+  EFI_STATUS   Status;\r
+  UINTN        WriteSize = *BufferSize;\r
+\r
+  Fcb = SEMIHOST_FCB_FROM_THIS(File);\r
+\r
+  Status = SemihostFileWrite (Fcb->SemihostHandle, &WriteSize, Buffer);\r
+\r
+  if (!EFI_ERROR(Status)) {\r
+    // Semihost write return the number of bytes *NOT* written.\r
+    *BufferSize -= WriteSize;\r
+    Fcb->Position += *BufferSize;\r
+  }\r
+  \r
+  return Status;\r
+}\r
+\r
+EFI_STATUS\r
+FileGetPosition (\r
+  IN  EFI_FILE    *File,\r
+  OUT UINT64      *Position\r
+  )\r
+{\r
+  SEMIHOST_FCB *Fcb = NULL;\r
+    \r
+  if (Position == NULL) {\r
+    return EFI_INVALID_PARAMETER;\r
+  }\r
+\r
+  Fcb = SEMIHOST_FCB_FROM_THIS(File);\r
+\r
+  *Position = Fcb->Position;\r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+FileSetPosition (\r
+  IN EFI_FILE *File,\r
+  IN UINT64   Position\r
+  )\r
+{\r
+  SEMIHOST_FCB *Fcb    = NULL;\r
+  UINT32       Length;\r
+  EFI_STATUS   Status;\r
+\r
+  Fcb = SEMIHOST_FCB_FROM_THIS(File);\r
+\r
+  Status = SemihostFileLength (Fcb->SemihostHandle, &Length);\r
+  if (!EFI_ERROR(Status) && (Length < Position)) {\r
+    Position = Length;\r
+  }\r
+\r
+  Status = SemihostFileSeek (Fcb->SemihostHandle, (UINT32)Position);\r
+  if (!EFI_ERROR(Status)) {\r
+    Fcb->Position = Position;\r
+  }\r
+\r
+  return Status;\r
+}\r
+\r
+STATIC\r
+EFI_STATUS\r
+GetFileInfo (\r
+  IN     SEMIHOST_FCB  *Fcb,\r
+  IN OUT UINTN        *BufferSize,\r
+  OUT    VOID         *Buffer\r
+  )\r
+{\r
+  EFI_FILE_INFO   *Info = NULL;\r
+  UINTN           NameSize = 0;\r
+  UINTN           ResultSize;\r
+  UINTN           Index;\r
+  UINT32          Length;\r
+  EFI_STATUS      Status;\r
+\r
+  if (Fcb->IsRoot == TRUE) {\r
+    ResultSize = SIZE_OF_EFI_FILE_INFO + sizeof(CHAR16);\r
+  } else {\r
+    NameSize   = AsciiStrLen (Fcb->FileName) + 1;\r
+    ResultSize = SIZE_OF_EFI_FILE_INFO + NameSize * sizeof (CHAR16);\r
+  }\r
+\r
+  if (*BufferSize < ResultSize) {\r
+    *BufferSize = ResultSize;\r
+    return EFI_BUFFER_TOO_SMALL;\r
+  }\r
+\r
+  Info = Buffer;\r
+\r
+  // Zero out the structure\r
+  ZeroMem (Info, SIZE_OF_EFI_FILE_INFO);\r
+\r
+  // Fill in the structure\r
+  Info->Size = ResultSize;\r
+\r
+  if (Fcb->IsRoot == TRUE) {\r
+    Info->Attribute    = EFI_FILE_READ_ONLY | EFI_FILE_DIRECTORY;\r
+    Info->FileName[0]  = L'\0';\r
+  } else {\r
+    Status = SemihostFileLength (Fcb->SemihostHandle, &Length);\r
+    if (EFI_ERROR(Status)) {\r
+      return Status;\r
+    }\r
+\r
+    Info->FileSize     = Length;\r
+    Info->PhysicalSize = Length;\r
+\r
+    for (Index = 0; Index < NameSize; Index++) {\r
+      Info->FileName[Index] = Fcb->FileName[Index];            \r
+    }\r
+  }\r
+\r
+\r
+  *BufferSize = ResultSize;    \r
+\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+STATIC\r
+EFI_STATUS\r
+GetFilesystemInfo (\r
+  IN     SEMIHOST_FCB *Fcb,\r
+  IN OUT UINTN        *BufferSize,\r
+  OUT    VOID         *Buffer\r
+  )\r
+{\r
+  EFI_FILE_SYSTEM_INFO    *Info = NULL;\r
+  EFI_STATUS              Status;\r
+  STATIC CHAR16           Label[] = L"SemihostFs";\r
+  UINTN                   ResultSize = SIZE_OF_EFI_FILE_SYSTEM_INFO + StrSize(Label);\r
+    \r
+  if(*BufferSize >= ResultSize) {\r
+    ZeroMem (Buffer, ResultSize);\r
+    Status = EFI_SUCCESS;\r
+        \r
+    Info = Buffer;\r
+\r
+    Info->Size       = ResultSize;\r
+    Info->ReadOnly   = FALSE;\r
+    Info->VolumeSize = 0;\r
+    Info->FreeSpace  = 0;\r
+    Info->BlockSize  = 0;\r
+\r
+    StrCpy (Info->VolumeLabel, Label);\r
+  } else {\r
+    Status = EFI_BUFFER_TOO_SMALL;\r
+  }\r
+\r
+  *BufferSize = ResultSize;    \r
+  return Status;\r
+}\r
+\r
+EFI_STATUS\r
+FileGetInfo (\r
+  IN     EFI_FILE *File,\r
+  IN     EFI_GUID *InformationType,\r
+  IN OUT UINTN    *BufferSize,\r
+  OUT    VOID     *Buffer\r
+  )\r
+{\r
+  SEMIHOST_FCB *Fcb = NULL;\r
+  EFI_STATUS   Status = EFI_UNSUPPORTED;\r
+  \r
+  Fcb = SEMIHOST_FCB_FROM_THIS(File);\r
+  \r
+  if (CompareGuid(InformationType, &gEfiFileSystemInfoGuid) != 0) {\r
+    Status = GetFilesystemInfo(Fcb, BufferSize, Buffer);  \r
+  } else if (CompareGuid(InformationType, &gEfiFileInfoGuid) != 0) {\r
+    Status = GetFileInfo(Fcb, BufferSize, Buffer);  \r
+  }\r
+    \r
+  return Status;\r
+}\r
+\r
+EFI_STATUS\r
+FileSetInfo (\r
+  IN EFI_FILE *File,\r
+  IN EFI_GUID *InformationType,\r
+  IN UINTN    BufferSize,\r
+  IN VOID     *Buffer\r
+  )\r
+{\r
+  return EFI_UNSUPPORTED;\r
+}\r
+\r
+EFI_STATUS\r
+FileFlush (\r
+  IN EFI_FILE *File\r
+  )\r
+{\r
+  return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+SemihostFsEntryPoint (\r
+  IN EFI_HANDLE           ImageHandle,\r
+  IN EFI_SYSTEM_TABLE     *SystemTable\r
+  )\r
+{\r
+  EFI_STATUS    Status = EFI_NOT_FOUND;\r
+\r
+  if (SemihostConnectionSupported ()) {\r
+    Status = gBS->InstallMultipleProtocolInterfaces (\r
+                    &gInstallHandle, \r
+                    &gEfiSimpleFileSystemProtocolGuid, &gSemihostFs, \r
+                    &gEfiDevicePathProtocolGuid,       &gDevicePath,\r
+                    NULL\r
+                    );\r
+  }\r
\r
+  return Status;\r
+}\r
+\r
diff --git a/edk2/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.h b/edk2/ArmPkg/Filesystem/SemihostFs/Arm/SemihostFs.h
new file mode 100644 (file)
index 0000000..f058d92
--- /dev/null
@@ -0,0 +1,114 @@
+/** @file\r
+  Support a Semi Host file system over a debuggers JTAG\r
+\r
+  Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>\r
+\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __SEMIHOST_FS_H__\r
+#define __SEMIHOST_FS_H__\r
+\r
+EFI_STATUS\r
+SemihostFsSupported(\r
+  IN EFI_DRIVER_BINDING_PROTOCOL  *This,\r
+  IN EFI_HANDLE                   Controller,\r
+  IN EFI_DEVICE_PATH_PROTOCOL     *RemainingDevicePath\r
+  );\r
+\r
+EFI_STATUS\r
+SemihostFsStart(\r
+  IN EFI_DRIVER_BINDING_PROTOCOL  *This,\r
+  IN EFI_HANDLE                   Controller,\r
+  IN EFI_DEVICE_PATH_PROTOCOL     *RemainingDevicePath\r
+  );\r
+\r
+EFI_STATUS\r
+SemihostFsStop(\r
+  IN EFI_DRIVER_BINDING_PROTOCOL  *This,\r
+  IN EFI_HANDLE                   Controller,\r
+  IN UINTN                        NumberOfChildren,\r
+  IN EFI_HANDLE                   *ChildHandleBuffer\r
+  );\r
+\r
+EFI_STATUS\r
+VolumeOpen(\r
+  IN  EFI_SIMPLE_FILE_SYSTEM_PROTOCOL *This,\r
+  OUT EFI_FILE                        **Root\r
+  );\r
+\r
+EFI_STATUS\r
+FileOpen(\r
+  IN  EFI_FILE  *File,\r
+  OUT EFI_FILE  **NewHandle,\r
+  IN  CHAR16    *FileName,\r
+  IN  UINT64    OpenMode,\r
+  IN  UINT64    Attributes\r
+  );\r
+\r
+EFI_STATUS\r
+FileClose(\r
+  IN EFI_FILE *File\r
+  );\r
+\r
+EFI_STATUS\r
+FileDelete(\r
+  IN EFI_FILE *File\r
+  );\r
+\r
+EFI_STATUS\r
+FileRead(\r
+  IN     EFI_FILE *File,\r
+  IN OUT UINTN    *BufferSize,\r
+  OUT    VOID     *Buffer\r
+  );\r
+\r
+EFI_STATUS\r
+FileWrite(\r
+  IN     EFI_FILE *File,\r
+  IN OUT UINTN    *BufferSize,\r
+  IN     VOID     *Buffer\r
+  );\r
+\r
+EFI_STATUS\r
+FileGetPosition(\r
+  IN  EFI_FILE  *File,\r
+  OUT UINT64    *Position\r
+  );\r
+\r
+EFI_STATUS\r
+FileSetPosition(\r
+  IN EFI_FILE *File,\r
+  IN UINT64   Position\r
+  );\r
+\r
+EFI_STATUS\r
+FileGetInfo(\r
+  IN     EFI_FILE *File,\r
+  IN     EFI_GUID *InformationType,\r
+  IN OUT UINTN    *BufferSize,\r
+  OUT    VOID     *Buffer\r
+  );\r
+\r
+EFI_STATUS\r
+FileSetInfo(\r
+  IN EFI_FILE *File,\r
+  IN EFI_GUID *InformationType,\r
+  IN UINTN    BufferSize,\r
+  IN VOID     *Buffer\r
+  );\r
+\r
+EFI_STATUS\r
+FileFlush(\r
+  IN EFI_FILE *File\r
+  );\r
+\r
+#endif // __SEMIHOST_FS_H__\r
+\r
diff --git a/edk2/ArmPkg/Filesystem/SemihostFs/SemihostFs.inf b/edk2/ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
new file mode 100644 (file)
index 0000000..7fca293
--- /dev/null
@@ -0,0 +1,48 @@
+#%HEADER%
+#/** @file
+#  Support a Semi Host file system over a debuggers JTAG
+#
+#  Copyright (c) 2009, Apple, Inc.                                                         
+#  All rights reserved. This program and the accompanying materials                          
+#  are licensed and made available under the terms and conditions of the BSD License         
+#  which accompanies this distribution.  The full text of the license may be found at        
+#  http://opensource.org/licenses/bsd-license.php                                            
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = SemihostFs
+  FILE_GUID                      = C5B9C74A-6D72-4719-99AB-C59F199091EB
+  MODULE_TYPE                    = UEFI_DRIVER
+  VERSION_STRING                 = 1.0
+
+  ENTRY_POINT                    = SemihostFsEntryPoint
+
+
+[Sources.ARM]
+  Arm/SemihostFs.c
+  
+[Packages]
+  MdePkg/MdePkg.dec
+  ArmPkg/ArmPkg.dec
+
+[LibraryClasses]
+  BaseLib
+  MemoryAllocationLib
+  SemihostLib
+  UefiDriverEntryPoint
+  UefiLib
+
+[Guids]
+  gEfiFileSystemInfoGuid
+  gEfiFileInfoGuid
+  gEfiFileSystemVolumeLabelInfoIdGuid
+
+[Protocols]
+  gEfiSimpleFileSystemProtocolGuid
+  gEfiDevicePathProtocolGuid
+  
diff --git a/edk2/ArmPkg/Include/AsmMacroIoLib.h b/edk2/ArmPkg/Include/AsmMacroIoLib.h
new file mode 100644 (file)
index 0000000..aa3ed61
--- /dev/null
@@ -0,0 +1,236 @@
+/** @file\r
+  Macros to work around lack of Apple support for LDR register, =expr\r
+\r
+  Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>\r
+\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#ifndef __MACRO_IO_LIB_H__\r
+#define __MACRO_IO_LIB_H__\r
+\r
+#if defined(__APPLE__)\r
+\r
+//\r
+//  ldr reg, =expr does not work with current Apple tool chain. So do the work our selves\r
+//\r
+\r
+// returns _Data in R0 and _Address in R1\r
+#define MmioWrite32(_Address, _Data) \\r
+  ldr  r1, [pc, #8]     ;            \\r
+  ldr  r0, [pc, #8]     ;            \\r
+  str  r0, [r1]         ;            \\r
+  b    1f               ;            \\r
+  .long (_Address)      ;            \\r
+  .long (_Data) ;                    \\r
+1:\r
+\r
+// returns _Data in R0 and _Address in R1, and _OrData in r2\r
+#define MmioOr32(_Address, _OrData) \\r
+  ldr  r1, [pc, #16]    ;           \\r
+  ldr  r2, [pc, #16]    ;           \\r
+  ldr  r0, [r1]         ;           \\r
+  orr  r0, r0, r2       ;           \\r
+  str  r0, [r1]         ;           \\r
+  b    1f               ;           \\r
+  .long (_Address)      ;           \\r
+  .long (_OrData)       ;           \\r
+1:\r
+\r
+// returns _Data in R0 and _Address in R1, and _OrData in r2\r
+#define MmioAnd32(_Address, _AndData) \\r
+  ldr  r1, [pc, #16]    ;             \\r
+  ldr  r2, [pc, #16]    ;             \\r
+  ldr  r0, [r1]         ;             \\r
+  and  r0, r0, r2       ;             \\r
+  str  r0, [r1]         ;             \\r
+  b    1f               ;             \\r
+  .long (_Address)      ;             \\r
+  .long (_AndData)       ;             \\r
+1:\r
+\r
+// returns result in R0, _Address in R1, and _OrData in r2\r
+#define MmioAndThenOr32(_Address, _AndData, _OrData)  \\r
+  ldr  r1, [pc, #24]    ;                             \\r
+  ldr  r0, [r1]         ;                             \\r
+  ldr  r2, [pc, #20]    ;                             \\r
+  and  r0, r0, r2       ;                             \\r
+  ldr  r2, [pc, #16]    ;                             \\r
+  orr  r0, r0, r2       ;                             \\r
+  str  r0, [r1]         ;                             \\r
+  b    1f               ;                             \\r
+  .long (_Address)      ;                             \\r
+  .long (_AndData)      ;                             \\r
+  .long (_OrData)       ;                             \\r
+1:\r
+\r
+// returns _Data in _Reg and _Address in R1\r
+#define MmioWriteFromReg32(_Address, _Reg) \\r
+  ldr  r1, [pc, #4]     ;                  \\r
+  str  _Reg, [r1]       ;                  \\r
+  b    1f               ;                  \\r
+  .long (_Address)      ;                  \\r
+1:\r
+\r
+\r
+// returns _Data in R0 and _Address in R1\r
+#define MmioRead32(_Address)   \\r
+  ldr  r1, [pc, #4]     ;      \\r
+  ldr  r0, [r1]         ;      \\r
+  b    1f               ;      \\r
+  .long (_Address)      ;      \\r
+1:\r
+\r
+// returns _Data in Reg and _Address in R1\r
+#define MmioReadToReg32(_Address, _Reg) \\r
+  ldr  r1, [pc, #4]     ;               \\r
+  ldr  _Reg, [r1]       ;               \\r
+  b    1f               ;               \\r
+  .long (_Address)      ;               \\r
+1:\r
+\r
+\r
+// load R0 with _Data\r
+#define LoadConstant(_Data)  \\r
+  ldr  r0, [pc, #0]     ;    \\r
+  b    1f               ;    \\r
+  .long (_Data)         ;    \\r
+1:\r
+\r
+// load _Reg with _Data\r
+#define LoadConstantToReg(_Data, _Reg)  \\r
+  ldr  _Reg, [pc, #0]   ;               \\r
+  b    1f               ;               \\r
+  .long (_Data)         ;               \\r
+1:\r
+\r
+// load _Reg with _Data if eq\r
+#define LoadConstantToRegIfEq(_Data, _Reg)  \\r
+  ldreq  _Reg, [pc, #0]   ;                 \\r
+  b    1f                 ;                 \\r
+  .long (_Data)           ;                 \\r
+1:\r
+\r
+\r
+#elif defined (__GNUC__)\r
+\r
+#define MmioWrite32(Address, Data) \\r
+  ldr  r1, =Address ;              \\r
+  ldr  r0, =Data    ;              \\r
+  str  r0, [r1]\r
+    \r
+#define MmioOr32(Address, OrData) \\r
+  ldr  r1, =Address ;             \\r
+  ldr  r2, =OrData  ;             \\r
+  ldr  r0, [r1]     ;             \\r
+  orr  r0, r0, r2   ;             \\r
+  str  r0, [r1]\r
+\r
+#define MmioAnd32(Address, AndData) \\r
+  ldr  r1, =Address ;               \\r
+  ldr  r2, =AndData ;               \\r
+  ldr  r0, [r1]     ;               \\r
+  and  r0, r0, r2   ;               \\r
+  str  r0, [r1]\r
+\r
+#define MmioAndThenOr32(Address, AndData, OrData) \\r
+  ldr  r1, =Address ;                             \\r
+  ldr  r0, [r1]     ;                             \\r
+  ldr  r2, =AndData ;                             \\r
+  and  r0, r0, r2   ;                             \\r
+  ldr  r2, =OrData  ;                             \\r
+  orr  r0, r0, r2   ;                             \\r
+  str  r0, [r1]         \r
+\r
+#define MmioWriteFromReg32(Address, Reg) \\r
+  ldr  r1, =Address ;                    \\r
+  str  Reg, [r1]\r
+\r
+#define MmioRead32(Address) \\r
+  ldr  r1, =Address ;       \\r
+  ldr  r0, [r1]\r
+\r
+#define MmioReadToReg32(Address, Reg) \\r
+  ldr  r1, =Address ;                 \\r
+  ldr  Reg, [r1]\r
+\r
+#define LoadConstant(Data) \\r
+  ldr  r0, =Data\r
+\r
+#define LoadConstantToReg(Data, Reg) \\r
+  ldr  Reg, =Data\r
+  \r
+#else\r
+\r
+//\r
+// Use ARM assembly macros, form armasam \r
+//\r
+//  Less magic in the macros if ldr reg, =expr works\r
+//\r
+\r
+// returns _Data in R0 and _Address in R1\r
+\r
+\r
+\r
+#define MmioWrite32(Address, Data) MmioWrite32Macro Address, Data\r
+\r
+\r
+\r
+\r
+// returns Data in R0 and Address in R1, and OrData in r2\r
+#define MmioOr32(Address, OrData) MmioOr32Macro Address, OrData\r
+  \r
+\r
+// returns _Data in R0 and _Address in R1, and _OrData in r2\r
+\r
+\r
+#define MmioAnd32(Address, AndData)  MmioAnd32Macro Address, AndData\r
+\r
+// returns result in R0, _Address in R1, and _OrData in r2\r
+\r
+\r
+#define MmioAndThenOr32(Address, AndData, OrData) MmioAndThenOr32Macro Address, AndData, OrData\r
+\r
+\r
+// returns _Data in _Reg and _Address in R1\r
+\r
+\r
+#define MmioWriteFromReg32(Address, Reg) MmioWriteFromReg32Macro Address, Reg\r
+\r
+// returns _Data in R0 and _Address in R1\r
+\r
+\r
+#define MmioRead32(Address)  MmioRead32Macro Address\r
+\r
+// returns _Data in Reg and _Address in R1\r
+\r
+\r
+#define MmioReadToReg32(Address, Reg) MmioReadToReg32Macro Address, Reg\r
+\r
+\r
+// load R0 with _Data\r
+\r
+\r
+#define LoadConstant(Data)  LoadConstantMacro Data\r
+\r
+// load _Reg with _Data\r
+\r
+\r
+#define LoadConstantToReg(Data, Reg)  LoadConstantToRegMacro Data, Reg\r
+\r
+// conditional load testing eq flag\r
+#define LoadConstantToRegIfEq(Data, Reg)  LoadConstantToRegIfEqMacro Data, Reg\r
+\r
+\r
+#endif\r
+\r
+\r
+#endif\r
diff --git a/edk2/ArmPkg/Include/AsmMacroIoLib.inc b/edk2/ArmPkg/Include/AsmMacroIoLib.inc
new file mode 100644 (file)
index 0000000..23f3c44
--- /dev/null
@@ -0,0 +1,74 @@
+;%HEADER%\r
+;/** @file\r
+;  Macros to work around lack of Apple support for LDR register, =expr\r
+;\r
+;  Copyright (c) 2009, Apple, Inc.  All rights reserved.\r
+;\r
+;**/\r
+\r
+\r
+  MACRO \r
+  MmioWrite32Macro $Address, $Data \r
+  ldr  r1, = ($Address)                \r
+  ldr  r0, = ($Data)                 \r
+  str  r0, [r1]  \r
+  MEND\r
+    \r
+  MACRO \r
+  MmioOr32Macro $Address, $OrData \r
+  ldr  r1, =($Address)               \r
+  ldr  r2, =($OrData)                \r
+  ldr  r0, [r1]                      \r
+  orr  r0, r0, r2                    \r
+  str  r0, [r1] \r
+  MEND\r
+\r
+  MACRO \r
+  MmioAnd32Macro $Address, $AndData \r
+  ldr  r1, =($Address)                 \r
+  ldr  r2, =($AndData)                 \r
+  ldr  r0, [r1]                        \r
+  and  r0, r0, r2                      \r
+  str  r0, [r1] \r
+  MEND\r
+\r
+  MACRO \r
+  MmioAndThenOr32Macro $Address, $AndData, $OrData \r
+  ldr  r1, =($Address)                         \r
+  ldr  r0, [r1]                                        \r
+  ldr  r2, =($AndData)                                 \r
+  and  r0, r0, r2                                      \r
+  ldr  r2, =($OrData)                                  \r
+  orr  r0, r0, r2                                      \r
+  str  r0, [r1]          \r
+  MEND\r
+\r
+  MACRO \r
+  MmioWriteFromReg32Macro $Address, $Reg \r
+  ldr  r1, =($Address)   \r
+  str  $Reg, [r1]        \r
+  MEND\r
+\r
+  MACRO \r
+  MmioRead32Macro $Address   \r
+  ldr  r1, =($Address)         \r
+  ldr  r0, [r1]   \r
+  MEND\r
+\r
+  MACRO \r
+  MmioReadToReg32Macro $Address, $Reg \r
+  ldr  r1, =($Address)                   \r
+  ldr  $Reg, [r1]        \r
+  MEND\r
+\r
+  MACRO \r
+  LoadConstantMacro $Data \r
+  ldr  r0, =($Data) \r
+  MEND\r
+\r
+  MACRO \r
+  LoadConstantToRegMacro $Data, $Reg \r
+  ldr  $Reg, =($Data) \r
+  MEND \r
+\r
+  END\r
diff --git a/edk2/ArmPkg/Include/Chipset/ARM1176JZ-S.h b/edk2/ArmPkg/Include/Chipset/ARM1176JZ-S.h
new file mode 100644 (file)
index 0000000..2331f8e
--- /dev/null
@@ -0,0 +1,111 @@
+/** @file\r
+\r
+  Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>\r
+\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __ARM1176JZ_S_H__\r
+#define __ARM1176JZ_S_H__\r
+\r
+// Domain Access Control Register\r
+#define DOMAIN_ACCESS_CONTROL_MASK(a)     (3UL << (2 * (a)))\r
+#define DOMAIN_ACCESS_CONTROL_NONE(a)     (0UL << (2 * (a)))\r
+#define DOMAIN_ACCESS_CONTROL_CLIENT(a)   (1UL << (2 * (a)))\r
+#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))\r
+#define DOMAIN_ACCESS_CONTROL_MANAGER(a)  (3UL << (2 * (a)))\r
+\r
+#define TRANSLATION_TABLE_SIZE            (16 * 1024)\r
+#define TRANSLATION_TABLE_ALIGNMENT       (16 * 1024)\r
+#define TRANSLATION_TABLE_ALIGNMENT_MASK  (TRANSLATION_TABLE_ALIGNMENT - 1)\r
+\r
+#define TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(table, address) ((UINT32 *)(table) + (((UINTN)(address)) >> 20))\r
+\r
+// Translation table descriptor types\r
+#define TT_DESCRIPTOR_TYPE_MASK         ((1UL << 18) | (3UL << 0))\r
+#define TT_DESCRIPTOR_TYPE_PAGE_TABLE   ((0UL << 18) | (1UL << 0))\r
+#define TT_DESCRIPTOR_TYPE_SECTION      ((0UL << 18) | (2UL << 0))\r
+#define TT_DESCRIPTOR_TYPE_SUPERSECTION ((1UL << 18) | (2UL << 0))\r
+\r
+// Section descriptor definitions\r
+#define TT_DESCRIPTOR_SECTION_SIZE                              (0x00100000)\r
+\r
+#define TT_DESCRIPTOR_SECTION_NS_MASK                           (1UL << 19)\r
+#define TT_DESCRIPTOR_SECTION_NS_SECURE                         (0UL << 19)\r
+#define TT_DESCRIPTOR_SECTION_NS_NON_SECURE                     (1UL << 19)\r
+\r
+#define TT_DESCRIPTOR_SECTION_NG_MASK                           (1UL << 17)\r
+#define TT_DESCRIPTOR_SECTION_NG_GLOBAL                         (0UL << 17)\r
+#define TT_DESCRIPTOR_SECTION_NG_LOCAL                          (1UL << 17)\r
+\r
+#define TT_DESCRIPTOR_SECTION_S_MASK                            (1UL << 16)\r
+#define TT_DESCRIPTOR_SECTION_S_NOT_SHARED                      (0UL << 16)\r
+#define TT_DESCRIPTOR_SECTION_S_SHARED                          (1UL << 16)\r
+\r
+#define TT_DESCRIPTOR_SECTION_AP_MASK                           ((1UL << 15) | (3UL << 10))\r
+#define TT_DESCRIPTOR_SECTION_AP_NO_NO                          ((0UL << 15) | (0UL << 10))\r
+#define TT_DESCRIPTOR_SECTION_AP_RW_NO                          ((0UL << 15) | (1UL << 10))\r
+#define TT_DESCRIPTOR_SECTION_AP_RW_RO                          ((0UL << 15) | (2UL << 10))\r
+#define TT_DESCRIPTOR_SECTION_AP_RW_RW                          ((0UL << 15) | (3UL << 10))\r
+#define TT_DESCRIPTOR_SECTION_AP_RO_NO                          ((1UL << 15) | (1UL << 10))\r
+#define TT_DESCRIPTOR_SECTION_AP_RO_RO                          ((1UL << 15) | (3UL << 10))\r
+\r
+#define TT_DESCRIPTOR_CACHE_POLICY_NON_CACHEABLE                (0UL)\r
+#define TT_DESCRIPTOR_CACHE_POLICY_WRITE_BACK_ALLOCATE          (1UL)\r
+#define TT_DESCRIPTOR_CACHE_POLICY_WRITE_THROUGH_NO_ALLOCATE    (2UL)\r
+#define TT_DESCRIPTOR_CACHE_POLICY_WRITE_BACK_NO_ALLOCATE       (3UL)\r
+\r
+#define TT_DESCRIPTOR_OUTER_CACHE_POLICY_MASK                       ((1UL << 14) | (3UL << 12))\r
+#define TT_DESCRIPTOR_OUTER_CACHE_POLICY_NON_CACHEABLE              ((1UL << 14) | (TT_DESCRIPTOR_CACHE_POLICY_NON_CACHEABLE             << 12))\r
+#define TT_DESCRIPTOR_OUTER_CACHE_POLICY_WRITE_BACK_ALLOCATE        ((1UL << 14) | (TT_DESCRIPTOR_CACHE_POLICY_WRITE_BACK_ALLOCATE       << 12))\r
+#define TT_DESCRIPTOR_OUTER_CACHE_POLICY_WRITE_THROUGH_NO_ALLOCATE  ((1UL << 14) | (TT_DESCRIPTOR_CACHE_POLICY_WRITE_THROUGH_NO_ALLOCATE << 12))\r
+#define TT_DESCRIPTOR_OUTER_CACHE_POLICY_WRITE_BACK_NO_ALLOCATE     ((1UL << 14) | (TT_DESCRIPTOR_CACHE_POLICY_WRITE_BACK_NO_ALLOCATE    << 12))\r
+\r
+#define TT_DESCRIPTOR_INNER_CACHE_POLICY_MASK                       (3UL << 2)\r
+#define TT_DESCRIPTOR_INNER_CACHE_POLICY_NON_CACHEABLE              (TT_DESCRIPTOR_CACHE_POLICY_NON_CACHEABLE             << 2)\r
+#define TT_DESCRIPTOR_INNER_CACHE_POLICY_WRITE_BACK_ALLOCATE        (TT_DESCRIPTOR_CACHE_POLICY_WRITE_BACK_ALLOCATE       << 2)\r
+#define TT_DESCRIPTOR_INNER_CACHE_POLICY_WRITE_THROUGH_NO_ALLOCATE  (TT_DESCRIPTOR_CACHE_POLICY_WRITE_THROUGH_NO_ALLOCATE << 2)\r
+#define TT_DESCRIPTOR_INNER_CACHE_POLICY_WRITE_BACK_NO_ALLOCATE     (TT_DESCRIPTOR_CACHE_POLICY_WRITE_BACK_NO_ALLOCATE    << 2)\r
+\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK                   (TT_DESCRIPTOR_OUTER_CACHE_POLICY_MASK                      | TT_DESCRIPTOR_INNER_CACHE_POLICY_MASK)\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC (TT_DESCRIPTOR_OUTER_CACHE_POLICY_WRITE_THROUGH_NO_ALLOCATE | TT_DESCRIPTOR_INNER_CACHE_POLICY_WRITE_THROUGH_NO_ALLOCATE)\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC    (TT_DESCRIPTOR_OUTER_CACHE_POLICY_WRITE_BACK_NO_ALLOCATE    | TT_DESCRIPTOR_INNER_CACHE_POLICY_WRITE_BACK_NO_ALLOCATE)\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE          (TT_DESCRIPTOR_OUTER_CACHE_POLICY_NON_CACHEABLE             | TT_DESCRIPTOR_INNER_CACHE_POLICY_NON_CACHEABLE)\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC       (TT_DESCRIPTOR_OUTER_CACHE_POLICY_WRITE_BACK_ALLOCATE       | TT_DESCRIPTOR_INNER_CACHE_POLICY_WRITE_BACK_ALLOCATE)\r
+\r
+#define TT_DESCRIPTOR_SECTION_DOMAIN_MASK                       (0x0FUL << 5)\r
+#define TT_DESCRIPTOR_SECTION_DOMAIN(a)                         (((a) & 0x0FUL) << 5)\r
+\r
+#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK                 (0xFFF00000)\r
+#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a)                   (a & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)\r
+\r
+#define TT_DESCRIPTOR_SECTION_WRITE_BACK          (TT_DESCRIPTOR_TYPE_SECTION                              | \\r
+                                                   TT_DESCRIPTOR_SECTION_NS_NON_SECURE                         | \\r
+                                                   TT_DESCRIPTOR_SECTION_NG_GLOBAL                         | \\r
+                                                   TT_DESCRIPTOR_SECTION_S_NOT_SHARED                      | \\r
+                                                   TT_DESCRIPTOR_SECTION_DOMAIN(0)                         | \\r
+                                                   TT_DESCRIPTOR_SECTION_AP_RW_RW                          | \\r
+                                                   TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)\r
+#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH       (TT_DESCRIPTOR_TYPE_SECTION                              | \\r
+                                                   TT_DESCRIPTOR_SECTION_NS_NON_SECURE                         | \\r
+                                                   TT_DESCRIPTOR_SECTION_NG_GLOBAL                         | \\r
+                                                   TT_DESCRIPTOR_SECTION_S_NOT_SHARED                      | \\r
+                                                   TT_DESCRIPTOR_SECTION_DOMAIN(0)                         | \\r
+                                                   TT_DESCRIPTOR_SECTION_AP_RW_RW                          | \\r
+                                                   TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)\r
+#define TT_DESCRIPTOR_SECTION_UNCACHED            (TT_DESCRIPTOR_TYPE_SECTION                              | \\r
+                                                   TT_DESCRIPTOR_SECTION_NS_NON_SECURE                         | \\r
+                                                   TT_DESCRIPTOR_SECTION_NG_GLOBAL                         | \\r
+                                                   TT_DESCRIPTOR_SECTION_S_NOT_SHARED                      | \\r
+                                                   TT_DESCRIPTOR_SECTION_DOMAIN(0)                         | \\r
+                                                   TT_DESCRIPTOR_SECTION_AP_RW_RW                          | \\r
+                                                   TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)\r
+\r
+#endif // __ARM1176JZ_S_H__\r
diff --git a/edk2/ArmPkg/Include/Chipset/ARM926EJ-S.h b/edk2/ArmPkg/Include/Chipset/ARM926EJ-S.h
new file mode 100644 (file)
index 0000000..799d60c
--- /dev/null
@@ -0,0 +1,71 @@
+/** @file\r
+\r
+  Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>\r
+\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __ARM926EJ_S_H__\r
+#define __ARM926EJ_S_H__\r
+\r
+// Domain Access Control Register\r
+#define DOMAIN_ACCESS_CONTROL_MASK(a)     (3UL << (2 * (a)))\r
+#define DOMAIN_ACCESS_CONTROL_NONE(a)     (0UL << (2 * (a)))\r
+#define DOMAIN_ACCESS_CONTROL_CLIENT(a)   (1UL << (2 * (a)))\r
+#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))\r
+#define DOMAIN_ACCESS_CONTROL_MANAGER(a)  (3UL << (2 * (a)))\r
+\r
+#define TRANSLATION_TABLE_SIZE            (16 * 1024)\r
+#define TRANSLATION_TABLE_ALIGNMENT       (16 * 1024)\r
+#define TRANSLATION_TABLE_ALIGNMENT_MASK  (TRANSLATION_TABLE_ALIGNMENT - 1)\r
+\r
+#define TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(table, address) ((UINT32 *)(table) + (((UINTN)(address)) >> 20))\r
+\r
+// Translation table descriptor types\r
+#define TT_DESCRIPTOR_TYPE_MASK     (3UL << 0)\r
+#define TT_DESCRIPTOR_TYPE_FAULT    (0UL << 0)\r
+#define TT_DESCRIPTOR_TYPE_COARSE   ((1UL << 0) | (1UL << 4))\r
+#define TT_DESCRIPTOR_TYPE_SECTION  ((2UL << 0) | (1UL << 4))\r
+#define TT_DESCRIPTOR_TYPE_FINE     ((3UL << 0) | (1UL << 4))\r
+\r
+// Section descriptor definitions\r
+#define TT_DESCRIPTOR_SECTION_SIZE                              (0x00100000)\r
+\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK                 (3UL <<  2)\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_UNCACHED_UNBUFFERED  (0UL <<  2)\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_UNCACHED_BUFFERED    (1UL <<  2)\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH        (2UL <<  2)\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK           (3UL <<  2)\r
+\r
+#define TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_MASK            (3UL << 10)\r
+#define TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_NONE            (1UL << 10)\r
+#define TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_READ_ONLY       (2UL << 10)\r
+#define TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_READ_WRITE      (3UL << 10)\r
+\r
+#define TT_DESCRIPTOR_SECTION_DOMAIN_MASK                       (0x0FUL << 5)\r
+#define TT_DESCRIPTOR_SECTION_DOMAIN(a)                         (((a) & 0xF) << 5)\r
+\r
+#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK                 (0xFFF00000)\r
+#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a)                   (a & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)\r
+\r
+#define TT_DESCRIPTOR_SECTION_WRITE_BACK          (TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_READ_WRITE | \\r
+                                                   TT_DESCRIPTOR_SECTION_DOMAIN(0)                    | \\r
+                                                   TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK      | \\r
+                                                   TT_DESCRIPTOR_TYPE_SECTION)                                                   \r
+#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH       (TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_READ_WRITE | \\r
+                                                   TT_DESCRIPTOR_SECTION_DOMAIN(0)                    | \\r
+                                                   TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH   | \\r
+                                                   TT_DESCRIPTOR_TYPE_SECTION)\r
+#define TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED (TT_DESCRIPTOR_SECTION_ACCESS_PERMISSION_READ_WRITE     | \\r
+                                                   TT_DESCRIPTOR_SECTION_DOMAIN(0)                        | \\r
+                                                   TT_DESCRIPTOR_SECTION_CACHE_POLICY_UNCACHED_UNBUFFERED | \\r
+                                                   TT_DESCRIPTOR_TYPE_SECTION)\r
+\r
+#endif // __ARM926EJ_S_H__\r
diff --git a/edk2/ArmPkg/Include/Chipset/Cortex-A8.h b/edk2/ArmPkg/Include/Chipset/Cortex-A8.h
new file mode 100644 (file)
index 0000000..75ce397
--- /dev/null
@@ -0,0 +1,104 @@
+/** @file\r
+\r
+  Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>\r
+\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __CORTEX_A8_H__\r
+#define __CORTEX_A8_H__\r
+\r
+// Domain Access Control Register\r
+#define DOMAIN_ACCESS_CONTROL_MASK(a)     (3UL << (2 * (a)))\r
+#define DOMAIN_ACCESS_CONTROL_NONE(a)     (0UL << (2 * (a)))\r
+#define DOMAIN_ACCESS_CONTROL_CLIENT(a)   (1UL << (2 * (a)))\r
+#define DOMAIN_ACCESS_CONTROL_RESERVED(a) (2UL << (2 * (a)))\r
+#define DOMAIN_ACCESS_CONTROL_MANAGER(a)  (3UL << (2 * (a)))\r
+\r
+#define TRANSLATION_TABLE_SIZE            (16 * 1024)\r
+#define TRANSLATION_TABLE_ALIGNMENT       (16 * 1024)\r
+#define TRANSLATION_TABLE_ALIGNMENT_MASK  (TRANSLATION_TABLE_ALIGNMENT - 1)\r
+\r
+#define TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(table, address) ((UINT32 *)(table) + (((UINTN)(address)) >> 20))\r
+\r
+// Translation table descriptor types\r
+#define TT_DESCRIPTOR_TYPE_MASK         ((1UL << 18) | (3UL << 0))\r
+#define TT_DESCRIPTOR_TYPE_PAGE_TABLE   ((0UL << 18) | (1UL << 0))\r
+#define TT_DESCRIPTOR_TYPE_SECTION      ((0UL << 18) | (2UL << 0))\r
+#define TT_DESCRIPTOR_TYPE_SUPERSECTION ((1UL << 18) | (2UL << 0))\r
+\r
+// Section descriptor definitions\r
+#define TT_DESCRIPTOR_SECTION_SIZE                              (0x00100000)\r
+\r
+#define TT_DESCRIPTOR_SECTION_NS_MASK                           (1UL << 19)\r
+#define TT_DESCRIPTOR_SECTION_NS_SECURE                         (0UL << 19)\r
+#define TT_DESCRIPTOR_SECTION_NS_NON_SECURE                     (1UL << 19)\r
+\r
+#define TT_DESCRIPTOR_SECTION_NG_MASK                           (1UL << 17)\r
+#define TT_DESCRIPTOR_SECTION_NG_GLOBAL                         (0UL << 17)\r
+#define TT_DESCRIPTOR_SECTION_NG_LOCAL                          (1UL << 17)\r
+\r
+#define TT_DESCRIPTOR_SECTION_S_MASK                            (1UL << 16)\r
+#define TT_DESCRIPTOR_SECTION_S_NOT_SHARED                      (0UL << 16)\r
+#define TT_DESCRIPTOR_SECTION_S_SHARED                          (1UL << 16)\r
+\r
+#define TT_DESCRIPTOR_SECTION_AP_MASK                           ((1UL << 15) | (3UL << 10))\r
+#define TT_DESCRIPTOR_SECTION_AP_NO_NO                          ((0UL << 15) | (0UL << 10))\r
+#define TT_DESCRIPTOR_SECTION_AP_RW_NO                          ((0UL << 15) | (1UL << 10))\r
+#define TT_DESCRIPTOR_SECTION_AP_RW_RO                          ((0UL << 15) | (2UL << 10))\r
+#define TT_DESCRIPTOR_SECTION_AP_RW_RW                          ((0UL << 15) | (3UL << 10))\r
+#define TT_DESCRIPTOR_SECTION_AP_RO_NO                          ((1UL << 15) | (1UL << 10))\r
+#define TT_DESCRIPTOR_SECTION_AP_RO_RO                          ((1UL << 15) | (3UL << 10))\r
+\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_MASK                   ((3UL << 12) | (0UL << 3) | (0UL << 2))\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_STRONGLY_ORDERED       ((0UL << 12) | (0UL << 3) | (0UL << 2))\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE       ((0UL << 12) | (0UL << 3) | (1UL << 2))\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC ((0UL << 12) | (1UL << 3) | (0UL << 2))\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_NO_ALLOC    ((0UL << 12) | (1UL << 3) | (1UL << 2))\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE          ((1UL << 12) | (0UL << 3) | (0UL << 2))\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC       ((1UL << 12) | (1UL << 3) | (1UL << 2))\r
+#define TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_SHAREABLE_DEVICE   ((2UL << 12) | (0UL << 3) | (0UL << 2))\r
+\r
+#define TT_DESCRIPTOR_SECTION_DOMAIN_MASK                       (0x0FUL << 5)\r
+#define TT_DESCRIPTOR_SECTION_DOMAIN(a)                         (((a) & 0x0FUL) << 5)\r
+\r
+#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK                 (0xFFF00000)\r
+#define TT_DESCRIPTOR_SECTION_BASE_ADDRESS(a)                   (a & TT_DESCRIPTOR_SECTION_BASE_ADDRESS_MASK)\r
+\r
+#define TT_DESCRIPTOR_SECTION_WRITE_BACK          (TT_DESCRIPTOR_TYPE_SECTION                              | \\r
+                                                   TT_DESCRIPTOR_SECTION_NS_NON_SECURE                         | \\r
+                                                   TT_DESCRIPTOR_SECTION_NG_GLOBAL                         | \\r
+                                                   TT_DESCRIPTOR_SECTION_S_NOT_SHARED                      | \\r
+                                                   TT_DESCRIPTOR_SECTION_DOMAIN(0)                         | \\r
+                                                   TT_DESCRIPTOR_SECTION_AP_RW_RW                          | \\r
+                                                   TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_BACK_ALLOC)\r
+#define TT_DESCRIPTOR_SECTION_WRITE_THROUGH       (TT_DESCRIPTOR_TYPE_SECTION                              | \\r
+                                                   TT_DESCRIPTOR_SECTION_NS_NON_SECURE                     | \\r
+                                                   TT_DESCRIPTOR_SECTION_NG_GLOBAL                         | \\r
+                                                   TT_DESCRIPTOR_SECTION_S_NOT_SHARED                      | \\r
+                                                   TT_DESCRIPTOR_SECTION_DOMAIN(0)                         | \\r
+                                                   TT_DESCRIPTOR_SECTION_AP_RW_RW                          | \\r
+                                                   TT_DESCRIPTOR_SECTION_CACHE_POLICY_WRITE_THROUGH_NO_ALLOC)\r
+#define TT_DESCRIPTOR_SECTION_DEVICE              (TT_DESCRIPTOR_TYPE_SECTION                              | \\r
+                                                   TT_DESCRIPTOR_SECTION_NS_NON_SECURE                         | \\r
+                                                   TT_DESCRIPTOR_SECTION_NG_GLOBAL                         | \\r
+                                                   TT_DESCRIPTOR_SECTION_S_NOT_SHARED                      | \\r
+                                                   TT_DESCRIPTOR_SECTION_DOMAIN(0)                         | \\r
+                                                   TT_DESCRIPTOR_SECTION_AP_RW_RW                          | \\r
+                                                   TT_DESCRIPTOR_SECTION_CACHE_POLICY_SHAREABLE_DEVICE)\r
+#define TT_DESCRIPTOR_SECTION_UNCACHED            (TT_DESCRIPTOR_TYPE_SECTION                              | \\r
+                                                   TT_DESCRIPTOR_SECTION_NS_NON_SECURE                         | \\r
+                                                   TT_DESCRIPTOR_SECTION_NG_GLOBAL                         | \\r
+                                                   TT_DESCRIPTOR_SECTION_S_NOT_SHARED                      | \\r
+                                                   TT_DESCRIPTOR_SECTION_DOMAIN(0)                         | \\r
+                                                   TT_DESCRIPTOR_SECTION_AP_RW_RW                          | \\r
+                                                   TT_DESCRIPTOR_SECTION_CACHE_POLICY_NON_CACHEABLE)\r
+\r
+#endif // __CORTEX_A8_H__\r
diff --git a/edk2/ArmPkg/Include/Library/ArmLib.h b/edk2/ArmPkg/Include/Library/ArmLib.h
new file mode 100644 (file)
index 0000000..d68b334
--- /dev/null
@@ -0,0 +1,294 @@
+/** @file
+
+  Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
+
+  All rights reserved. This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __ARM_LIB__
+#define __ARM_LIB__
+
+typedef enum {
+  ARM_CACHE_TYPE_WRITE_BACK,
+  ARM_CACHE_TYPE_UNKNOWN
+} ARM_CACHE_TYPE;
+
+typedef enum {
+  ARM_CACHE_ARCHITECTURE_UNIFIED,
+  ARM_CACHE_ARCHITECTURE_SEPARATE,
+  ARM_CACHE_ARCHITECTURE_UNKNOWN
+} ARM_CACHE_ARCHITECTURE;
+
+typedef struct {
+  ARM_CACHE_TYPE          Type;
+  ARM_CACHE_ARCHITECTURE  Architecture;
+  BOOLEAN                 DataCachePresent;
+  UINTN                   DataCacheSize;
+  UINTN                   DataCacheAssociativity;
+  UINTN                   DataCacheLineLength;
+  BOOLEAN                 InstructionCachePresent;
+  UINTN                   InstructionCacheSize;
+  UINTN                   InstructionCacheAssociativity;
+  UINTN                   InstructionCacheLineLength;
+} ARM_CACHE_INFO;
+
+typedef enum {
+  ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED,
+  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK,
+  ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH,
+  ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
+} ARM_MEMORY_REGION_ATTRIBUTES;
+
+typedef struct {
+  UINT32                        PhysicalBase;
+  UINT32                        VirtualBase;
+  UINT32                        Length;
+  ARM_MEMORY_REGION_ATTRIBUTES  Attributes;
+} ARM_MEMORY_REGION_DESCRIPTOR;
+
+typedef VOID (*CACHE_OPERATION)(VOID);
+typedef VOID (*LINE_OPERATION)(UINTN);
+
+typedef enum {
+  ARM_PROCESSOR_MODE_USER       = 0x10,
+  ARM_PROCESSOR_MODE_FIQ        = 0x11,
+  ARM_PROCESSOR_MODE_IRQ        = 0x12,
+  ARM_PROCESSOR_MODE_SUPERVISOR = 0x13,
+  ARM_PROCESSOR_MODE_ABORT      = 0x17,
+  ARM_PROCESSOR_MODE_UNDEFINED  = 0x1B,
+  ARM_PROCESSOR_MODE_SYSTEM     = 0x1F,
+  ARM_PROCESSOR_MODE_MASK       = 0x1F
+} ARM_PROCESSOR_MODE;
+
+ARM_CACHE_TYPE
+EFIAPI
+ArmCacheType (
+  VOID
+  );
+
+ARM_CACHE_ARCHITECTURE
+EFIAPI
+ArmCacheArchitecture (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmCacheInformation (
+  OUT ARM_CACHE_INFO  *CacheInfo
+  );
+
+BOOLEAN
+EFIAPI
+ArmDataCachePresent (
+  VOID
+  );
+  
+UINTN
+EFIAPI
+ArmDataCacheSize (
+  VOID
+  );
+  
+UINTN
+EFIAPI
+ArmDataCacheAssociativity (
+  VOID
+  );
+  
+UINTN
+EFIAPI
+ArmDataCacheLineLength (
+  VOID
+  );
+  
+BOOLEAN
+EFIAPI
+ArmInstructionCachePresent (
+  VOID
+  );
+  
+UINTN
+EFIAPI
+ArmInstructionCacheSize (
+  VOID
+  );
+  
+UINTN
+EFIAPI
+ArmInstructionCacheAssociativity (
+  VOID
+  );
+  
+UINTN
+EFIAPI
+ArmInstructionCacheLineLength (
+  VOID
+  );
+  
+UINT32
+EFIAPI
+Cp15IdCode (
+  VOID
+  );
+  
+UINT32
+EFIAPI
+Cp15CacheInfo (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmInvalidateDataCache (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmCleanInvalidateDataCache (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmCleanDataCache (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmInvalidateInstructionCache (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmInvalidateDataCacheEntryByMVA (
+  IN  UINTN   Address
+  );
+
+VOID
+EFIAPI
+ArmCleanDataCacheEntryByMVA (
+  IN  UINTN   Address
+  );
+
+VOID
+EFIAPI
+ArmCleanInvalidateDataCacheEntryByMVA (
+  IN  UINTN   Address
+  );
+
+VOID
+EFIAPI
+ArmEnableDataCache (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmDisableDataCache (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmEnableInstructionCache (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmDisableInstructionCache (
+  VOID
+  );
+  
+VOID
+EFIAPI
+ArmEnableMmu (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmDisableMmu (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmEnableInterrupts (
+  VOID
+  );
+
+UINTN
+EFIAPI
+ArmDisableInterrupts (
+  VOID
+  );
+  
+BOOLEAN
+EFIAPI
+ArmGetInterruptState (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmInvalidateTlb (
+  VOID
+  );
+  
+VOID
+EFIAPI
+ArmSetDomainAccessControl (
+  IN  UINT32  Domain
+  );
+
+VOID
+EFIAPI
+ArmSetTranslationTableBaseAddress (
+  IN  VOID  *TranslationTableBase
+  );
+
+VOID
+EFIAPI
+ArmConfigureMmu (
+  IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
+  OUT VOID                          **TranslationTableBase OPTIONAL,
+  OUT UINTN                         *TranslationTableSize  OPTIONAL
+  );
+  
+VOID
+EFIAPI
+ArmSwitchProcessorMode (
+  IN ARM_PROCESSOR_MODE Mode
+  );
+
+ARM_PROCESSOR_MODE
+EFIAPI
+ArmProcessorMode (
+  VOID
+  );
+  
+VOID
+EFIAPI
+ArmEnableBranchPrediction (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmDisableBranchPrediction (
+  VOID
+  );
+
+#endif // __ARM_LIB__
diff --git a/edk2/ArmPkg/Include/Library/SemihostLib.h b/edk2/ArmPkg/Include/Library/SemihostLib.h
new file mode 100644 (file)
index 0000000..2c8b6ac
--- /dev/null
@@ -0,0 +1,100 @@
+/** @file
+
+  Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
+
+  All rights reserved. This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __SEMIHOSTING_H__
+#define __SEMIHOSTING_H__
+
+/*
+ *
+ *  Please refer to ARM RVDS 3.0 Compiler and Libraries Guide for more information
+ *  about the semihosting interface.
+ *
+ */
+#define SEMIHOST_FILE_MODE_READ     (0 << 2)
+#define SEMIHOST_FILE_MODE_WRITE    (1 << 2)
+#define SEMIHOST_FILE_MODE_APPEND   (2 << 2)
+#define SEMIHOST_FILE_MODE_CREATE   (1 << 1)
+#define SEMIHOST_FILE_MODE_BINARY   (1 << 0)
+#define SEMIHOST_FILE_MODE_ASCII    (0 << 0)
+
+BOOLEAN
+SemihostConnectionSupported (
+  VOID
+  );
+
+EFI_STATUS
+SemihostFileOpen (
+  IN  CHAR8  *FileName,
+  IN  UINT32 Mode,
+  OUT UINT32 *FileHandle
+  );
+
+EFI_STATUS
+SemihostFileSeek (
+  IN UINT32 FileHandle,
+  IN UINT32 Offset
+  );
+
+EFI_STATUS
+SemihostFileRead (
+  IN     UINT32 FileHandle,
+  IN OUT UINT32 *Length,
+  OUT    VOID   *Buffer
+  );
+
+EFI_STATUS
+SemihostFileWrite (
+  IN     UINT32 FileHandle,
+  IN OUT UINT32 *Length,
+  IN     VOID   *Buffer
+  );
+
+EFI_STATUS
+SemihostFileClose (
+  IN UINT32 FileHandle
+  );
+
+EFI_STATUS
+SemihostFileLength (
+  IN  UINT32 FileHandle,
+  OUT UINT32 *Length
+  );
+
+EFI_STATUS
+SemihostFileRemove (
+  IN CHAR8 *FileName
+  );
+
+CHAR8
+SemihostReadCharacter (
+  VOID
+  );
+
+VOID
+SemihostWriteCharacter (
+  IN CHAR8 Character
+  );
+
+VOID
+SemihostWriteString (
+  IN CHAR8 *String
+  );
+  
+UINT32
+SemihostSystem (
+  IN CHAR8 *CommandLine
+  );
+  
+#endif // __SEMIHOSTING_H__
diff --git a/edk2/ArmPkg/Include/Library/UncachedMemoryAllocationLib.h b/edk2/ArmPkg/Include/Library/UncachedMemoryAllocationLib.h
new file mode 100644 (file)
index 0000000..8a65fcc
--- /dev/null
@@ -0,0 +1,665 @@
+/** @file
+
+  Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
+
+  All rights reserved. This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __UNCACHED_MEMORY_ALLOCATION_LIB_H__
+#define __UNCACHED_MEMORY_ALLOCATION_LIB_H__
+
+/**
+  Converts a cached or uncached address to a physical address suitable for use in SoC registers.
+
+  @param  VirtualAddress                 The pointer to convert.
+
+  @return The physical address of the supplied virtual pointer.
+
+**/
+EFI_PHYSICAL_ADDRESS
+ConvertToPhysicalAddress (
+  IN VOID *VirtualAddress
+  );
+
+/**
+  Converts a cached or uncached address to a cached address.
+
+  @param  Address                 The pointer to convert.
+
+  @return The address of the cached memory location corresponding to the input address.
+
+**/
+VOID *
+ConvertToCachedAddress (
+  IN VOID *Address
+  );
+
+/**
+  Converts a cached or uncached address to an uncached address.
+
+  @param  Address                 The pointer to convert.
+
+  @return The address of the uncached memory location corresponding to the input address.
+
+**/
+VOID *
+ConvertToUncachedAddress (
+  IN VOID *Address
+  );
+
+/**
+  Allocates one or more 4KB pages of type EfiBootServicesData.
+
+  Allocates the number of 4KB pages of type EfiBootServicesData and returns a pointer to the
+  allocated buffer.  The buffer returned is aligned on a 4KB boundary.  If Pages is 0, then NULL
+  is returned.  If there is not enough memory remaining to satisfy the request, then NULL is
+  returned.
+
+  @param  Pages                 The number of 4 KB pages to allocate.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocatePages (
+  IN UINTN  Pages
+  );
+
+/**
+  Allocates one or more 4KB pages of type EfiRuntimeServicesData.
+
+  Allocates the number of 4KB pages of type EfiRuntimeServicesData and returns a pointer to the
+  allocated buffer.  The buffer returned is aligned on a 4KB boundary.  If Pages is 0, then NULL
+  is returned.  If there is not enough memory remaining to satisfy the request, then NULL is
+  returned.
+
+  @param  Pages                 The number of 4 KB pages to allocate.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateRuntimePages (
+  IN UINTN  Pages
+  );
+
+/**
+  Allocates one or more 4KB pages of type EfiReservedMemoryType.
+
+  Allocates the number of 4KB pages of type EfiReservedMemoryType and returns a pointer to the
+  allocated buffer.  The buffer returned is aligned on a 4KB boundary.  If Pages is 0, then NULL
+  is returned.  If there is not enough memory remaining to satisfy the request, then NULL is
+  returned.
+
+  @param  Pages                 The number of 4 KB pages to allocate.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateReservedPages (
+  IN UINTN  Pages
+  );
+
+/**
+  Frees one or more 4KB pages that were previously allocated with one of the page allocation
+  functions in the Memory Allocation Library.
+
+  Frees the number of 4KB pages specified by Pages from the buffer specified by Buffer.  Buffer
+  must have been allocated on a previous call to the page allocation services of the Memory
+  Allocation Library.
+  If Buffer was not allocated with a page allocation function in the Memory Allocation Library,
+  then ASSERT().
+  If Pages is zero, then ASSERT().
+  @param  Buffer                Pointer to the buffer of pages to free.
+  @param  Pages                 The number of 4 KB pages to free.
+
+**/
+VOID
+EFIAPI
+UncachedFreePages (
+  IN VOID   *Buffer,
+  IN UINTN  Pages
+  );
+
+/**
+  Allocates one or more 4KB pages of type EfiBootServicesData at a specified alignment.
+
+  Allocates the number of 4KB pages specified by Pages of type EfiBootServicesData with an
+  alignment specified by Alignment.  The allocated buffer is returned.  If Pages is 0, then NULL is
+  returned.  If there is not enough memory at the specified alignment remaining to satisfy the
+  request, then NULL is returned.
+  If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+  @param  Pages                 The number of 4 KB pages to allocate.
+  @param  Alignment             The requested alignment of the allocation.  Must be a power of two.
+                                If Alignment is zero, then byte alignment is used.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedPages (
+  IN UINTN  Pages,
+  IN UINTN  Alignment
+  );
+
+/**
+  Allocates one or more 4KB pages of type EfiRuntimeServicesData at a specified alignment.
+
+  Allocates the number of 4KB pages specified by Pages of type EfiRuntimeServicesData with an
+  alignment specified by Alignment.  The allocated buffer is returned.  If Pages is 0, then NULL is
+  returned.  If there is not enough memory at the specified alignment remaining to satisfy the
+  request, then NULL is returned.
+  If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+  @param  Pages                 The number of 4 KB pages to allocate.
+  @param  Alignment             The requested alignment of the allocation.  Must be a power of two.
+                                If Alignment is zero, then byte alignment is used.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedRuntimePages (
+  IN UINTN  Pages,
+  IN UINTN  Alignment
+  );
+
+/**
+  Allocates one or more 4KB pages of type EfiReservedMemoryType at a specified alignment.
+
+  Allocates the number of 4KB pages specified by Pages of type EfiReservedMemoryType with an
+  alignment specified by Alignment.  The allocated buffer is returned.  If Pages is 0, then NULL is
+  returned.  If there is not enough memory at the specified alignment remaining to satisfy the
+  request, then NULL is returned.
+  If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+  @param  Pages                 The number of 4 KB pages to allocate.
+  @param  Alignment             The requested alignment of the allocation.  Must be a power of two.
+                                If Alignment is zero, then byte alignment is used.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedReservedPages (
+  IN UINTN  Pages,
+  IN UINTN  Alignment
+  );
+
+/**
+  Frees one or more 4KB pages that were previously allocated with one of the aligned page
+  allocation functions in the Memory Allocation Library.
+
+  Frees the number of 4KB pages specified by Pages from the buffer specified by Buffer.  Buffer
+  must have been allocated on a previous call to the aligned page allocation services of the Memory
+  Allocation Library.
+  If Buffer was not allocated with an aligned page allocation function in the Memory Allocation
+  Library, then ASSERT().
+  If Pages is zero, then ASSERT().
+  
+  @param  Buffer                Pointer to the buffer of pages to free.
+  @param  Pages                 The number of 4 KB pages to free.
+
+**/
+VOID
+EFIAPI
+UncachedFreeAlignedPages (
+  IN VOID   *Buffer,
+  IN UINTN  Pages
+  );
+
+/**
+  Allocates a buffer of type EfiBootServicesData.
+
+  Allocates the number bytes specified by AllocationSize of type EfiBootServicesData and returns a
+  pointer to the allocated buffer.  If AllocationSize is 0, then a valid buffer of 0 size is
+  returned.  If there is not enough memory remaining to satisfy the request, then NULL is returned.
+
+  @param  AllocationSize        The number of bytes to allocate.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocatePool (
+  IN UINTN  AllocationSize
+  );
+
+/**
+  Allocates a buffer of type EfiRuntimeServicesData.
+
+  Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData and returns
+  a pointer to the allocated buffer.  If AllocationSize is 0, then a valid buffer of 0 size is
+  returned.  If there is not enough memory remaining to satisfy the request, then NULL is returned.
+
+  @param  AllocationSize        The number of bytes to allocate.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateRuntimePool (
+  IN UINTN  AllocationSize
+  );
+
+/**
+  Allocates a buffer of type EfieservedMemoryType.
+
+  Allocates the number bytes specified by AllocationSize of type EfieservedMemoryType and returns
+  a pointer to the allocated buffer.  If AllocationSize is 0, then a valid buffer of 0 size is
+  returned.  If there is not enough memory remaining to satisfy the request, then NULL is returned.
+
+  @param  AllocationSize        The number of bytes to allocate.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateReservedPool (
+  IN UINTN  AllocationSize
+  );
+
+/**
+  Allocates and zeros a buffer of type EfiBootServicesData.
+
+  Allocates the number bytes specified by AllocationSize of type EfiBootServicesData, clears the
+  buffer with zeros, and returns a pointer to the allocated buffer.  If AllocationSize is 0, then a
+  valid buffer of 0 size is returned.  If there is not enough memory remaining to satisfy the
+  request, then NULL is returned.
+
+  @param  AllocationSize        The number of bytes to allocate and zero.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateZeroPool (
+  IN UINTN  AllocationSize
+  );
+
+/**
+  Allocates and zeros a buffer of type EfiRuntimeServicesData.
+
+  Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData, clears the
+  buffer with zeros, and returns a pointer to the allocated buffer.  If AllocationSize is 0, then a
+  valid buffer of 0 size is returned.  If there is not enough memory remaining to satisfy the
+  request, then NULL is returned.
+
+  @param  AllocationSize        The number of bytes to allocate and zero.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateRuntimeZeroPool (
+  IN UINTN  AllocationSize
+  );
+
+/**
+  Allocates and zeros a buffer of type EfiReservedMemoryType.
+
+  Allocates the number bytes specified by AllocationSize of type EfiReservedMemoryType, clears the
+  buffer with zeros, and returns a pointer to the allocated buffer.  If AllocationSize is 0, then a
+  valid buffer of 0 size is returned.  If there is not enough memory remaining to satisfy the
+  request, then NULL is returned.
+
+  @param  AllocationSize        The number of bytes to allocate and zero.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateReservedZeroPool (
+  IN UINTN  AllocationSize
+  );
+
+/**
+  Copies a buffer to an allocated buffer of type EfiBootServicesData.
+
+  Allocates the number bytes specified by AllocationSize of type EfiBootServicesData, copies
+  AllocationSize bytes from Buffer to the newly allocated buffer, and returns a pointer to the
+  allocated buffer.  If AllocationSize is 0, then a valid buffer of 0 size is returned.  If there
+  is not enough memory remaining to satisfy the request, then NULL is returned.
+  If Buffer is NULL, then ASSERT().
+  If AllocationSize is greater than (MAX_ADDRESS ? Buffer + 1), then ASSERT(). 
+
+  @param  AllocationSize        The number of bytes to allocate and zero.
+  @param  Buffer                The buffer to copy to the allocated buffer.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateCopyPool (
+  IN UINTN       AllocationSize,
+  IN CONST VOID  *Buffer
+  );
+
+/**
+  Copies a buffer to an allocated buffer of type EfiRuntimeServicesData.
+
+  Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData, copies
+  AllocationSize bytes from Buffer to the newly allocated buffer, and returns a pointer to the
+  allocated buffer.  If AllocationSize is 0, then a valid buffer of 0 size is returned.  If there
+  is not enough memory remaining to satisfy the request, then NULL is returned.
+  If Buffer is NULL, then ASSERT().
+  If AllocationSize is greater than (MAX_ADDRESS ? Buffer + 1), then ASSERT(). 
+
+  @param  AllocationSize        The number of bytes to allocate and zero.
+  @param  Buffer                The buffer to copy to the allocated buffer.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateRuntimeCopyPool (
+  IN UINTN       AllocationSize,
+  IN CONST VOID  *Buffer
+  );
+
+/**
+  Copies a buffer to an allocated buffer of type EfiReservedMemoryType.
+
+  Allocates the number bytes specified by AllocationSize of type EfiReservedMemoryType, copies
+  AllocationSize bytes from Buffer to the newly allocated buffer, and returns a pointer to the
+  allocated buffer.  If AllocationSize is 0, then a valid buffer of 0 size is returned.  If there
+  is not enough memory remaining to satisfy the request, then NULL is returned.
+  If Buffer is NULL, then ASSERT().
+  If AllocationSize is greater than (MAX_ADDRESS ? Buffer + 1), then ASSERT(). 
+
+  @param  AllocationSize        The number of bytes to allocate and zero.
+  @param  Buffer                The buffer to copy to the allocated buffer.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateReservedCopyPool (
+  IN UINTN       AllocationSize,
+  IN CONST VOID  *Buffer
+  );
+
+/**
+  Frees a buffer that was previously allocated with one of the pool allocation functions in the
+  Memory Allocation Library.
+
+  Frees the buffer specified by Buffer.  Buffer must have been allocated on a previous call to the
+  pool allocation services of the Memory Allocation Library.
+  If Buffer was not allocated with a pool allocation function in the Memory Allocation Library,
+  then ASSERT().
+
+  @param  Buffer                Pointer to the buffer to free.
+
+**/
+VOID
+EFIAPI
+UncachedFreePool (
+  IN VOID   *Buffer
+  );
+
+/**
+  Allocates a buffer of type EfiBootServicesData at a specified alignment.
+
+  Allocates the number bytes specified by AllocationSize of type EfiBootServicesData with an
+  alignment specified by Alignment.  The allocated buffer is returned.  If AllocationSize is 0,
+  then a valid buffer of 0 size is returned.  If there is not enough memory at the specified
+  alignment remaining to satisfy the request, then NULL is returned.
+  If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+  @param  AllocationSize        The number of bytes to allocate.
+  @param  Alignment             The requested alignment of the allocation.  Must be a power of two.
+                                If Alignment is zero, then byte alignment is used.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedPool (
+  IN UINTN  AllocationSize,
+  IN UINTN  Alignment
+  );
+
+/**
+  Allocates a buffer of type EfiRuntimeServicesData at a specified alignment.
+
+  Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData with an
+  alignment specified by Alignment.  The allocated buffer is returned.  If AllocationSize is 0,
+  then a valid buffer of 0 size is returned.  If there is not enough memory at the specified
+  alignment remaining to satisfy the request, then NULL is returned.
+  If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+  @param  AllocationSize        The number of bytes to allocate.
+  @param  Alignment             The requested alignment of the allocation.  Must be a power of two.
+                                If Alignment is zero, then byte alignment is used.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedRuntimePool (
+  IN UINTN  AllocationSize,
+  IN UINTN  Alignment
+  );
+
+/**
+  Allocates a buffer of type EfieservedMemoryType at a specified alignment.
+
+  Allocates the number bytes specified by AllocationSize of type EfieservedMemoryType with an
+  alignment specified by Alignment.  The allocated buffer is returned.  If AllocationSize is 0,
+  then a valid buffer of 0 size is returned.  If there is not enough memory at the specified
+  alignment remaining to satisfy the request, then NULL is returned.
+  If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+  @param  AllocationSize        The number of bytes to allocate.
+  @param  Alignment             The requested alignment of the allocation.  Must be a power of two.
+                                If Alignment is zero, then byte alignment is used.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedReservedPool (
+  IN UINTN  AllocationSize,
+  IN UINTN  Alignment
+  );
+
+/**
+  Allocates and zeros a buffer of type EfiBootServicesData at a specified alignment.
+
+  Allocates the number bytes specified by AllocationSize of type EfiBootServicesData with an
+  alignment specified by Alignment, clears the buffer with zeros, and returns a pointer to the
+  allocated buffer.  If AllocationSize is 0, then a valid buffer of 0 size is returned.  If there
+  is not enough memory at the specified alignment remaining to satisfy the request, then NULL is
+  returned.
+  If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+  @param  AllocationSize        The number of bytes to allocate.
+  @param  Alignment             The requested alignment of the allocation.  Must be a power of two.
+                                If Alignment is zero, then byte alignment is used.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedZeroPool (
+  IN UINTN  AllocationSize,
+  IN UINTN  Alignment
+  );
+
+/**
+  Allocates and zeros a buffer of type EfiRuntimeServicesData at a specified alignment.
+
+  Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData with an
+  alignment specified by Alignment, clears the buffer with zeros, and returns a pointer to the
+  allocated buffer.  If AllocationSize is 0, then a valid buffer of 0 size is returned.  If there
+  is not enough memory at the specified alignment remaining to satisfy the request, then NULL is
+  returned.
+  If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+  @param  AllocationSize        The number of bytes to allocate.
+  @param  Alignment             The requested alignment of the allocation.  Must be a power of two.
+                                If Alignment is zero, then byte alignment is used.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedRuntimeZeroPool (
+  IN UINTN  AllocationSize,
+  IN UINTN  Alignment
+  );
+
+/**
+  Allocates and zeros a buffer of type EfieservedMemoryType at a specified alignment.
+
+  Allocates the number bytes specified by AllocationSize of type EfieservedMemoryType with an
+  alignment specified by Alignment, clears the buffer with zeros, and returns a pointer to the
+  allocated buffer.  If AllocationSize is 0, then a valid buffer of 0 size is returned.  If there
+  is not enough memory at the specified alignment remaining to satisfy the request, then NULL is
+  returned.
+  If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+  @param  AllocationSize        The number of bytes to allocate.
+  @param  Alignment             The requested alignment of the allocation.  Must be a power of two.
+                                If Alignment is zero, then byte alignment is used.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedReservedZeroPool (
+  IN UINTN  AllocationSize,
+  IN UINTN  Alignment
+  );
+
+/**
+  Copies a buffer to an allocated buffer of type EfiBootServicesData at a specified alignment.
+
+  Allocates the number bytes specified by AllocationSize of type EfiBootServicesData type with an
+  alignment specified by Alignment.  The allocated buffer is returned.  If AllocationSize is 0,
+  then a valid buffer of 0 size is returned.  If there is not enough memory at the specified
+  alignment remaining to satisfy the request, then NULL is returned.
+  If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+  @param  AllocationSize        The number of bytes to allocate.
+  @param  Buffer                The buffer to copy to the allocated buffer.
+  @param  Alignment             The requested alignment of the allocation.  Must be a power of two.
+                                If Alignment is zero, then byte alignment is used.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedCopyPool (
+  IN UINTN       AllocationSize,
+  IN CONST VOID  *Buffer,
+  IN UINTN       Alignment
+  );
+
+/**
+  Copies a buffer to an allocated buffer of type EfiRuntimeServicesData at a specified alignment.
+
+  Allocates the number bytes specified by AllocationSize of type EfiRuntimeServicesData type with an
+  alignment specified by Alignment.  The allocated buffer is returned.  If AllocationSize is 0,
+  then a valid buffer of 0 size is returned.  If there is not enough memory at the specified
+  alignment remaining to satisfy the request, then NULL is returned.
+  If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+  @param  AllocationSize        The number of bytes to allocate.
+  @param  Buffer                The buffer to copy to the allocated buffer.
+  @param  Alignment             The requested alignment of the allocation.  Must be a power of two.
+                                If Alignment is zero, then byte alignment is used.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedRuntimeCopyPool (
+  IN UINTN       AllocationSize,
+  IN CONST VOID  *Buffer,
+  IN UINTN       Alignment
+  );
+
+/**
+  Copies a buffer to an allocated buffer of type EfiReservedMemoryType at a specified alignment.
+
+  Allocates the number bytes specified by AllocationSize of type EfiReservedMemoryType type with an
+  alignment specified by Alignment.  The allocated buffer is returned.  If AllocationSize is 0,
+  then a valid buffer of 0 size is returned.  If there is not enough memory at the specified
+  alignment remaining to satisfy the request, then NULL is returned.
+  If Alignment is not a power of two and Alignment is not zero, then ASSERT().
+
+  @param  AllocationSize        The number of bytes to allocate.
+  @param  Buffer                The buffer to copy to the allocated buffer.
+  @param  Alignment             The requested alignment of the allocation.  Must be a power of two.
+                                If Alignment is zero, then byte alignment is used.
+
+  @return A pointer to the allocated buffer or NULL if allocation fails.
+
+**/
+VOID *
+EFIAPI
+UncachedAllocateAlignedReservedCopyPool (
+  IN UINTN       AllocationSize,
+  IN CONST VOID  *Buffer,
+  IN UINTN       Alignment
+  );
+
+/**
+  Frees a buffer that was previously allocated with one of the aligned pool allocation functions 
+  in the Memory Allocation Library.
+
+  Frees the buffer specified by Buffer.  Buffer must have been allocated on a previous call to the
+  aligned pool allocation services of the Memory Allocation Library.
+  If Buffer was not allocated with an aligned pool allocation function in the Memory Allocation
+  Library, then ASSERT().
+
+  @param  Buffer                Pointer to the buffer to free.
+
+**/
+VOID
+EFIAPI
+UncachedFreeAlignedPool (
+  IN VOID   *Buffer
+  );
+
+VOID
+EFIAPI
+UncachedSafeFreePool (
+  IN VOID   *Buffer
+  );
+
+#endif // __UNCACHED_MEMORY_ALLOCATION_LIB_H__
diff --git a/edk2/ArmPkg/Include/Protocol/TimerDebugSupport.h b/edk2/ArmPkg/Include/Protocol/TimerDebugSupport.h
new file mode 100644 (file)
index 0000000..8ed9254
--- /dev/null
@@ -0,0 +1,59 @@
+/** @file\r
+\r
+  Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>\r
+\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __TIMERDEBUGSUPPORTPROTOCOL_H__\r
+#define __TIMERDEBUGSUPPORTPROTOCOL_H__\r
+\r
+//\r
+// Protocol GUID\r
+//\r
+#define TIMER_DEBUG_PROTOCOL_GUID { 0x68300561, 0x0197, 0x465d, { 0xb5, 0xa1, 0x28, 0xeb, 0xa1, 0x98, 0xdd, 0x0b } }\r
+\r
+\r
+\r
+//\r
+// Protocol interface structure\r
+//\r
+typedef struct _TIMER_DEBUG_SUPPORT_PROTOCOL  TIMER_DEBUG_SUPPORT_PROTOCOL;\r
+\r
+\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *TIMER_DEBUG_SUPPORT_REGISTER_PERIODIC_CALLBACK) (\r
+  IN  TIMER_DEBUG_SUPPORT_PROTOCOL  *This,\r
+  IN  EFI_PERIODIC_CALLBACK         PeriodicCallback\r
+  )\r
+/*++\r
+\r
+Routine Description:\r
+  Register a periodic callback for debug support.\r
+\r
+Arguments:\r
+  This              - pointer to protocol\r
+  PeriodicCallback  - callback to be registered\r
+  \r
+Returns:\r
+  EFI_SUCCESS - callback registered\r
+\r
+--*/\r
+;\r
+\r
+struct _TIMER_DEBUG_SUPPORT_PROTOCOL {\r
+  TIMER_DEBUG_SUPPORT_REGISTER_PERIODIC_CALLBACK  RegisterPeriodicCallback;\r
+};\r
+\r
+extern EFI_GUID gTimerDebugSupportProtocolGuid;\r
+\r
+#endif // __TIMERDEBUGSUPPORTPROTOCOL_H__\r
+\r
diff --git a/edk2/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c b/edk2/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
new file mode 100644 (file)
index 0000000..7da6b42
--- /dev/null
@@ -0,0 +1,129 @@
+/** @file
+
+  Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+  
+  All rights reserved. This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+#include <Base.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+
+VOID
+CacheRangeOperation (
+  IN  VOID            *Start,
+  IN  UINTN           Length,
+  IN  CACHE_OPERATION CacheOperation,
+  IN  LINE_OPERATION  LineOperation
+  )
+{
+  UINTN ArmCacheLineLength         = ArmDataCacheLineLength();
+  UINTN ArmCacheLineAlignmentMask  = ArmCacheLineLength - 1;
+  UINTN ArmCacheOperationThreshold = PcdGet32(PcdArmCacheOperationThreshold);
+  
+  if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold))
+  {
+    CacheOperation();
+  }
+  else
+  {
+    // Align address (rounding down)
+    UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
+    UINTN EndAddress     = (UINTN)Start + Length;
+
+    // Perform the line operation on an address in each cache line
+    while (AlignedAddress < EndAddress)
+    {
+      LineOperation(AlignedAddress);
+      AlignedAddress += ArmCacheLineLength;
+    }
+  }
+}
+
+VOID
+EFIAPI
+InvalidateInstructionCache (
+  VOID
+  )
+{
+  ArmCleanDataCache();
+  ArmInvalidateInstructionCache();
+}
+
+VOID
+EFIAPI
+InvalidateDataCache (
+  VOID
+  )
+{
+  ArmInvalidateDataCache();
+}
+
+VOID *
+EFIAPI
+InvalidateInstructionCacheRange (
+  IN      VOID                      *Address,
+  IN      UINTN                     Length
+  )
+{
+  CacheRangeOperation(Address, Length, ArmCleanDataCache, ArmCleanDataCacheEntryByMVA);
+  ArmInvalidateInstructionCache();
+  return Address;
+}
+
+VOID
+EFIAPI
+WriteBackInvalidateDataCache (
+  VOID
+  )
+{
+  ArmCleanInvalidateDataCache();
+}
+
+VOID *
+EFIAPI
+WriteBackInvalidateDataCacheRange (
+  IN      VOID                      *Address,
+  IN      UINTN                     Length
+  )
+{
+  CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCache, ArmCleanInvalidateDataCacheEntryByMVA);
+  return Address;
+}
+
+VOID
+EFIAPI
+WriteBackDataCache (
+  VOID
+  )
+{
+  ArmCleanDataCache();
+}
+
+VOID *
+EFIAPI
+WriteBackDataCacheRange (
+  IN      VOID                      *Address,
+  IN      UINTN                     Length
+  )
+{
+  CacheRangeOperation(Address, Length, ArmCleanDataCache, ArmCleanDataCacheEntryByMVA);
+  return Address;
+}
+
+VOID *
+EFIAPI
+InvalidateDataCacheRange (
+  IN      VOID                      *Address,
+  IN      UINTN                     Length
+  )
+{
+  CacheRangeOperation(Address, Length, NULL, ArmInvalidateDataCacheEntryByMVA);
+  return Address;
+}
diff --git a/edk2/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf b/edk2/ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
new file mode 100644 (file)
index 0000000..93b88f4
--- /dev/null
@@ -0,0 +1,23 @@
+#%HEADER%
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = ArmCacheMaintenanceLib
+  FILE_GUID                      = 1A20BE1F-33AD-450C-B49A-7123FCA8B7F9
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = CacheMaintenanceLib 
+
+[Sources.common]
+  ArmCacheMaintenanceLib.c
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdePkg/MdePkg.dec
+
+[LibraryClasses]
+  ArmLib
+  BaseLib
+
+[FixedPcd]
+  gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
+  
diff --git a/edk2/ArmPkg/Library/ArmLib/Arm11/Arm11ArmLib.inf b/edk2/ArmPkg/Library/ArmLib/Arm11/Arm11ArmLib.inf
new file mode 100644 (file)
index 0000000..8042e4d
--- /dev/null
@@ -0,0 +1,32 @@
+#%HEADER%\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = Arm11ArmLib\r
+  FILE_GUID                      = 00586300-0E06-4790-AC44-86C56ACBB942\r
+  MODULE_TYPE                    = DXE_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = ArmLib\r
+\r
+[Sources.common]\r
+  ../Common/ArmLibSupport.S    | GCC\r
+  ../Common/ArmLibSupport.asm  | RVCT\r
+  ../Common/ArmLib.c\r
+  \r
+  Arm11Support.S    | GCC\r
+  Arm11Support.asm  | RVCT\r
+  \r
+  Arm11Lib.c\r
+  ../Arm9/Arm9CacheInformation.c\r
+\r
+[Packages]\r
+  ArmPkg/ArmPkg.dec\r
+  MdePkg/MdePkg.dec\r
+\r
+[LibraryClasses]\r
+  MemoryAllocationLib\r
+  \r
+[Protocols]\r
+  gEfiCpuArchProtocolGuid\r
+\r
+[FixedPcd]\r
+  gArmTokenSpaceGuid.PcdArmCacheOperationThreshold\r
diff --git a/edk2/ArmPkg/Library/ArmLib/Arm11/Arm11ArmLibPrePi.inf b/edk2/ArmPkg/Library/ArmLib/Arm11/Arm11ArmLibPrePi.inf
new file mode 100644 (file)
index 0000000..040179e
--- /dev/null
@@ -0,0 +1,32 @@
+#%HEADER%\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = Arm11ArmLib\r
+  FILE_GUID                      = 8dfb4ea2-3901-44f9-ae54-ca3d50362d2f\r
+  MODULE_TYPE                    = DXE_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = ArmLib\r
+\r
+[Sources.common]\r
+  ../Common/ArmLibSupport.S    | GCC\r
+  ../Common/ArmLibSupport.asm  | RVCT\r
+  ../Common/ArmLib.c\r
+  \r
+  Arm11Support.S    | GCC\r
+  Arm11Support.asm  | RVCT\r
+  \r
+  Arm11Lib.c\r
+  ../Arm9/Arm9CacheInformation.c\r
+\r
+[Packages]\r
+  ArmPkg/ArmPkg.dec\r
+  MdePkg/MdePkg.dec\r
+\r
+[LibraryClasses]\r
+  PrePiLib\r
+  \r
+[Protocols]\r
+  gEfiCpuArchProtocolGuid\r
+\r
+[FixedPcd]\r
+  gArmTokenSpaceGuid.PcdArmCacheOperationThreshold\r
diff --git a/edk2/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c b/edk2/ArmPkg/Library/ArmLib/Arm11/Arm11Lib.c
new file mode 100644 (file)
index 0000000..3736904
--- /dev/null
@@ -0,0 +1,118 @@
+/** @file
+
+  Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+  
+  All rights reserved. This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Chipset/ARM1176JZ-S.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+VOID
+FillTranslationTable (
+  IN  UINT32                        *TranslationTable,
+  IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryRegion
+  )
+{
+  UINT32  *Entry;
+  UINTN   Sections;
+  UINTN   Index;
+  UINT32  Attributes;
+  UINT32  PhysicalBase = MemoryRegion->PhysicalBase;
+  
+  switch (MemoryRegion->Attributes) {
+    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
+      Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
+      break;
+    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
+      Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;
+      break;
+    case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
+    default:
+      Attributes = TT_DESCRIPTOR_SECTION_UNCACHED;
+      break;
+  }
+  
+  Entry    = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
+  Sections = ((( MemoryRegion->Length - 1 ) / TT_DESCRIPTOR_SECTION_SIZE ) + 1 );
+  
+  for (Index = 0; Index < Sections; Index++)
+  {
+    *Entry++     =  TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
+    PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
+  }
+}
+
+VOID
+EFIAPI
+ArmConfigureMmu (
+  IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
+  OUT VOID                          **TranslationTableBase OPTIONAL,
+  OUT UINTN                         *TranslationTableSize  OPTIONAL
+  )
+{
+  VOID  *TranslationTable;
+
+  // Allocate pages for translation table.
+  TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
+  TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
+
+  if (TranslationTableBase != NULL) {
+    *TranslationTableBase = TranslationTable;
+  }
+  
+  if (TranslationTableBase != NULL) {
+    *TranslationTableSize = TRANSLATION_TABLE_SIZE;
+  }
+
+  ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
+
+  ArmCleanInvalidateDataCache();
+  ArmInvalidateInstructionCache();
+  ArmInvalidateTlb();
+
+  ArmDisableDataCache();
+  ArmDisableInstructionCache();
+  ArmDisableMmu();
+
+  // Make sure nothing sneaked into the cache
+  ArmCleanInvalidateDataCache();
+  ArmInvalidateInstructionCache();
+
+  while (MemoryTable->Length != 0) {
+    FillTranslationTable(TranslationTable, MemoryTable);
+    MemoryTable++;
+  }
+
+  ArmSetTranslationTableBaseAddress(TranslationTable);
+    
+  ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
+                            DOMAIN_ACCESS_CONTROL_NONE(14) |
+                            DOMAIN_ACCESS_CONTROL_NONE(13) |
+                            DOMAIN_ACCESS_CONTROL_NONE(12) |
+                            DOMAIN_ACCESS_CONTROL_NONE(11) |
+                            DOMAIN_ACCESS_CONTROL_NONE(10) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 9) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 8) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 7) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 6) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 5) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 4) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 3) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 2) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 1) |
+                            DOMAIN_ACCESS_CONTROL_MANAGER(0));
+    
+  ArmEnableInstructionCache();
+  ArmEnableDataCache();
+  ArmEnableMmu();  
+}
diff --git a/edk2/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S b/edk2/ArmPkg/Library/ArmLib/Arm11/Arm11Support.S
new file mode 100644 (file)
index 0000000..eec8f20
--- /dev/null
@@ -0,0 +1,129 @@
+#------------------------------------------------------------------------------ 
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+.text
+.align 2
+.globl ASM_PFX(ArmCleanInvalidateDataCache)
+.globl ASM_PFX(ArmCleanDataCache)
+.globl ASM_PFX(ArmInvalidateDataCache)
+.globl ASM_PFX(ArmInvalidateInstructionCache)
+.globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
+.globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
+.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
+.globl ASM_PFX(ArmEnableMmu)
+.globl ASM_PFX(ArmDisableMmu)
+.globl ASM_PFX(ArmEnableDataCache)
+.globl ASM_PFX(ArmDisableDataCache)
+.globl ASM_PFX(ArmEnableInstructionCache)
+.globl ASM_PFX(ArmDisableInstructionCache)
+.globl ASM_PFX(ArmEnableBranchPrediction)
+.globl ASM_PFX(ArmDisableBranchPrediction)
+
+.set DC_ON, (0x1<<2)
+.set IC_ON, (0x1<<12)
+.set XP_ON, (0x1<<23)
+
+ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
+  mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line                                           
+  bx      lr
+
+
+ASM_PFX(ArmCleanDataCacheEntryByMVA):
+  mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line     
+  bx      lr
+
+
+ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
+  mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line
+  bx      lr
+
+
+ASM_PFX(ArmCleanDataCache):
+  mcr     p15, 0, r0, c7, c10, 0  @ clean entire data cache
+  bx      lr
+
+
+ASM_PFX(ArmCleanInvalidateDataCache):
+  mcr     p15, 0, r0, c7, c14, 0  @ clean and invalidate entire data cache
+  bx      lr
+
+
+ASM_PFX(ArmInvalidateDataCache):
+  mcr     p15, 0, r0, c7, c6, 0  @ invalidate entire data cache
+  bx      lr
+
+
+ASM_PFX(ArmInvalidateInstructionCache):
+  mcr     p15, 0, r0, c7, c5, 0  @invalidate entire instruction cache
+  mov     R0,#0
+  mcr     p15,0,R0,c7,c5,4       @Flush Prefetch buffer
+  bx      lr
+
+ASM_PFX(ArmEnableMmu):
+  mrc     p15,0,R0,c1,c0,0
+  orr     R0,R0,#1
+  mcr     p15,0,R0,c1,c0,0
+  bx      LR
+
+ASM_PFX(ArmDisableMmu):
+  mrc     p15,0,R0,c1,c0,0
+  bic     R0,R0,#1
+  mcr     p15,0,R0,c1,c0,0
+  mov     R0,#0
+  mcr     p15,0,R0,c7,c10,4     @Data synchronization barrier
+  mov     R0,#0
+  mcr     p15,0,R0,c7,c5,4      @Flush Prefetch buffer
+  bx      LR
+
+ASM_PFX(ArmEnableDataCache):
+  ldr     R1,=DC_ON
+  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
+  orr     R0,R0,R1              @Set C bit
+  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
+  bx      LR
+    
+ASM_PFX(ArmDisableDataCache):
+  ldr     R1,=DC_ON
+  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
+  bic     R0,R0,R1              @Clear C bit
+  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
+  bx      LR
+
+ASM_PFX(ArmEnableInstructionCache):
+  ldr     R1,=IC_ON
+  mrc     p15,0,R0,c1,c0,0     @Read control register configuration data
+  orr     R0,R0,R1             @Set I bit
+  mcr     p15,0,r0,c1,c0,0     @Write control register configuration data
+  bx      LR
+  
+ASM_PFX(ArmDisableInstructionCache):
+  ldr     R1,=IC_ON
+  mrc     p15,0,R0,c1,c0,0     @Read control register configuration data
+  bic     R0,R0,R1             @Clear I bit.
+  mcr     p15,0,r0,c1,c0,0     @Write control register configuration data
+  bx      LR
+
+ASM_PFX(ArmEnableBranchPrediction):
+  mrc     p15, 0, r0, c1, c0, 0
+  orr     r0, r0, #0x00000800
+  mcr     p15, 0, r0, c1, c0, 0
+  bx      LR
+
+ASM_PFX(ArmDisableBranchPrediction):
+  mrc     p15, 0, r0, c1, c0, 0
+  bic     r0, r0, #0x00000800
+  mcr     p15, 0, r0, c1, c0, 0
+  bx      LR
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/edk2/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm b/edk2/ArmPkg/Library/ArmLib/Arm11/Arm11Support.asm
new file mode 100644 (file)
index 0000000..e0be8f0
--- /dev/null
@@ -0,0 +1,133 @@
+//------------------------------------------------------------------------------ 
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+    EXPORT  ArmCleanInvalidateDataCache
+    EXPORT  ArmCleanDataCache
+    EXPORT  ArmInvalidateDataCache
+    EXPORT  ArmInvalidateInstructionCache
+    EXPORT  ArmInvalidateDataCacheEntryByMVA
+    EXPORT  ArmCleanDataCacheEntryByMVA
+    EXPORT  ArmCleanInvalidateDataCacheEntryByMVA
+    EXPORT  ArmEnableMmu
+    EXPORT  ArmDisableMmu
+    EXPORT  ArmEnableDataCache
+    EXPORT  ArmDisableDataCache
+    EXPORT  ArmEnableInstructionCache
+    EXPORT  ArmDisableInstructionCache
+    EXPORT  ArmEnableBranchPrediction
+    EXPORT  ArmDisableBranchPrediction
+
+
+DC_ON       EQU     ( 0x1:SHL:2 )
+IC_ON       EQU     ( 0x1:SHL:12 )
+XP_ON       EQU     ( 0x1:SHL:23 )
+
+
+    AREA    ArmCacheLib, CODE, READONLY
+    PRESERVE8
+
+
+ArmInvalidateDataCacheEntryByMVA
+  mcr     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line                                           
+  bx      lr
+
+
+ArmCleanDataCacheEntryByMVA
+  mcr     p15, 0, r0, c7, c10, 1  ; clean single data cache line     
+  bx      lr
+
+
+ArmCleanInvalidateDataCacheEntryByMVA
+  mcr     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
+  bx      lr
+
+
+ArmCleanDataCache
+  mcr     p15, 0, r0, c7, c10, 0  ; clean entire data cache
+  bx      lr
+
+
+ArmCleanInvalidateDataCache
+  mcr     p15, 0, r0, c7, c14, 0  ; clean and invalidate entire data cache
+  bx      lr
+
+
+ArmInvalidateDataCache
+  mcr     p15, 0, r0, c7, c6, 0  ; invalidate entire data cache
+  bx      lr
+
+
+ArmInvalidateInstructionCache
+  mcr     p15, 0, r0, c7, c5, 0  ;invalidate entire instruction cache
+  mov     R0,#0
+  mcr     p15,0,R0,c7,c5,4       ;Flush Prefetch buffer
+  bx      lr
+
+ArmEnableMmu
+  mrc     p15,0,R0,c1,c0,0
+  orr     R0,R0,#1
+  mcr     p15,0,R0,c1,c0,0
+  bx      LR
+
+ArmDisableMmu
+  mrc     p15,0,R0,c1,c0,0
+  bic     R0,R0,#1
+  mcr     p15,0,R0,c1,c0,0
+  mov     R0,#0
+  mcr     p15,0,R0,c7,c10,4     ;Data synchronization barrier
+  mov     R0,#0
+  mcr     p15,0,R0,c7,c5,4      ;Flush Prefetch buffer
+  bx      LR
+
+ArmEnableDataCache
+  LDR     R1,=DC_ON
+  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
+  ORR     R0,R0,R1              ;Set C bit
+  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
+  BX      LR
+    
+ArmDisableDataCache
+  LDR     R1,=DC_ON
+  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
+  BIC     R0,R0,R1              ;Clear C bit
+  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
+  BX      LR
+
+ArmEnableInstructionCache
+  LDR     R1,=IC_ON
+  MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
+  ORR     R0,R0,R1             ;Set I bit
+  MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
+  BX      LR
+  
+ArmDisableInstructionCache
+  LDR     R1,=IC_ON
+  MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
+  BIC     R0,R0,R1             ;Clear I bit.
+  MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
+  BX      LR
+
+ArmEnableBranchPrediction
+  mrc     p15, 0, r0, c1, c0, 0
+  orr     r0, r0, #0x00000800
+  mcr     p15, 0, r0, c1, c0, 0
+  bx      LR
+
+ArmDisableBranchPrediction
+  mrc     p15, 0, r0, c1, c0, 0
+  bic     r0, r0, #0x00000800
+  mcr     p15, 0, r0, c1, c0, 0
+  bx      LR
+
+    END
diff --git a/edk2/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf b/edk2/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf
new file mode 100644 (file)
index 0000000..9a94039
--- /dev/null
@@ -0,0 +1,32 @@
+#%HEADER%\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = Arm9ArmLib\r
+  FILE_GUID                      = 375D70D3-91E0-4374-A540-68BD959EB184\r
+  MODULE_TYPE                    = DXE_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = ArmLib\r
+\r
+[Sources.common]\r
+  ../Common/ArmLibSupport.S    | GCC\r
+  ../Common/ArmLibSupport.asm  | RVCT\r
+  ../Common/ArmLib.c\r
+\r
+  Arm9Support.S    | GCC\r
+  Arm9Support.asm  | RVCT\r
+  \r
+  Arm9Lib.c\r
+  Arm9CacheInformation.c\r
+\r
+[Packages]\r
+  ArmPkg/ArmPkg.dec\r
+  MdePkg/MdePkg.dec\r
+\r
+[LibraryClasses]\r
+  MemoryAllocationLib\r
+  \r
+[Protocols]\r
+  gEfiCpuArchProtocolGuid\r
+\r
+[FixedPcd]\r
+  gArmTokenSpaceGuid.PcdArmCacheOperationThreshold\r
diff --git a/edk2/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf b/edk2/ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf
new file mode 100755 (executable)
index 0000000..909ce27
--- /dev/null
@@ -0,0 +1,32 @@
+#%HEADER%\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = Arm9ArmLibPrePi\r
+  FILE_GUID                      = e9b6011f-ee15-4e59-ab8f-a819a081fa54\r
+  MODULE_TYPE                    = DXE_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = ArmLib\r
+\r
+[Sources.common]\r
+  ../Common/ArmLibSupport.S    | GCC\r
+  ../Common/ArmLibSupport.asm  | RVCT\r
+  ../Common/ArmLib.c\r
+\r
+  Arm9Support.S    | GCC\r
+  Arm9Support.asm  | RVCT\r
+  \r
+  Arm9Lib.c\r
+  Arm9CacheInformation.c\r
+\r
+[Packages]\r
+  ArmPkg/ArmPkg.dec\r
+  MdePkg/MdePkg.dec\r
+\r
+[LibraryClasses]\r
+  PrePiLib\r
+\r
+[Protocols]\r
+  gEfiCpuArchProtocolGuid\r
+\r
+[FixedPcd]\r
+  gArmTokenSpaceGuid.PcdArmCacheOperationThreshold\r
diff --git a/edk2/ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c b/edk2/ArmPkg/Library/ArmLib/Arm9/Arm9CacheInformation.c
new file mode 100644 (file)
index 0000000..a8207b9
--- /dev/null
@@ -0,0 +1,164 @@
+/** @file\r
+\r
+  Copyright (c) 2008-2009, Apple Inc. All rights reserved.\r
+  \r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Library/ArmLib.h>\r
+#include "ArmLibPrivate.h"\r
+\r
+ARM_CACHE_TYPE\r
+EFIAPI\r
+ArmCacheType (\r
+  VOID\r
+  )\r
+{\r
+  switch (CACHE_TYPE(Cp15CacheInfo()))\r
+  {\r
+    case CACHE_TYPE_WRITE_BACK: return ARM_CACHE_TYPE_WRITE_BACK;\r
+    default:                    return ARM_CACHE_TYPE_UNKNOWN;\r
+  }\r
+}\r
+\r
+ARM_CACHE_ARCHITECTURE\r
+EFIAPI\r
+ArmCacheArchitecture (\r
+  VOID\r
+  )\r
+{\r
+  switch (CACHE_ARCHITECTURE(Cp15CacheInfo()))\r
+  {\r
+    case CACHE_ARCHITECTURE_UNIFIED:  return ARM_CACHE_ARCHITECTURE_UNIFIED;\r
+    case CACHE_ARCHITECTURE_SEPARATE: return ARM_CACHE_ARCHITECTURE_SEPARATE;\r
+    default:                          return ARM_CACHE_ARCHITECTURE_UNKNOWN;\r
+  }\r
+}\r
+\r
+BOOLEAN\r
+EFIAPI\r
+ArmDataCachePresent (\r
+  VOID\r
+  )\r
+{\r
+  switch (DATA_CACHE_PRESENT(Cp15CacheInfo()))\r
+  {\r
+    case CACHE_PRESENT:     return TRUE;\r
+    case CACHE_NOT_PRESENT: return FALSE;\r
+    default:                return FALSE;\r
+  }\r
+}\r
+  \r
+UINTN\r
+EFIAPI\r
+ArmDataCacheSize (\r
+  VOID\r
+  )\r
+{\r
+  switch (DATA_CACHE_SIZE(Cp15CacheInfo()))\r
+  {\r
+    case CACHE_SIZE_4_KB:   return   4 * 1024;      \r
+    case CACHE_SIZE_8_KB:   return   8 * 1024;\r
+    case CACHE_SIZE_16_KB:  return  16 * 1024;      \r
+    case CACHE_SIZE_32_KB:  return  32 * 1024;\r
+    case CACHE_SIZE_64_KB:  return  64 * 1024;\r
+    case CACHE_SIZE_128_KB: return 128 * 1024;\r
+    default:                return   0;\r
+  }\r
+}\r
+  \r
+UINTN\r
+EFIAPI\r
+ArmDataCacheAssociativity (\r
+  VOID\r
+  )\r
+{\r
+  switch (DATA_CACHE_ASSOCIATIVITY(Cp15CacheInfo()))\r
+  {\r
+    case CACHE_ASSOCIATIVITY_4_WAY:   return 4;\r
+    case CACHE_ASSOCIATIVITY_DIRECT:  return 1;\r
+    default:                          return 0;\r
+  }\r
+}\r
+  \r
+UINTN\r
+EFIAPI\r
+ArmDataCacheLineLength (\r
+  VOID\r
+  )\r
+{\r
+  switch (DATA_CACHE_LINE_LENGTH(Cp15CacheInfo()))\r
+  {\r
+    case CACHE_LINE_LENGTH_32_BYTES: return 32;\r
+    default:                         return  0;\r
+  }\r
+}\r
+  \r
+BOOLEAN\r
+EFIAPI\r
+ArmInstructionCachePresent (\r
+  VOID\r
+  )\r
+{\r
+  switch (INSTRUCTION_CACHE_PRESENT(Cp15CacheInfo()))\r
+  {\r
+    case CACHE_PRESENT:     return TRUE;\r
+    case CACHE_NOT_PRESENT: return FALSE;\r
+    default:                return FALSE;\r
+  }\r
+}\r
+  \r
+UINTN\r
+EFIAPI\r
+ArmInstructionCacheSize (\r
+  VOID\r
+  )\r
+{\r
+  switch (INSTRUCTION_CACHE_SIZE(Cp15CacheInfo()))\r
+  {\r
+    case CACHE_SIZE_4_KB:   return   4 * 1024;      \r
+    case CACHE_SIZE_8_KB:   return   8 * 1024;\r
+    case CACHE_SIZE_16_KB:  return  16 * 1024;      \r
+    case CACHE_SIZE_32_KB:  return  32 * 1024;\r
+    case CACHE_SIZE_64_KB:  return  64 * 1024;\r
+    case CACHE_SIZE_128_KB: return 128 * 1024;\r
+    default:                return   0;\r
+  }\r
+}\r
+  \r
+UINTN\r
+EFIAPI\r
+ArmInstructionCacheAssociativity (\r
+  VOID\r
+  )\r
+{\r
+  switch (INSTRUCTION_CACHE_ASSOCIATIVITY(Cp15CacheInfo()))\r
+  {\r
+    case CACHE_ASSOCIATIVITY_8_WAY:   return 8;\r
+    case CACHE_ASSOCIATIVITY_4_WAY:   return 4;\r
+    case CACHE_ASSOCIATIVITY_DIRECT:  return 1;\r
+    default:                          return 0;\r
+  }\r
+}\r
+  \r
+UINTN\r
+EFIAPI\r
+ArmInstructionCacheLineLength (\r
+  VOID\r
+  )\r
+{\r
+  switch (INSTRUCTION_CACHE_LINE_LENGTH(Cp15CacheInfo()))\r
+  {\r
+    case CACHE_LINE_LENGTH_32_BYTES: return 32;\r
+    default:                         return  0;\r
+  }\r
+}\r
+\r
+\r
diff --git a/edk2/ArmPkg/Library/ArmLib/Arm9/Arm9Lib.c b/edk2/ArmPkg/Library/ArmLib/Arm9/Arm9Lib.c
new file mode 100644 (file)
index 0000000..0ba2237
--- /dev/null
@@ -0,0 +1,118 @@
+/** @file
+
+  Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+  
+  All rights reserved. This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Chipset/ARM926EJ-S.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+VOID
+FillTranslationTable (
+  IN  UINT32                        *TranslationTable,
+  IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryRegion
+  )
+{
+  UINT32  *Entry;
+  UINTN   Sections;
+  UINTN   Index;
+  UINT32  Attributes;
+  UINT32  PhysicalBase = MemoryRegion->PhysicalBase;
+  
+  switch (MemoryRegion->Attributes) {
+    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
+      Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
+      break;
+    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
+      Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;
+      break;
+    case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
+    default:
+      Attributes = TT_DESCRIPTOR_SECTION_UNCACHED_UNBUFFERED;
+      break;
+  }
+  
+  Entry    = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
+  Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE;
+  
+  for (Index = 0; Index < Sections; Index++)
+  {
+    *Entry++     =  TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
+    PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
+  }
+}
+
+VOID
+EFIAPI
+ArmConfigureMmu (
+  IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
+  OUT VOID                          **TranslationTableBase OPTIONAL,
+  OUT UINTN                         *TranslationTableSize  OPTIONAL
+  )
+{
+  VOID  *TranslationTable;
+
+  // Allocate pages for translation table.
+  TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
+  TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
+
+  if (TranslationTableBase != NULL) {
+    *TranslationTableBase = TranslationTable;
+  }
+  
+  if (TranslationTableBase != NULL) {
+    *TranslationTableSize = TRANSLATION_TABLE_SIZE;
+  }
+
+  ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
+
+  ArmCleanInvalidateDataCache();
+  ArmInvalidateInstructionCache();
+  ArmInvalidateTlb();
+
+  ArmDisableDataCache();
+  ArmDisableInstructionCache();
+  ArmDisableMmu();
+
+  // Make sure nothing sneaked into the cache
+  ArmCleanInvalidateDataCache();
+  ArmInvalidateInstructionCache();
+
+  while (MemoryTable->Length != 0) {
+    FillTranslationTable(TranslationTable, MemoryTable);
+    MemoryTable++;
+  }
+
+  ArmSetTranslationTableBaseAddress(TranslationTable);
+    
+  ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
+                            DOMAIN_ACCESS_CONTROL_NONE(14) |
+                            DOMAIN_ACCESS_CONTROL_NONE(13) |
+                            DOMAIN_ACCESS_CONTROL_NONE(12) |
+                            DOMAIN_ACCESS_CONTROL_NONE(11) |
+                            DOMAIN_ACCESS_CONTROL_NONE(10) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 9) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 8) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 7) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 6) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 5) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 4) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 3) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 2) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 1) |
+                            DOMAIN_ACCESS_CONTROL_MANAGER(0));
+    
+  ArmEnableInstructionCache();
+  ArmEnableDataCache();
+  ArmEnableMmu();
+}
diff --git a/edk2/ArmPkg/Library/ArmLib/Arm9/Arm9Support.S b/edk2/ArmPkg/Library/ArmLib/Arm9/Arm9Support.S
new file mode 100644 (file)
index 0000000..5c9afe9
--- /dev/null
@@ -0,0 +1,128 @@
+#------------------------------------------------------------------------------ 
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+.text
+.align 2
+.globl ASM_PFX(ArmCleanInvalidateDataCache)
+.globl ASM_PFX(ArmCleanDataCache)
+.globl ASM_PFX(ArmInvalidateDataCache)
+.globl ASM_PFX(ArmInvalidateInstructionCache)
+.globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
+.globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
+.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
+.globl ASM_PFX(ArmEnableMmu)
+.globl ASM_PFX(ArmDisableMmu)
+.globl ASM_PFX(ArmEnableDataCache)
+.globl ASM_PFX(ArmDisableDataCache)
+.globl ASM_PFX(ArmEnableInstructionCache)
+.globl ASM_PFX(ArmDisableInstructionCache)
+.globl ASM_PFX(ArmEnableBranchPrediction)
+.globl ASM_PFX(ArmDisableBranchPrediction)
+
+.set DC_ON, (1<<2)
+.set IC_ON, (1<<12)
+
+#------------------------------------------------------------------------------
+
+ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
+  mcr     p15, 0, r0, c7, c6, 1   @ invalidate single data cache line                                           
+  bx      lr
+
+ASM_PFX(ArmCleanDataCacheEntryByMVA):
+  mcr     p15, 0, r0, c7, c10, 1  @ clean single data cache line     
+  bx      lr
+
+ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
+  mcr     p15, 0, r0, c7, c14, 1  @ clean and invalidate single data cache line
+  bx      lr
+
+ASM_PFX(ArmEnableInstructionCache):
+  ldr    r1,=IC_ON
+  mrc    p15,0,r0,c1,c0,0     @Read control register configuration data
+  orr    r0,r0,r1             @Set I bit
+  mcr    p15,0,r0,c1,c0,0     @Write control register configuration data
+  bx     LR
+       
+ASM_PFX(ArmDisableInstructionCache):
+  ldr    r1,=IC_ON
+  mrc    p15,0,r0,c1,c0,0     @Read control register configuration data
+  bic    r0,r0,r1             @Clear I bit.
+  mcr    p15,0,r0,c1,c0,0     @Write control register configuration data
+  bx     LR
+       
+ASM_PFX(ArmInvalidateInstructionCache):
+  mov     r0,#0
+  mcr     p15,0,r0,c7,c5,0     @Invalidate entire Instruction cache. 
+                              @Also flushes the branch target cache.
+  mov     r0,#0
+  mcr     p15,0,r0,c7,c10,4    @Data write buffer
+  bx      LR
+
+ASM_PFX(ArmEnableMmu):
+  mrc     p15,0,R0,c1,c0,0
+  orr     R0,R0,#1
+  mcr     p15,0,R0,c1,c0,0
+  bx      LR
+
+ASM_PFX(ArmDisableMmu):
+  mrc     p15,0,R0,c1,c0,0
+  bic     R0,R0,#1
+  mcr     p15,0,R0,c1,c0,0
+  mov     R0,#0
+  mcr     p15,0,R0,c7,c10,4     @Drain write buffer
+  bx      LR
+
+ASM_PFX(ArmEnableDataCache):
+  ldr     R1,=DC_ON
+  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
+  orr     R0,R0,R1              @Set C bit
+  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
+  bx      LR
+       
+ASM_PFX(ArmDisableDataCache):
+  ldr     R1,=DC_ON
+  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
+  bic     R0,R0,R1              @Clear C bit
+  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
+  bx      LR
+
+ASM_PFX(ArmCleanDataCache):
+  mrc     p15,0,r15,c7,c10,3
+  bne     ASM_PFX(ArmCleanDataCache)
+  mov     R0,#0
+  mcr     p15,0,R0,c7,c10,4    @Drain write buffer
+  bx      LR
+    
+ASM_PFX(ArmInvalidateDataCache):
+  mov     R0,#0
+  mcr     p15,0,R0,c7,c6,0        @Invalidate entire data cache
+  mov     R0,#0
+  mcr     p15,0,R0,c7,c10,4       @Drain write buffer
+  bx      LR
+
+ASM_PFX(ArmCleanInvalidateDataCache):
+  mrc     p15,0,r15,c7,c14,3
+  bne     ASM_PFX(ArmCleanInvalidateDataCache)
+  mov     R0,#0
+  mcr     p15,0,R0,c7,c10,4          @Drain write buffer
+  bx      LR
+
+ASM_PFX(ArmEnableBranchPrediction):
+  bx      LR                      @Branch prediction is not supported.
+
+ASM_PFX(ArmDisableBranchPrediction):
+  bx      LR                      @Branch prediction is not supported.
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
+
diff --git a/edk2/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm b/edk2/ArmPkg/Library/ArmLib/Arm9/Arm9Support.asm
new file mode 100644 (file)
index 0000000..3204d66
--- /dev/null
@@ -0,0 +1,129 @@
+//------------------------------------------------------------------------------ 
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+    EXPORT  ArmCleanInvalidateDataCache
+    EXPORT  ArmCleanDataCache
+    EXPORT  ArmInvalidateDataCache
+    EXPORT  ArmInvalidateInstructionCache
+    EXPORT  ArmInvalidateDataCacheEntryByMVA
+    EXPORT  ArmCleanDataCacheEntryByMVA
+    EXPORT  ArmCleanInvalidateDataCacheEntryByMVA
+    EXPORT  ArmEnableMmu
+    EXPORT  ArmDisableMmu
+    EXPORT  ArmEnableDataCache
+    EXPORT  ArmDisableDataCache
+    EXPORT  ArmEnableInstructionCache
+    EXPORT  ArmDisableInstructionCache
+    EXPORT  ArmEnableBranchPrediction
+    EXPORT  ArmDisableBranchPrediction
+
+
+DC_ON       EQU     ( 0x1:SHL:2 )
+IC_ON       EQU     ( 0x1:SHL:12 )
+
+    AREA    ArmCacheLib, CODE, READONLY
+    PRESERVE8
+
+
+ArmInvalidateDataCacheEntryByMVA
+  MCR     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line                                           
+  BX      lr
+
+
+ArmCleanDataCacheEntryByMVA
+  MCR     p15, 0, r0, c7, c10, 1  ; clean single data cache line     
+  BX      lr
+
+
+ArmCleanInvalidateDataCacheEntryByMVA
+  MCR     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
+  BX      lr
+
+ArmEnableInstructionCache
+  LDR     R1,=IC_ON
+  MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
+  ORR     R0,R0,R1             ;Set I bit
+  MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
+  BX      LR
+  
+ArmDisableInstructionCache
+  LDR     R1,=IC_ON
+  MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
+  BIC     R0,R0,R1             ;Clear I bit.
+  MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
+  BX      LR
+
+ArmInvalidateInstructionCache
+  MOV     R0,#0
+  MCR     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache
+  MOV     R0,#0
+  MCR     p15,0,R0,c7,c10,4     ;Drain write buffer
+  BX      LR
+
+ArmEnableMmu
+  mrc     p15,0,R0,c1,c0,0
+  orr     R0,R0,#1
+  mcr     p15,0,R0,c1,c0,0
+  bx      LR
+
+ArmDisableMmu
+  mrc     p15,0,R0,c1,c0,0
+  bic     R0,R0,#1
+  mcr     p15,0,R0,c1,c0,0
+  mov     R0,#0
+  mcr     p15,0,R0,c7,c10,4     ;Drain write buffer
+  bx      LR
+
+ArmEnableDataCache
+  LDR     R1,=DC_ON
+  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
+  ORR     R0,R0,R1              ;Set C bit
+  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
+  BX      LR
+    
+ArmDisableDataCache
+  LDR     R1,=DC_ON
+  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
+  BIC     R0,R0,R1              ;Clear C bit
+  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
+  BX      LR
+
+ArmCleanDataCache
+  MRC     p15,0,r15,c7,c10,3
+  BNE     ArmCleanDataCache
+  MOV     R0,#0
+  MCR     p15,0,R0,c7,c10,4        ;Drain write buffer
+  BX      LR
+
+ArmInvalidateDataCache
+  MOV     R0,#0
+  MCR     p15,0,R0,c7,c6,0      ;Invalidate entire data cache
+  MOV     R0,#0
+  MCR     p15,0,R0,c7,c10,4     ;Drain write buffer
+  BX      LR
+  
+ArmCleanInvalidateDataCache
+  MRC     p15,0,r15,c7,c14,3
+  BNE     ArmCleanInvalidateDataCache
+  MOV     R0,#0
+  MCR     p15,0,R0,c7,c10,4        ;Drain write buffer
+  BX      LR
+
+ArmEnableBranchPrediction
+  bx      LR                    ;Branch prediction is not supported.
+
+ArmDisableBranchPrediction
+  bx      LR                    ;Branch prediction is not supported.
+
+    END
diff --git a/edk2/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexALib.c b/edk2/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexALib.c
new file mode 100644 (file)
index 0000000..4dfa18d
--- /dev/null
@@ -0,0 +1,288 @@
+/** @file
+
+  Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+  
+  All rights reserved. This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Chipset/Cortex-A8.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include "ArmCortexALib.h"
+
+VOID
+FillTranslationTable (
+  IN  UINT32                        *TranslationTable,
+  IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryRegion
+  )
+{
+  UINT32  *Entry;
+  UINTN   Sections;
+  UINTN   Index;
+  UINT32  Attributes;
+  UINT32  PhysicalBase = MemoryRegion->PhysicalBase;
+  
+  switch (MemoryRegion->Attributes) {
+    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK:
+      Attributes = TT_DESCRIPTOR_SECTION_WRITE_BACK;
+      break;
+    case ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH:
+      Attributes = TT_DESCRIPTOR_SECTION_WRITE_THROUGH;
+      break;
+    case ARM_MEMORY_REGION_ATTRIBUTE_DEVICE:
+      Attributes = TT_DESCRIPTOR_SECTION_DEVICE;
+      break;
+    case ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED:
+    default:
+      Attributes = TT_DESCRIPTOR_SECTION_UNCACHED;
+      break;
+  }
+  
+  Entry    = TRANSLATION_TABLE_ENTRY_FOR_VIRTUAL_ADDRESS(TranslationTable, MemoryRegion->VirtualBase);
+  Sections = MemoryRegion->Length / TT_DESCRIPTOR_SECTION_SIZE;
+  
+  for (Index = 0; Index < Sections; Index++)
+  {
+    *Entry++     =  TT_DESCRIPTOR_SECTION_BASE_ADDRESS(PhysicalBase) | Attributes;
+    PhysicalBase += TT_DESCRIPTOR_SECTION_SIZE;
+  }
+}
+
+VOID
+EFIAPI
+ArmConfigureMmu (
+  IN  ARM_MEMORY_REGION_DESCRIPTOR  *MemoryTable,
+  OUT VOID                          **TranslationTableBase OPTIONAL,
+  OUT UINTN                         *TranslationTableSize  OPTIONAL
+  )
+{
+  VOID  *TranslationTable;
+
+  // Allocate pages for translation table.
+  TranslationTable = AllocatePages(EFI_SIZE_TO_PAGES(TRANSLATION_TABLE_SIZE + TRANSLATION_TABLE_ALIGNMENT));
+  TranslationTable = (VOID *)(((UINTN)TranslationTable + TRANSLATION_TABLE_ALIGNMENT_MASK) & ~TRANSLATION_TABLE_ALIGNMENT_MASK);
+
+  if (TranslationTableBase != NULL) {
+    *TranslationTableBase = TranslationTable;
+  }
+  
+  if (TranslationTableBase != NULL) {
+    *TranslationTableSize = TRANSLATION_TABLE_SIZE;
+  }
+
+  ZeroMem(TranslationTable, TRANSLATION_TABLE_SIZE);
+
+  ArmCleanInvalidateDataCache();
+  ArmInvalidateInstructionCache();
+  ArmInvalidateTlb();
+
+  ArmDisableDataCache();
+  ArmDisableInstructionCache();
+  ArmDisableMmu();
+
+  // Make sure nothing sneaked into the cache
+  ArmCleanInvalidateDataCache();
+  ArmInvalidateInstructionCache();
+
+  while (MemoryTable->Length != 0) {
+    FillTranslationTable(TranslationTable, MemoryTable);
+    MemoryTable++;
+  }
+
+  ArmSetTranslationTableBaseAddress(TranslationTable);
+    
+  ArmSetDomainAccessControl(DOMAIN_ACCESS_CONTROL_NONE(15) |
+                            DOMAIN_ACCESS_CONTROL_NONE(14) |
+                            DOMAIN_ACCESS_CONTROL_NONE(13) |
+                            DOMAIN_ACCESS_CONTROL_NONE(12) |
+                            DOMAIN_ACCESS_CONTROL_NONE(11) |
+                            DOMAIN_ACCESS_CONTROL_NONE(10) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 9) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 8) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 7) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 6) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 5) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 4) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 3) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 2) |
+                            DOMAIN_ACCESS_CONTROL_NONE( 1) |
+                            DOMAIN_ACCESS_CONTROL_MANAGER(0));
+    
+  ArmEnableInstructionCache();
+  ArmEnableDataCache();
+  ArmEnableMmu();
+}
+
+ARM_CACHE_TYPE
+EFIAPI
+ArmCacheType (
+  VOID
+  )
+{
+  return ARM_CACHE_TYPE_WRITE_BACK;
+}
+
+ARM_CACHE_ARCHITECTURE
+EFIAPI
+ArmCacheArchitecture (
+  VOID
+  )
+{
+  return ARM_CACHE_ARCHITECTURE_SEPARATE;
+}
+
+BOOLEAN
+EFIAPI
+ArmDataCachePresent (
+  VOID
+  )
+{
+  return TRUE;
+}
+  
+UINTN
+EFIAPI
+ArmDataCacheSize (
+  VOID
+  )
+{
+  return  16 * 1024;      
+}
+  
+UINTN
+EFIAPI
+ArmDataCacheAssociativity (
+  VOID
+  )
+{
+  return 4;
+}
+  
+UINTN
+ArmDataCacheSets (
+  VOID
+  )
+{
+  return 64;
+}
+
+UINTN
+EFIAPI
+ArmDataCacheLineLength (
+  VOID
+  )
+{
+  return 64;
+}
+  
+BOOLEAN
+EFIAPI
+ArmInstructionCachePresent (
+  VOID
+  )
+{
+  return TRUE;
+}
+  
+UINTN
+EFIAPI
+ArmInstructionCacheSize (
+  VOID
+  )
+{
+  return  16 * 1024;      
+}
+  
+UINTN
+EFIAPI
+ArmInstructionCacheAssociativity (
+  VOID
+  )
+{
+  return 4;
+}
+  
+UINTN
+EFIAPI
+ArmInstructionCacheLineLength (
+  VOID
+  )
+{
+  return 64;
+}
+
+VOID
+ArmCortexADataCacheOperation (
+  IN  ARM_CORTEX_A_CACHE_OPERATION  DataCacheOperation
+  )
+{
+  UINTN     Set;
+  UINTN     SetCount;
+  UINTN     SetShift;
+  UINTN     Way;
+  UINTN     WayCount;
+  UINTN     WayShift;
+  UINT32    SetWayFormat;
+  UINTN     SavedInterruptState;
+
+  SetCount = ArmDataCacheSets();
+  WayCount = ArmDataCacheAssociativity();
+
+  // Cortex-A8 Manual, System Control Coprocessor chapter
+  SetShift = 6;
+  WayShift = 32 - LowBitSet32 ((UINT32)WayCount);
+  
+  SavedInterruptState = ArmDisableInterrupts();
+      
+  for (Way = 0; Way < WayCount; Way++) {
+    for (Set = 0; Set < SetCount; Set++) {      
+      // Build the format that the CP15 instruction can understand
+      SetWayFormat = (Way << WayShift) | (Set << SetShift);
+
+      // Pass it through
+      (*DataCacheOperation)(SetWayFormat);
+    }
+  }
+  
+  ArmDrainWriteBuffer();
+  
+  if (SavedInterruptState) {
+    ArmEnableInterrupts();
+  }
+}
+
+VOID
+EFIAPI
+ArmInvalidateDataCache (
+  VOID
+  )
+{
+  ArmCortexADataCacheOperation(ArmInvalidateDataCacheEntryBySetWay);
+}
+
+VOID
+EFIAPI
+ArmCleanInvalidateDataCache (
+  VOID
+  )
+{
+  ArmCortexADataCacheOperation(ArmCleanInvalidateDataCacheEntryBySetWay);
+}
+
+VOID
+EFIAPI
+ArmCleanDataCache (
+  VOID
+  )
+{
+  ArmCortexADataCacheOperation(ArmCleanDataCacheEntryBySetWay);
+}
diff --git a/edk2/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexALib.h b/edk2/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexALib.h
new file mode 100644 (file)
index 0000000..afe98bd
--- /dev/null
@@ -0,0 +1,45 @@
+/** @file
+
+  Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
+
+  All rights reserved. This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef __ARMCORTEXALIB_H__
+#define __ARMCORTEXALIB_H__
+
+typedef VOID (*ARM_CORTEX_A_CACHE_OPERATION)(UINT32);
+
+VOID
+EFIAPI
+ArmDrainWriteBuffer (
+  VOID
+  );
+
+VOID
+EFIAPI
+ArmInvalidateDataCacheEntryBySetWay (
+  IN  UINT32  SetWayFormat
+  );
+
+VOID
+EFIAPI
+ArmCleanDataCacheEntryBySetWay (
+  IN  UINT32  SetWayFormat
+  );
+
+VOID
+EFIAPI
+ArmCleanInvalidateDataCacheEntryBySetWay (
+  IN  UINT32   SetWayFormat
+  );
+
+#endif // __ARMCORTEXALIB_H__
+
diff --git a/edk2/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexASupport.S b/edk2/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexASupport.S
new file mode 100644 (file)
index 0000000..0e24f63
--- /dev/null
@@ -0,0 +1,140 @@
+#------------------------------------------------------------------------------ 
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+.text
+.align 2
+.globl ASM_PFX(ArmInvalidateInstructionCache)
+.globl ASM_PFX(ArmInvalidateDataCacheEntryByMVA)
+.globl ASM_PFX(ArmCleanDataCacheEntryByMVA)
+.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA)
+.globl ASM_PFX(ArmInvalidateDataCacheEntryBySetWay)
+.globl ASM_PFX(ArmCleanDataCacheEntryBySetWay)
+.globl ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay)
+.globl ASM_PFX(ArmDrainWriteBuffer)
+.globl ASM_PFX(ArmEnableMmu)
+.globl ASM_PFX(ArmDisableMmu)
+.globl ASM_PFX(ArmEnableDataCache)
+.globl ASM_PFX(ArmDisableDataCache)
+.globl ASM_PFX(ArmEnableInstructionCache)
+.globl ASM_PFX(ArmDisableInstructionCache)
+.globl ASM_PFX(ArmEnableExtendPTConfig)
+.globl ASM_PFX(ArmDisableExtendPTConfig)
+.globl ASM_PFX(ArmEnableBranchPrediction)
+.globl ASM_PFX(ArmDisableBranchPrediction)
+
+.set DC_ON, (0x1<<2)
+.set IC_ON, (0x1<<12)
+.set XP_ON, (0x1<<23)
+
+ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
+  mcr     p15, 0, r0, c7, c6, 1   @invalidate single data cache line                                           
+  bx      lr
+
+
+ASM_PFX(ArmCleanDataCacheEntryByMVA):
+  mcr     p15, 0, r0, c7, c10, 1  @clean single data cache line     
+  bx      lr
+
+
+ASM_PFX(ArmCleanInvalidateDataCacheEntryByMVA):
+  mcr     p15, 0, r0, c7, c14, 1  @clean and invalidate single data cache line
+  bx      lr
+
+
+ASM_PFX(ArmInvalidateDataCacheEntryBySetWay):
+  mcr     p15, 0, r0, c7, c6, 2        @ Invalidate this line          
+  bx      lr
+
+
+ASM_PFX(ArmCleanInvalidateDataCacheEntryBySetWay):
+  mcr     p15, 0, r0, c7, c14, 2       @ Clean and Invalidate this line                
+  bx      lr
+
+
+ASM_PFX(ArmCleanDataCacheEntryBySetWay):
+  mcr     p15, 0, r0, c7, c10, 2       @ Clean this line               
+  bx      lr
+
+
+ASM_PFX(ArmDrainWriteBuffer):
+  mcr     p15, 0, r0, c7, c10, 4       @ Drain write buffer for sync
+  bx      lr
+  
+
+ASM_PFX(ArmInvalidateInstructionCache):
+  mov     R0,#0
+  mcr     p15,0,R0,c7,c5,0      @Invalidate entire instruction cache
+  mov     R0,#0
+  mcr     p15,0,R0,c7,c5,4      @Instruction synchronization barrier
+  bx      LR
+
+ASM_PFX(ArmEnableMmu):
+  mrc     p15,0,R0,c1,c0,0
+  orr     R0,R0,#1
+  mcr     p15,0,R0,c1,c0,0
+  bx      LR
+
+ASM_PFX(ArmDisableMmu):
+  mov     R0,#0
+  mcr     p15,0,R0,c13,c0,0     @FCSE PID register must be cleared before disabling MMU
+  mrc     p15,0,R0,c1,c0,0
+  bic     R0,R0,#1
+  mcr     p15,0,R0,c1,c0,0      @Disable MMU
+  mov     R0,#0
+  mcr     p15,0,R0,c7,c10,4     @Data synchronization barrier
+  mov     R0,#0
+  mcr     p15,0,R0,c7,c5,4      @Instruction synchronization barrier
+  bx      LR
+
+ASM_PFX(ArmEnableDataCache):
+  ldr     R1,=DC_ON
+  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
+  orr     R0,R0,R1              @Set C bit
+  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
+  bx      LR
+    
+ASM_PFX(ArmDisableDataCache):
+  ldr     R1,=DC_ON
+  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
+  bic     R0,R0,R1              @Clear C bit
+  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
+  bx      LR
+
+ASM_PFX(ArmEnableInstructionCache):
+  ldr     R1,=IC_ON
+  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
+  orr     R0,R0,R1              @Set I bit
+  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
+  bx      LR
+  
+ASM_PFX(ArmDisableInstructionCache):
+  ldr     R1,=IC_ON
+  mrc     p15,0,R0,c1,c0,0      @Read control register configuration data
+  bic     R0,R0,R1              @Clear I bit.
+  mcr     p15,0,r0,c1,c0,0      @Write control register configuration data
+  bx      LR
+
+ASM_PFX(ArmEnableBranchPrediction):
+  mrc     p15, 0, r0, c1, c0, 0
+  orr     r0, r0, #0x00000800
+  mcr     p15, 0, r0, c1, c0, 0
+  bx      LR
+
+ASM_PFX(ArmDisableBranchPrediction):
+  mrc     p15, 0, r0, c1, c0, 0
+  bic     r0, r0, #0x00000800
+  mcr     p15, 0, r0, c1, c0, 0
+  bx      LR
+
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/edk2/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexASupport.asm b/edk2/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexASupport.asm
new file mode 100644 (file)
index 0000000..dbd8bd2
--- /dev/null
@@ -0,0 +1,141 @@
+//------------------------------------------------------------------------------ 
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+    EXPORT  ArmInvalidateInstructionCache
+    EXPORT  ArmInvalidateDataCacheEntryByMVA
+    EXPORT  ArmCleanDataCacheEntryByMVA
+    EXPORT  ArmCleanInvalidateDataCacheEntryByMVA
+    EXPORT  ArmInvalidateDataCacheEntryBySetWay
+    EXPORT  ArmCleanDataCacheEntryBySetWay
+    EXPORT  ArmCleanInvalidateDataCacheEntryBySetWay
+    EXPORT  ArmDrainWriteBuffer
+    EXPORT  ArmEnableMmu
+    EXPORT  ArmDisableMmu
+    EXPORT  ArmEnableDataCache
+    EXPORT  ArmDisableDataCache
+    EXPORT  ArmEnableInstructionCache
+    EXPORT  ArmDisableInstructionCache
+    EXPORT  ArmEnableBranchPrediction
+    EXPORT  ArmDisableBranchPrediction
+
+DC_ON       EQU     ( 0x1:SHL:2 )
+IC_ON       EQU     ( 0x1:SHL:12 )
+XP_ON       EQU     ( 0x1:SHL:23 )
+
+
+    AREA    ArmCacheLib, CODE, READONLY
+    PRESERVE8
+
+
+ArmInvalidateDataCacheEntryByMVA
+  MCR     p15, 0, r0, c7, c6, 1   ; invalidate single data cache line                                           
+  BX      lr
+
+
+ArmCleanDataCacheEntryByMVA
+  MCR     p15, 0, r0, c7, c10, 1  ; clean single data cache line     
+  BX      lr
+
+
+ArmCleanInvalidateDataCacheEntryByMVA
+  MCR     p15, 0, r0, c7, c14, 1  ; clean and invalidate single data cache line
+  BX      lr
+
+
+ArmInvalidateDataCacheEntryBySetWay
+  mcr     p15, 0, r0, c7, c6, 2        ; Invalidate this line          
+  bx      lr
+
+
+ArmCleanInvalidateDataCacheEntryBySetWay
+  mcr     p15, 0, r0, c7, c14, 2       ; Clean and Invalidate this line                
+  bx      lr
+
+
+ArmCleanDataCacheEntryBySetWay
+  mcr     p15, 0, r0, c7, c10, 2       ; Clean this line               
+  bx      lr
+
+
+ArmDrainWriteBuffer
+  mcr     p15, 0, r0, c7, c10, 4       ; Drain write buffer for sync
+  bx      lr
+
+
+ArmInvalidateInstructionCache
+  MOV     R0,#0
+  MCR     p15,0,R0,c7,c5,0      ;Invalidate entire instruction cache
+  MOV     R0,#0
+  MCR     p15,0,R0,c7,c5,4      ;Instruction synchronization barrier
+  BX      LR
+
+ArmEnableMmu
+  mrc     p15,0,R0,c1,c0,0
+  orr     R0,R0,#1
+  mcr     p15,0,R0,c1,c0,0
+  bx      LR
+
+ArmDisableMmu
+  mov     R0,#0
+  mcr     p15,0,R0,c13,c0,0     ;FCSE PID register must be cleared before disabling MMU
+  mrc     p15,0,R0,c1,c0,0
+  bic     R0,R0,#1
+  mcr     p15,0,R0,c1,c0,0      ;Disable MMU
+  mov     R0,#0
+  mcr     p15,0,R0,c7,c10,4     ;Data synchronization barrier
+  mov     R0,#0
+  mcr     p15,0,R0,c7,c5,4      ;Instruction synchronization barrier
+  bx      LR
+
+ArmEnableDataCache
+  LDR     R1,=DC_ON
+  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
+  ORR     R0,R0,R1              ;Set C bit
+  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
+  BX      LR
+    
+ArmDisableDataCache
+  LDR     R1,=DC_ON
+  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
+  BIC     R0,R0,R1              ;Clear C bit
+  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
+  BX      LR
+
+ArmEnableInstructionCache
+  LDR     R1,=IC_ON
+  MRC     p15,0,R0,c1,c0,0      ;Read control register configuration data
+  ORR     R0,R0,R1              ;Set I bit
+  MCR     p15,0,r0,c1,c0,0      ;Write control register configuration data
+  BX      LR
+  
+ArmDisableInstructionCache
+  LDR     R1,=IC_ON
+  MRC     p15,0,R0,c1,c0,0     ;Read control register configuration data
+  BIC     R0,R0,R1             ;Clear I bit.
+  MCR     p15,0,r0,c1,c0,0     ;Write control register configuration data
+  BX      LR
+
+ArmEnableBranchPrediction
+  mrc     p15, 0, r0, c1, c0, 0
+  orr     r0, r0, #0x00000800
+  mcr     p15, 0, r0, c1, c0, 0
+  bx      LR
+
+ArmDisableBranchPrediction
+  mrc     p15, 0, r0, c1, c0, 0
+  bic     r0, r0, #0x00000800
+  mcr     p15, 0, r0, c1, c0, 0
+  bx      LR
+
+    END
diff --git a/edk2/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLib.inf b/edk2/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLib.inf
new file mode 100644 (file)
index 0000000..54b77e3
--- /dev/null
@@ -0,0 +1,31 @@
+#%HEADER%\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = ArmCortexArmLib\r
+  FILE_GUID                      = 411cdfd8-f964-4b9d-a3e3-1719a9c15559\r
+  MODULE_TYPE                    = DXE_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = ArmLib\r
+\r
+[Sources.common]\r
+  ../Common/ArmLibSupport.S    | GCC\r
+  ../Common/ArmLibSupport.asm  | RVCT\r
+  ../Common/ArmLib.c\r
+  \r
+  ArmCortexASupport.S    | GCC\r
+  ArmCortexASupport.asm  | RVCT\r
+\r
+  ArmCortexALib.c\r
+\r
+[Packages]\r
+  ArmPkg/ArmPkg.dec\r
+  MdePkg/MdePkg.dec\r
+\r
+[LibraryClasses]\r
+  MemoryAllocationLib\r
+  \r
+[Protocols]\r
+  gEfiCpuArchProtocolGuid\r
+\r
+[FixedPcd]\r
+  gArmTokenSpaceGuid.PcdArmCacheOperationThreshold\r
diff --git a/edk2/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLibPrePi.inf b/edk2/ArmPkg/Library/ArmLib/ArmCortexA/ArmCortexArmLibPrePi.inf
new file mode 100644 (file)
index 0000000..450dfe5
--- /dev/null
@@ -0,0 +1,31 @@
+#%HEADER%\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = ArmCortexArmLibPrePi\r
+  FILE_GUID                      = A150FA0C-F4E8-4207-9BEB-CD6DFB430D73\r
+  MODULE_TYPE                    = DXE_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = ArmLib\r
+\r
+[Sources.common]\r
+  ../Common/ArmLibSupport.S    | GCC\r
+  ../Common/ArmLibSupport.asm  | RVCT\r
+  ../Common/ArmLib.c\r
+  \r
+  ArmCortexASupport.S    | GCC\r
+  ArmCortexASupport.asm  | RVCT\r
+\r
+  ArmCortexALib.c\r
+\r
+[Packages]\r
+  ArmPkg/ArmPkg.dec\r
+  MdePkg/MdePkg.dec\r
+\r
+[LibraryClasses]\r
+  PrePiLib\r
+  \r
+[Protocols]\r
+  gEfiCpuArchProtocolGuid\r
+\r
+[FixedPcd]\r
+  gArmTokenSpaceGuid.PcdArmCacheOperationThreshold\r
diff --git a/edk2/ArmPkg/Library/ArmLib/Common/ArmLib.c b/edk2/ArmPkg/Library/ArmLib/Common/ArmLib.c
new file mode 100644 (file)
index 0000000..b015dc4
--- /dev/null
@@ -0,0 +1,60 @@
+/** @file\r
+\r
+  Copyright (c) 2008-2009, Apple Inc. All rights reserved.\r
+  \r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Base.h>\r
+\r
+#include <Library/ArmLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+#include "ArmLibPrivate.h"\r
+\r
+VOID\r
+EFIAPI\r
+ArmCacheInformation (\r
+  OUT ARM_CACHE_INFO  *CacheInfo\r
+  )\r
+{\r
+  if (CacheInfo != NULL) {\r
+    CacheInfo->Type                           = ArmCacheType();\r
+    CacheInfo->Architecture                   = ArmCacheArchitecture();\r
+    CacheInfo->DataCachePresent               = ArmDataCachePresent();\r
+    CacheInfo->DataCacheSize                  = ArmDataCacheSize();\r
+    CacheInfo->DataCacheAssociativity         = ArmDataCacheAssociativity();\r
+    CacheInfo->DataCacheLineLength            = ArmDataCacheLineLength();\r
+    CacheInfo->InstructionCachePresent        = ArmInstructionCachePresent();\r
+    CacheInfo->InstructionCacheSize           = ArmInstructionCacheSize();\r
+    CacheInfo->InstructionCacheAssociativity  = ArmInstructionCacheAssociativity();\r
+    CacheInfo->InstructionCacheLineLength     = ArmInstructionCacheLineLength();\r
+  }\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmSwitchProcessorMode (\r
+  IN ARM_PROCESSOR_MODE Mode\r
+  )\r
+{\r
+  CPSRMaskInsert(ARM_PROCESSOR_MODE_MASK, Mode);\r
+}\r
+\r
+\r
+ARM_PROCESSOR_MODE\r
+EFIAPI\r
+ArmProcessorMode (\r
+  VOID\r
+  )\r
+{\r
+  return (ARM_PROCESSOR_MODE)(CPSRRead() & (UINT32)ARM_PROCESSOR_MODE_MASK);\r
+}\r
diff --git a/edk2/ArmPkg/Library/ArmLib/Common/ArmLibPrivate.h b/edk2/ArmPkg/Library/ArmLib/Common/ArmLibPrivate.h
new file mode 100644 (file)
index 0000000..d1d2523
--- /dev/null
@@ -0,0 +1,70 @@
+/** @file\r
+\r
+  Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>\r
+\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __ARM_LIB_PRIVATE_H__\r
+#define __ARM_LIB_PRIVATE_H__\r
+\r
+#define CACHE_SIZE_4_KB             (3UL)\r
+#define CACHE_SIZE_8_KB             (4UL)\r
+#define CACHE_SIZE_16_KB            (5UL)\r
+#define CACHE_SIZE_32_KB            (6UL)\r
+#define CACHE_SIZE_64_KB            (7UL)\r
+#define CACHE_SIZE_128_KB           (8UL)\r
+\r
+#define CACHE_ASSOCIATIVITY_DIRECT  (0UL)\r
+#define CACHE_ASSOCIATIVITY_4_WAY   (2UL)\r
+#define CACHE_ASSOCIATIVITY_8_WAY   (3UL)\r
+\r
+#define CACHE_PRESENT               (0UL)\r
+#define CACHE_NOT_PRESENT           (1UL)\r
+\r
+#define CACHE_LINE_LENGTH_32_BYTES  (2UL)\r
+\r
+#define SIZE_FIELD_TO_CACHE_SIZE(x)           (((x) >> 6) & 0x0F)\r
+#define SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(x)  (((x) >> 3) & 0x07)\r
+#define SIZE_FIELD_TO_CACHE_PRESENCE(x)       (((x) >> 2) & 0x01)\r
+#define SIZE_FIELD_TO_CACHE_LINE_LENGTH(x)    (((x) >> 0) & 0x03)\r
+\r
+#define DATA_CACHE_SIZE_FIELD(x)              (((x) >> 12) & 0x0FFF)\r
+#define INSTRUCTION_CACHE_SIZE_FIELD(x)       (((x) >>  0) & 0x0FFF)\r
+\r
+#define DATA_CACHE_SIZE(x)                    (SIZE_FIELD_TO_CACHE_SIZE(DATA_CACHE_SIZE_FIELD(x)))\r
+#define DATA_CACHE_ASSOCIATIVITY(x)           (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(DATA_CACHE_SIZE_FIELD(x)))\r
+#define DATA_CACHE_PRESENT(x)                 (SIZE_FIELD_TO_CACHE_PRESENCE(DATA_CACHE_SIZE_FIELD(x)))\r
+#define DATA_CACHE_LINE_LENGTH(x)             (SIZE_FIELD_TO_CACHE_LINE_LENGTH(DATA_CACHE_SIZE_FIELD(x)))\r
+\r
+#define INSTRUCTION_CACHE_SIZE(x)             (SIZE_FIELD_TO_CACHE_SIZE(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
+#define INSTRUCTION_CACHE_ASSOCIATIVITY(x)    (SIZE_FIELD_TO_CACHE_ASSOCIATIVITY(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
+#define INSTRUCTION_CACHE_PRESENT(x)          (SIZE_FIELD_TO_CACHE_PRESENCE(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
+#define INSTRUCTION_CACHE_LINE_LENGTH(x)      (SIZE_FIELD_TO_CACHE_LINE_LENGTH(INSTRUCTION_CACHE_SIZE_FIELD(x)))\r
+\r
+#define CACHE_TYPE(x)                         (((x) >> 25) & 0x0F)\r
+#define CACHE_TYPE_WRITE_BACK                 (0x0EUL)\r
+\r
+#define CACHE_ARCHITECTURE(x)                 (((x) >> 24) & 0x01)\r
+#define CACHE_ARCHITECTURE_UNIFIED            (0UL)\r
+#define CACHE_ARCHITECTURE_SEPARATE           (1UL)\r
+\r
+VOID\r
+CPSRMaskInsert (\r
+  IN  UINT32  Mask,\r
+  IN  UINT32  Value\r
+  );\r
+\r
+UINT32\r
+CPSRRead (\r
+  VOID\r
+  );\r
+\r
+#endif // __ARM_LIB_PRIVATE_H__\r
diff --git a/edk2/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S b/edk2/ArmPkg/Library/ArmLib/Common/ArmLibSupport.S
new file mode 100644 (file)
index 0000000..d80100c
--- /dev/null
@@ -0,0 +1,89 @@
+#------------------------------------------------------------------------------ 
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+.text
+.align 2
+.globl ASM_PFX(Cp15IdCode)
+.globl ASM_PFX(Cp15CacheInfo)
+.globl ASM_PFX(ArmEnableInterrupts)
+.globl ASM_PFX(ArmDisableInterrupts)
+.globl ASM_PFX(ArmGetInterruptState)
+.globl ASM_PFX(ArmInvalidateTlb)
+.globl ASM_PFX(ArmSetTranslationTableBaseAddress)
+.globl ASM_PFX(ArmSetDomainAccessControl)
+.globl ASM_PFX(CPSRMaskInsert)
+.globl ASM_PFX(CPSRRead)
+
+#------------------------------------------------------------------------------
+
+ASM_PFX(Cp15IdCode):
+  mrc     p15,0,R0,c0,c0,0
+  bx      LR
+
+ASM_PFX(Cp15CacheInfo):
+  mrc     p15,0,R0,c0,c0,1
+  bx      LR
+
+ASM_PFX(ArmEnableInterrupts):
+       mrs     R0,CPSR
+       bic     R0,R0,#0x80             @Enable IRQ interrupts
+       msr     CPSR_c,R0
+       bx      LR
+
+ASM_PFX(ArmDisableInterrupts):
+       mrs     R0,CPSR
+       orr     R1,R0,#0x80             @Disable IRQ interrupts
+       msr     CPSR_c,R1
+  tst     R0,#0x80
+  moveq   R0,#1
+  movne   R0,#0
+       bx      LR
+
+ASM_PFX(ArmGetInterruptState):
+       mrs     R0,CPSR
+       tst     R0,#0x80            @Check if IRQ is enabled.
+       moveq   R0,#1
+       movne   R0,#0
+       bx      LR
+
+ASM_PFX(ArmInvalidateTlb):
+  mov     r0,#0
+  mcr     p15,0,r0,c8,c7,0
+  bx      lr
+
+ASM_PFX(ArmSetTranslationTableBaseAddress):
+  mcr     p15,0,r0,c2,c0,0
+  bx      lr
+
+ASM_PFX(ArmSetDomainAccessControl):
+  mcr     p15,0,r0,c3,c0,0
+  bx      lr
+
+ASM_PFX(CPSRMaskInsert):    @ on entry, r0 is the mask and r1 is the field to insert
+  stmfd   sp!, {r4-r12, lr} @ save all the banked registers
+  mov     r3, sp            @ copy the stack pointer into a non-banked register
+  mrs     r2, cpsr          @ read the cpsr
+  bic     r2, r2, r0        @ clear mask in the cpsr
+  and     r1, r1, r0        @ clear bits outside the mask in the input
+  orr     r2, r2, r1        @ set field
+  msr     cpsr_cxsf, r2     @ write back cpsr (may have caused a mode switch)
+  mov     sp, r3            @ restore stack pointer
+  ldmfd   sp!, {r4-r12, lr} @ restore registers
+  bx      lr                @ return (hopefully thumb-safe!)
+
+ASM_PFX(CPSRRead):
+  mrs     r0, cpsr
+  bx      lr
+  
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
diff --git a/edk2/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm b/edk2/ArmPkg/Library/ArmLib/Common/ArmLibSupport.asm
new file mode 100644 (file)
index 0000000..ec7db63
--- /dev/null
@@ -0,0 +1,90 @@
+//------------------------------------------------------------------------------ 
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+
+    EXPORT  Cp15IdCode
+    EXPORT  Cp15CacheInfo
+    EXPORT  ArmEnableInterrupts
+    EXPORT  ArmDisableInterrupts
+    EXPORT  ArmGetInterruptState
+    EXPORT  ArmInvalidateTlb
+    EXPORT  ArmSetTranslationTableBaseAddress
+    EXPORT  ArmSetDomainAccessControl
+    EXPORT  CPSRMaskInsert
+    EXPORT  CPSRRead
+
+    AREA ArmLibSupport, CODE, READONLY
+
+Cp15IdCode
+  mrc     p15,0,R0,c0,c0,0
+  bx      LR
+
+Cp15CacheInfo
+  mrc     p15,0,R0,c0,c0,1
+  bx      LR
+
+ArmEnableInterrupts
+       mrs     R0,CPSR
+       bic     R0,R0,#0x80             ;Enable IRQ interrupts
+       msr     CPSR_c,R0
+       bx      LR
+
+ArmDisableInterrupts
+       mrs     R0,CPSR
+       orr     R1,R0,#0x80             ;Disable IRQ interrupts
+       msr     CPSR_c,R1
+  tst     R0,#0x80
+  moveq   R0,#1
+  movne   R0,#0
+       bx      LR
+
+ArmGetInterruptState
+       mrs     R0,CPSR
+       tst     R0,#0x80            ;Check if IRQ is enabled.
+       moveq   R0,#1
+       movne   R0,#0
+       bx      LR
+  
+ArmInvalidateTlb
+  mov     r0,#0
+  mcr     p15,0,r0,c8,c7,0
+  bx      lr
+
+ArmSetTranslationTableBaseAddress
+  mcr     p15,0,r0,c2,c0,0
+  bx      lr
+
+ArmSetDomainAccessControl
+  mcr     p15,0,r0,c3,c0,0
+  bx      lr
+
+CPSRMaskInsert              ; on entry, r0 is the mask and r1 is the field to insert
+  stmfd   sp!, {r4-r12, lr} ; save all the banked registers
+  mov     r3, sp            ; copy the stack pointer into a non-banked register
+  mrs     r2, cpsr          ; read the cpsr
+  bic     r2, r2, r0        ; clear mask in the cpsr
+  and     r1, r1, r0        ; clear bits outside the mask in the input
+  orr     r2, r2, r1        ; set field
+  msr     cpsr_cxsf, r2     ; write back cpsr (may have caused a mode switch)
+  mov     sp, r3            ; restore stack pointer
+  ldmfd   sp!, {r4-r12, lr} ; restore registers
+  bx      lr                ; return (hopefully thumb-safe!)
+
+CPSRRead
+  mrs     r0, cpsr
+  bx      lr
+  
+  END
+
+
diff --git a/edk2/ArmPkg/Library/ArmLib/Null/NullArmCacheInformation.c b/edk2/ArmPkg/Library/ArmLib/Null/NullArmCacheInformation.c
new file mode 100644 (file)
index 0000000..08a1ad0
--- /dev/null
@@ -0,0 +1,106 @@
+/** @file\r
+\r
+  Copyright (c) 2008-2009, Apple Inc. All rights reserved.\r
+  \r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Library/ArmLib.h>\r
+#include "ArmLibPrivate.h"\r
+\r
+ARM_CACHE_TYPE\r
+EFIAPI\r
+ArmCacheType (\r
+  VOID\r
+  )\r
+{\r
+  return ARM_CACHE_TYPE_UNKNOWN;\r
+}\r
+\r
+ARM_CACHE_ARCHITECTURE\r
+EFIAPI\r
+ArmCacheArchitecture (\r
+  VOID\r
+  )\r
+{\r
+  return ARM_CACHE_ARCHITECTURE_UNKNOWN;\r
+}\r
+\r
+BOOLEAN\r
+EFIAPI\r
+ArmDataCachePresent (\r
+  VOID\r
+  )\r
+{\r
+  return FALSE;\r
+}\r
+  \r
+UINTN\r
+EFIAPI\r
+ArmDataCacheSize (\r
+  VOID\r
+  )\r
+{\r
+  return 0;      \r
+}\r
+  \r
+UINTN\r
+EFIAPI\r
+ArmDataCacheAssociativity (\r
+  VOID\r
+  )\r
+{\r
+  return 0;\r
+}\r
+  \r
+UINTN\r
+EFIAPI\r
+ArmDataCacheLineLength (\r
+  VOID\r
+  )\r
+{\r
+  return 0;\r
+}\r
+  \r
+BOOLEAN\r
+EFIAPI\r
+ArmInstructionCachePresent (\r
+  VOID\r
+  )\r
+{\r
+  return FALSE;\r
+}\r
+  \r
+UINTN\r
+EFIAPI\r
+ArmInstructionCacheSize (\r
+  VOID\r
+  )\r
+{\r
+  return 0;      \r
+}\r
+  \r
+UINTN\r
+EFIAPI\r
+ArmInstructionCacheAssociativity (\r
+  VOID\r
+  )\r
+{\r
+  return 0;\r
+}\r
+  \r
+UINTN\r
+EFIAPI\r
+ArmInstructionCacheLineLength (\r
+  VOID\r
+  )\r
+{\r
+  return 0;\r
+}\r
diff --git a/edk2/ArmPkg/Library/ArmLib/Null/NullArmLib.c b/edk2/ArmPkg/Library/ArmLib/Null/NullArmLib.c
new file mode 100644 (file)
index 0000000..6e95cba
--- /dev/null
@@ -0,0 +1,117 @@
+/** @file\r
+\r
+  Copyright (c) 2008-2009, Apple Inc. All rights reserved.\r
+  \r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <Uefi.h>\r
+#include <Library/ArmLib.h>\r
+#include <Library/DebugLib.h>\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanInvalidateDataCache (\r
+  VOID\r
+  )\r
+{\r
+  // Do not run code using the Null cache library.\r
+  ASSERT(FALSE);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanDataCache (\r
+  VOID\r
+  )\r
+{\r
+  // Do not run code using the Null cache library.\r
+  ASSERT(FALSE);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmInvalidateInstructionCache (\r
+  VOID\r
+  )\r
+{\r
+  // Do not run code using the Null cache library.\r
+  ASSERT(FALSE);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmInvalidateDataCacheEntryByMVA (\r
+  IN  UINTN Address\r
+  )\r
+{\r
+  // Do not run code using the Null cache library.\r
+  ASSERT(FALSE);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanDataCacheEntryByMVA (\r
+  IN  UINTN Address\r
+  )\r
+{\r
+  // Do not run code using the Null cache library.\r
+  ASSERT(FALSE);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmCleanInvalidateDataCacheEntryByMVA (\r
+  IN  UINTN Address\r
+  )\r
+{\r
+  // Do not run code using the Null cache library.\r
+  ASSERT(FALSE);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmEnableDataCache (\r
+  VOID\r
+  )\r
+{\r
+  // Do not run code using the Null cache library.\r
+  ASSERT(FALSE);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmDisableDataCache (\r
+  VOID\r
+  )\r
+{\r
+  // Do not run code using the Null cache library.\r
+  ASSERT(FALSE);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmEnableInstructionCache (\r
+  VOID\r
+  )\r
+{\r
+  // Do not run code using the Null cache library.\r
+  ASSERT(FALSE);\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+ArmDisableInstructionCache (\r
+  VOID\r
+  )\r
+{\r
+  // Do not run code using the Null cache library.\r
+  ASSERT(FALSE);\r
+}\r
diff --git a/edk2/ArmPkg/Library/ArmLib/Null/NullArmLib.inf b/edk2/ArmPkg/Library/ArmLib/Null/NullArmLib.inf
new file mode 100644 (file)
index 0000000..ff31b9c
--- /dev/null
@@ -0,0 +1,26 @@
+#%HEADER%\r
+[Defines]\r
+  INF_VERSION                    = 0x00010005\r
+  BASE_NAME                      = NullArmLib\r
+  FILE_GUID                      = 00586300-0E06-4790-AC44-86C56ACBB942\r
+  MODULE_TYPE                    = DXE_DRIVER\r
+  VERSION_STRING                 = 1.0\r
+  LIBRARY_CLASS                  = ArmLib\r
+\r
+[Sources.common]\r
+  ../Common/ArmLibSupport.S    | GCC\r
+  ../Common/ArmLibSupport.asm  | RVCT\r
+  ../Common/ArmLib.c\r
+\r
+  NullArmLib.c\r
+  NullArmCacheInformation.c\r
+\r
+[Packages]\r
+  ArmPkg/ArmPkg.dec\r
+  MdePkg/MdePkg.dec\r
+\r
+[Protocols]\r
+  gEfiCpuArchProtocolGuid\r
+\r
+[FixedPcd]\r
+  gArmTokenSpaceGuid.PcdArmCacheOperationThreshold\r
diff --git a/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/Llvm_int_lib.h b/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/Llvm_int_lib.h
new file mode 100644 (file)
index 0000000..e2c00a2
--- /dev/null
@@ -0,0 +1,83 @@
+/** @file
+
+  Copyright (c) 2008-2009 Apple Inc. All rights reserved.<BR>
+
+  All rights reserved. This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+  University of Illinois/NCSA
+  Open Source License
+  
+  Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
+  All rights reserved.
+  
+  Developed by:
+  
+      LLVM Team
+  
+      University of Illinois at Urbana-Champaign
+  
+      http://llvm.org
+  
+  Permission is hereby granted, free of charge, to any person obtaining a copy of
+  this software and associated documentation files (the "Software"), to deal with
+  the Software without restriction, including without limitation the rights to
+  use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+  of the Software, and to permit persons to whom the Software is furnished to do
+  so, subject to the following conditions:
+  
+      * Redistributions of source code must retain the above copyright notice,
+        this list of conditions and the following disclaimers.
+  
+      * Redistributions in binary form must reproduce the above copyright notice,
+        this list of conditions and the following disclaimers in the
+        documentation and/or other materials provided with the distribution.
+  
+      * Neither the names of the LLVM Team, University of Illinois at
+        Urbana-Champaign, nor the names of its contributors may be used to
+        endorse or promote products derived from this Software without specific
+        prior written permission.
+  
+  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+  FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+  CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+  SOFTWARE.
+**/
+
+#include <Base.h>
+#include <Library/DebugLib.h>
+
+#define CHAR_BIT  8
+
+typedef union {
+    INT64   all;
+    struct {
+        UINT32 low;
+        INT32  high;
+    };
+} dwords;
+
+typedef union {
+    UINT64  all;
+    struct {
+        UINT32 low;
+        UINT32 high;
+    };
+} udwords;
+
+#if __GNUC__
+  #define COUNT_LEADING_ZEROS(_a)   __builtin_clz((_a))
+  #define COUNT_TRAILING_ZEROS(_a)  __builtin_ctz((_a))
+#else
+#error COUNT_LEADING_ZEROS() and COUNT_TRAILING_ZEROS() macros not ported to your compiler
+#endif
diff --git a/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashldi3.S b/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashldi3.S
new file mode 100644 (file)
index 0000000..ac2bdba
--- /dev/null
@@ -0,0 +1,38 @@
+#------------------------------------------------------------------------------ 
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+       .text
+       .align 2
+       .globl ___ashldi3
+___ashldi3:
+       @ args = 0, pretend = 0, frame = 0
+       @ frame_needed = 0, uses_anonymous_args = 0
+       @ link register save eliminated.
+       cmp     r2, #31
+       @ lr needed for prologue
+       bls     L2
+       cmp     r2, #63
+       subls   r2, r2, #32
+       movls   r2, r0, asl r2
+       movhi   r2, #0
+       mov     r1, r2
+       mov     r0, #0
+       bx      lr
+L2:
+       cmp     r2, #0
+       rsbne   r3, r2, #32
+       movne   r3, r0, lsr r3
+       movne   r0, r0, asl r2
+       orrne   r1, r3, r1, asl r2
+       bx      lr
diff --git a/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashldi3.c b/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashldi3.c
new file mode 100644 (file)
index 0000000..f708737
--- /dev/null
@@ -0,0 +1,83 @@
+/** @file
+
+  Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+  
+  All rights reserved. This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+  University of Illinois/NCSA
+  Open Source License
+  
+  Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
+  All rights reserved.
+  
+  Developed by:
+  
+      LLVM Team
+  
+      University of Illinois at Urbana-Champaign
+  
+      http://llvm.org
+  
+  Permission is hereby granted, free of charge, to any person obtaining a copy of
+  this software and associated documentation files (the "Software"), to deal with
+  the Software without restriction, including without limitation the rights to
+  use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+  of the Software, and to permit persons to whom the Software is furnished to do
+  so, subject to the following conditions:
+  
+      * Redistributions of source code must retain the above copyright notice,
+        this list of conditions and the following disclaimers.
+  
+      * Redistributions in binary form must reproduce the above copyright notice,
+        this list of conditions and the following disclaimers in the
+        documentation and/or other materials provided with the distribution.
+  
+      * Neither the names of the LLVM Team, University of Illinois at
+        Urbana-Champaign, nor the names of its contributors may be used to
+        endorse or promote products derived from this Software without specific
+        prior written permission.
+  
+  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+  FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+  CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+  SOFTWARE.
+**/
+
+#include "Llvm_int_lib.h"
+
+// Returns: a << b
+
+// Precondition:  0 <= b < bits_in_dword
+
+INT64
+__ashldi3(INT64 a, INT32 b)
+{
+    const int bits_in_word = (int)(sizeof(INT32) * CHAR_BIT);
+    dwords input;
+    dwords result;
+    input.all = a;
+    if (b & bits_in_word)  // bits_in_word <= b < bits_in_dword
+    {
+        result.low = 0;
+        result.high = input.low << (b - bits_in_word);
+    }
+    else  // 0 <= b < bits_in_word
+    {
+        if (b == 0)
+            return a;
+        result.low  = input.low << b;
+        result.high = (input.high << b) | (input.low >> (bits_in_word - b));
+    }
+    return result.all;
+}
diff --git a/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashrdi3.S b/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashrdi3.S
new file mode 100644 (file)
index 0000000..fb87c88
--- /dev/null
@@ -0,0 +1,39 @@
+#------------------------------------------------------------------------------ 
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+       .text
+       .align 2
+       .globl ___ashrdi3
+___ashrdi3:
+       @ args = 0, pretend = 0, frame = 0
+       @ frame_needed = 0, uses_anonymous_args = 0
+       @ link register save eliminated.
+       cmp     r2, #31
+       @ lr needed for prologue
+       bls     L2
+       cmp     r2, #63
+       subls   r2, r2, #32
+       mov     ip, r1, asr #31
+       movls   r2, r1, asr r2
+       movhi   r2, ip
+       mov     r0, r2
+       mov     r1, ip
+       bx      lr
+L2:
+       cmp     r2, #0
+       rsbne   r3, r2, #32
+       movne   r3, r1, asl r3
+       movne   r1, r1, asr r2
+       orrne   r0, r3, r0, lsr r2
+       bx      lr
diff --git a/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashrdi3.c b/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ashrdi3.c
new file mode 100644 (file)
index 0000000..ce5134e
--- /dev/null
@@ -0,0 +1,84 @@
+/** @file
+
+  Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+  
+  All rights reserved. This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+  University of Illinois/NCSA
+  Open Source License
+  
+  Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
+  All rights reserved.
+  
+  Developed by:
+  
+      LLVM Team
+  
+      University of Illinois at Urbana-Champaign
+  
+      http://llvm.org
+  
+  Permission is hereby granted, free of charge, to any person obtaining a copy of
+  this software and associated documentation files (the "Software"), to deal with
+  the Software without restriction, including without limitation the rights to
+  use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+  of the Software, and to permit persons to whom the Software is furnished to do
+  so, subject to the following conditions:
+  
+      * Redistributions of source code must retain the above copyright notice,
+        this list of conditions and the following disclaimers.
+  
+      * Redistributions in binary form must reproduce the above copyright notice,
+        this list of conditions and the following disclaimers in the
+        documentation and/or other materials provided with the distribution.
+  
+      * Neither the names of the LLVM Team, University of Illinois at
+        Urbana-Champaign, nor the names of its contributors may be used to
+        endorse or promote products derived from this Software without specific
+        prior written permission.
+  
+  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+  FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+  CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+  SOFTWARE.
+**/
+
+#include "Llvm_int_lib.h"
+
+// Returns: arithmetic a >> b
+
+// Precondition:  0 <= b < bits_in_dword
+
+INT64
+__ashrdi3(INT64 a, INT32 b)
+{
+    const int bits_in_word = (int)(sizeof(INT32) * CHAR_BIT);
+    dwords input;
+    dwords result;
+    input.all = a;
+    if (b & bits_in_word)  // bits_in_word <= b < bits_in_dword
+    {
+        // result.high = input.high < 0 ? -1 : 0
+        result.high = input.high >> (bits_in_word - 1);
+        result.low = input.high >> (b - bits_in_word);
+    }
+    else  // 0 <= b < bits_in_word
+    {
+        if (b == 0)
+            return a;
+        result.high  = input.high >> b;
+        result.low = (input.high << (bits_in_word - b)) | (input.low >> b);
+    }
+    return result.all;
+}
diff --git a/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/clzsi2.c b/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/clzsi2.c
new file mode 100644 (file)
index 0000000..c7b4607
--- /dev/null
@@ -0,0 +1,96 @@
+/** @file
+  Compiler intrinsic to return the number of leading zeros, ported from LLVM code.
+
+  Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+  
+  All rights reserved. This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+  University of Illinois/NCSA
+  Open Source License
+  
+  Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
+  All rights reserved.
+  
+  Developed by:
+  
+      LLVM Team
+  
+      University of Illinois at Urbana-Champaign
+  
+      http://llvm.org
+  
+  Permission is hereby granted, free of charge, to any person obtaining a copy of
+  this software and associated documentation files (the "Software"), to deal with
+  the Software without restriction, including without limitation the rights to
+  use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+  of the Software, and to permit persons to whom the Software is furnished to do
+  so, subject to the following conditions:
+  
+      * Redistributions of source code must retain the above copyright notice,
+        this list of conditions and the following disclaimers.
+  
+      * Redistributions in binary form must reproduce the above copyright notice,
+        this list of conditions and the following disclaimers in the
+        documentation and/or other materials provided with the distribution.
+  
+      * Neither the names of the LLVM Team, University of Illinois at
+        Urbana-Champaign, nor the names of its contributors may be used to
+        endorse or promote products derived from this Software without specific
+        prior written permission.
+  
+  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+  FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+  CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+  SOFTWARE.
+**/
+
+
+#include "Llvm_int_lib.h"
+
+// Returns: the number of leading 0-bits
+
+// Precondition: a != 0
+
+INT32
+__clzsi2(INT32 a)
+{
+    UINT32 x = (UINT32)a;
+    INT32 t = ((x & 0xFFFF0000) == 0) << 4;  // if (x is small) t = 16 else 0
+    x >>= 16 - t;      // x = [0 - 0xFFFF]
+    UINT32 r = t;       // r = [0, 16]
+    // return r + clz(x)
+    t = ((x & 0xFF00) == 0) << 3;
+    x >>= 8 - t;       // x = [0 - 0xFF]
+    r += t;            // r = [0, 8, 16, 24]
+    // return r + clz(x)
+    t = ((x & 0xF0) == 0) << 2;
+    x >>= 4 - t;       // x = [0 - 0xF]
+    r += t;            // r = [0, 4, 8, 12, 16, 20, 24, 28]
+    // return r + clz(x)
+    t = ((x & 0xC) == 0) << 1;
+    x >>= 2 - t;       // x = [0 - 3]
+    r += t;            // r = [0 - 30] and is even
+    // return r + clz(x)
+//     switch (x)
+//     {
+//     case 0:
+//         return r + 2;
+//     case 1:
+//         return r + 1;
+//     case 2:
+//     case 3:
+//         return r;
+//     }
+    return r + ((2 - x) & -((x & 2) == 0));
+}
diff --git a/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ctzsi2.c b/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ctzsi2.c
new file mode 100644 (file)
index 0000000..c0e1897
--- /dev/null
@@ -0,0 +1,111 @@
+/** @file
+
+  Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+  
+  All rights reserved. This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/** @file
+  Compiler intrinsic to return the number of trailing zeros, ported from LLVM code.
+
+  Copyright (c) 2008, Apple, Inc.
+  All rights reserved. This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+  University of Illinois/NCSA
+  Open Source License
+  
+  Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
+  All rights reserved.
+  
+  Developed by:
+  
+      LLVM Team
+  
+      University of Illinois at Urbana-Champaign
+  
+      http://llvm.org
+  
+  Permission is hereby granted, free of charge, to any person obtaining a copy of
+  this software and associated documentation files (the "Software"), to deal with
+  the Software without restriction, including without limitation the rights to
+  use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+  of the Software, and to permit persons to whom the Software is furnished to do
+  so, subject to the following conditions:
+  
+      * Redistributions of source code must retain the above copyright notice,
+        this list of conditions and the following disclaimers.
+  
+      * Redistributions in binary form must reproduce the above copyright notice,
+        this list of conditions and the following disclaimers in the
+        documentation and/or other materials provided with the distribution.
+  
+      * Neither the names of the LLVM Team, University of Illinois at
+        Urbana-Champaign, nor the names of its contributors may be used to
+        endorse or promote products derived from this Software without specific
+        prior written permission.
+  
+  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+  FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+  CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+  SOFTWARE.
+**/
+
+
+#include "Llvm_int_lib.h"
+
+// Returns: the number of trailing 0-bits
+
+// Precondition: a != 0
+
+INT32
+__ctzsi2(INT32 a)
+{
+    UINT32 x = (UINT32)a;
+    INT32 t = ((x & 0x0000FFFF) == 0) << 4;  // if (x has no small bits) t = 16 else 0
+    x >>= t;           // x = [0 - 0xFFFF] + higher garbage bits
+    UINT32 r = t;       // r = [0, 16]
+    // return r + ctz(x)
+    t = ((x & 0x00FF) == 0) << 3;
+    x >>= t;           // x = [0 - 0xFF] + higher garbage bits
+    r += t;            // r = [0, 8, 16, 24]
+    // return r + ctz(x)
+    t = ((x & 0x0F) == 0) << 2;
+    x >>= t;           // x = [0 - 0xF] + higher garbage bits
+    r += t;            // r = [0, 4, 8, 12, 16, 20, 24, 28]
+    // return r + ctz(x)
+    t = ((x & 0x3) == 0) << 1;
+    x >>= t;
+    x &= 3;            // x = [0 - 3]
+    r += t;            // r = [0 - 30] and is even
+    // return r + ctz(x)
+//  The branch-less return statement below is equivalent
+//  to the following switch statement:
+//     switch (x)
+//     {
+//     case 0:
+//         return r + 2;
+//     case 2:
+//         return r + 1;
+//     case 1:
+//     case 3:
+//         return r;
+//     }
+    return r + ((2 - (x >> 1)) & -((x & 1) == 0));
+}
diff --git a/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/div.asm b/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/div.asm
new file mode 100644 (file)
index 0000000..f6f9bc2
--- /dev/null
@@ -0,0 +1,155 @@
+//------------------------------------------------------------------------------ 
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+
+    EXPORT  __aeabi_uidiv
+    EXPORT  __aeabi_uidivmod
+    EXPORT  __aeabi_idiv
+    EXPORT  __aeabi_idivmod
+           
+    AREA  Math, CODE, READONLY
+
+;
+;UINT32
+;EFIAPI
+;__aeabi_uidivmode (
+;  IN UINT32  Dividen
+;  IN UINT32  Divisor
+;  );
+;
+
+__aeabi_uidiv
+__aeabi_uidivmod
+    RSBS    r12, r1, r0, LSR #4
+    MOV     r2, #0
+    BCC     __arm_div4
+    RSBS    r12, r1, r0, LSR #8
+    BCC     __arm_div8
+    MOV     r3, #0
+    B       __arm_div_large
+
+;
+;INT32
+;EFIAPI
+;__aeabi_idivmode (
+;  IN INT32  Dividen
+;  IN INT32  Divisor
+;  );
+;
+__aeabi_idiv
+__aeabi_idivmod
+    ORRS    r12, r0, r1
+    BMI     __arm_div_negative
+    RSBS    r12, r1, r0, LSR #1
+    MOV     r2, #0
+    BCC     __arm_div1
+    RSBS    r12, r1, r0, LSR #4
+    BCC     __arm_div4
+    RSBS    r12, r1, r0, LSR #8
+    BCC     __arm_div8
+    MOV     r3, #0
+    B       __arm_div_large
+__arm_div8
+    RSBS    r12, r1, r0, LSR #7
+    SUBCS   r0, r0, r1, LSL #7
+    ADC     r2, r2, r2
+    RSBS    r12, r1, r0,LSR #6
+    SUBCS   r0, r0, r1, LSL #6
+    ADC     r2, r2, r2
+    RSBS    r12, r1, r0, LSR #5
+    SUBCS   r0, r0, r1, LSL #5
+    ADC     r2, r2, r2
+    RSBS    r12, r1, r0, LSR #4
+    SUBCS   r0, r0, r1, LSL #4
+    ADC     r2, r2, r2
+__arm_div4
+    RSBS    r12, r1, r0, LSR #3
+    SUBCS   r0, r0, r1, LSL #3
+    ADC     r2, r2, r2
+    RSBS    r12, r1, r0, LSR #2
+    SUBCS   r0, r0, r1, LSL #2
+    ADCS    r2, r2, r2
+    RSBS    r12, r1, r0, LSR #1
+    SUBCS   r0, r0, r1, LSL #1
+    ADC     r2, r2, r2
+__arm_div1
+    SUBS    r1, r0, r1
+    MOVCC   r1, r0
+    ADC     r0, r2, r2
+    BX      r14
+__arm_div_negative
+    ANDS    r2, r1, #0x80000000
+    RSBMI   r1, r1, #0
+    EORS    r3, r2, r0, ASR #32
+    RSBCS   r0, r0, #0
+    RSBS    r12, r1, r0, LSR #4
+    BCC     label1
+    RSBS    r12, r1, r0, LSR #8
+    BCC     label2
+__arm_div_large
+    LSL     r1, r1, #6
+    RSBS    r12, r1, r0, LSR #8
+    ORR     r2, r2, #0xfc000000
+    BCC     label2
+    LSL     r1, r1, #6
+    RSBS    r12, r1, r0, LSR #8
+    ORR     r2, r2, #0x3f00000
+    BCC     label2
+    LSL     r1, r1, #6
+    RSBS    r12, r1, r0, LSR #8
+    ORR     r2, r2, #0xfc000
+    ORRCS   r2, r2, #0x3f00
+    LSLCS   r1, r1, #6
+    RSBS    r12, r1, #0
+    BCS     __aeabi_idiv0
+label3
+    LSRCS   r1, r1, #6
+label2
+    RSBS    r12, r1, r0, LSR #7
+    SUBCS   r0, r0, r1, LSL #7
+    ADC     r2, r2, r2
+    RSBS    r12, r1, r0, LSR #6
+    SUBCS   r0, r0, r1, LSL #6
+    ADC     r2, r2, r2
+    RSBS    r12, r1, r0, LSR #5
+    SUBCS   r0, r0, r1, LSL #5
+    ADC     r2, r2, r2
+    RSBS    r12, r1, r0, LSR #4
+    SUBCS   r0, r0, r1, LSL #4
+    ADC     r2, r2, r2
+label1
+    RSBS    r12, r1, r0, LSR #3
+    SUBCS   r0, r0, r1, LSL #3
+    ADC     r2, r2, r2
+    RSBS    r12, r1, r0, LSR #2
+    SUBCS   r0, r0, r1, LSL #2
+    ADCS    r2, r2, r2
+    BCS     label3
+    RSBS    r12, r1, r0, LSR #1
+    SUBCS   r0, r0, r1, LSL #1
+    ADC     r2, r2, r2
+    SUBS    r1, r0, r1
+    MOVCC   r1, r0
+    ADC     r0, r2, r2
+    ASRS    r3, r3, #31
+    RSBMI   r0, r0, #0
+    RSBCS   r1, r1, #0
+    BX      r14
+
+    ; What to do about division by zero?  For now, just return.
+__aeabi_idiv0
+    BX      r14
+    END
+
diff --git a/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divdi3.S b/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divdi3.S
new file mode 100644 (file)
index 0000000..b7d946e
--- /dev/null
@@ -0,0 +1,48 @@
+#------------------------------------------------------------------------------ 
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+       .text
+       .align 2
+       .globl ___divdi3
+___divdi3:
+       @ args = 0, pretend = 0, frame = 0
+       @ frame_needed = 1, uses_anonymous_args = 0
+       stmfd   sp!, {r4, r5, r7, lr}
+       mov     r4, r3, asr #31
+       add     r7, sp, #8
+       stmfd   sp!, {r10, r11}
+       mov     r10, r1, asr #31
+       sub     sp, sp, #8
+       mov     r11, r10
+       mov     r5, r4
+       eor     r0, r0, r10
+       eor     r1, r1, r10
+       eor     r2, r2, r4
+       eor     r3, r3, r4
+       subs    r2, r2, r4
+       sbc     r3, r3, r5
+       mov     ip, #0
+       subs    r0, r0, r10
+       sbc     r1, r1, r11
+       str     ip, [sp, #0]
+       bl      ___udivmoddi4
+       eor     r2, r10, r4
+       eor     r3, r10, r4
+       eor     r0, r0, r2
+       eor     r1, r1, r3
+       subs    r0, r0, r2
+       sbc     r1, r1, r3
+       sub     sp, r7, #16
+       ldmfd   sp!, {r10, r11}
+       ldmfd   sp!, {r4, r5, r7, pc}
diff --git a/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divdi3.c b/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divdi3.c
new file mode 100644 (file)
index 0000000..286a504
--- /dev/null
@@ -0,0 +1,77 @@
+/** @file
+  Compiler intrinsic for 64-bit compare, ported from LLVM code.
+
+  Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+  
+  All rights reserved. This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+  University of Illinois/NCSA
+  Open Source License
+  
+  Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
+  All rights reserved.
+  
+  Developed by:
+  
+      LLVM Team
+  
+      University of Illinois at Urbana-Champaign
+  
+      http://llvm.org
+  
+  Permission is hereby granted, free of charge, to any person obtaining a copy of
+  this software and associated documentation files (the "Software"), to deal with
+  the Software without restriction, including without limitation the rights to
+  use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+  of the Software, and to permit persons to whom the Software is furnished to do
+  so, subject to the following conditions:
+  
+      * Redistributions of source code must retain the above copyright notice,
+        this list of conditions and the following disclaimers.
+  
+      * Redistributions in binary form must reproduce the above copyright notice,
+        this list of conditions and the following disclaimers in the
+        documentation and/or other materials provided with the distribution.
+  
+      * Neither the names of the LLVM Team, University of Illinois at
+        Urbana-Champaign, nor the names of its contributors may be used to
+        endorse or promote products derived from this Software without specific
+        prior written permission.
+  
+  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+  FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+  CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+  SOFTWARE.
+**/
+
+
+#include "Llvm_int_lib.h"
+
+UINT64 __udivmoddi4(UINT64 a, UINT64 b, UINT64* rem);
+
+// Returns: a / b
+
+INT64
+__divdi3(INT64 a, INT64 b)
+{
+    const int bits_in_dword_m1 = (int)(sizeof(INT64) * CHAR_BIT) - 1;
+    INT64 s_a = a >> bits_in_dword_m1;           // s_a = a < 0 ? -1 : 0
+    INT64 s_b = b >> bits_in_dword_m1;           // s_b = b < 0 ? -1 : 0
+    a = (a ^ s_a) - s_a;                         // negate if s_a == -1
+    b = (b ^ s_b) - s_b;                         // negate if s_b == -1
+    s_a ^= s_b;                                  // sign of quotient
+    return (__udivmoddi4(a, b, (UINT64*)0) ^ s_a) - s_a;  // negate if s_a == -1
+}
+
+
diff --git a/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divsi3.S b/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divsi3.S
new file mode 100644 (file)
index 0000000..2651572
--- /dev/null
@@ -0,0 +1,33 @@
+#------------------------------------------------------------------------------ 
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+       .text
+       .align 2
+       .globl ___divsi3
+___divsi3:
+       @ args = 0, pretend = 0, frame = 0
+       @ frame_needed = 1, uses_anonymous_args = 0
+       eor     r3, r0, r0, asr #31
+       eor     r2, r1, r1, asr #31
+       stmfd   sp!, {r4, r5, r7, lr}
+       mov     r5, r0, asr #31
+       add     r7, sp, #8
+       mov     r4, r1, asr #31
+       sub     r0, r3, r0, asr #31
+       sub     r1, r2, r1, asr #31
+       bl      ___udivsi3
+       eor     r1, r5, r4
+       eor     r0, r0, r1
+       rsb     r0, r1, r0
+       ldmfd   sp!, {r4, r5, r7, pc}
diff --git a/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divsi3.c b/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/divsi3.c
new file mode 100644 (file)
index 0000000..56d731c
--- /dev/null
@@ -0,0 +1,78 @@
+/** @file
+  Compiler intrinsic for 32--bit unsigned division, ported from LLVM code.
+
+
+  Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+  
+  All rights reserved. This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+  University of Illinois/NCSA
+  Open Source License
+  
+  Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
+  All rights reserved.
+  
+  Developed by:
+  
+      LLVM Team
+  
+      University of Illinois at Urbana-Champaign
+  
+      http://llvm.org
+  
+  Permission is hereby granted, free of charge, to any person obtaining a copy of
+  this software and associated documentation files (the "Software"), to deal with
+  the Software without restriction, including without limitation the rights to
+  use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+  of the Software, and to permit persons to whom the Software is furnished to do
+  so, subject to the following conditions:
+  
+      * Redistributions of source code must retain the above copyright notice,
+        this list of conditions and the following disclaimers.
+  
+      * Redistributions in binary form must reproduce the above copyright notice,
+        this list of conditions and the following disclaimers in the
+        documentation and/or other materials provided with the distribution.
+  
+      * Neither the names of the LLVM Team, University of Illinois at
+        Urbana-Champaign, nor the names of its contributors may be used to
+        endorse or promote products derived from this Software without specific
+        prior written permission.
+  
+  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+  FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
+  CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS WITH THE
+  SOFTWARE.
+**/
+
+
+#include "Llvm_int_lib.h"
+
+UINT32 __udivsi3(UINT32 n, UINT32 d);
+
+// Returns: a / b
+
+INT32
+__divsi3(INT32 a, INT32 b)
+{
+    const int bits_in_word_m1 = (int)(sizeof(INT32) * CHAR_BIT) - 1;
+    INT32 s_a = a >> bits_in_word_m1;           // s_a = a < 0 ? -1 : 0
+    INT32 s_b = b >> bits_in_word_m1;           // s_b = b < 0 ? -1 : 0
+    a = (a ^ s_a) - s_a;                         // negate if s_a == -1
+    b = (b ^ s_b) - s_b;                         // negate if s_b == -1
+    s_a ^= s_b;                                  // sign of quotient
+    return (__udivsi3(a, b) ^ s_a) - s_a;        // negate if s_a == -1
+}
+
+
diff --git a/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lasr.asm b/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lasr.asm
new file mode 100644 (file)
index 0000000..9956d06
--- /dev/null
@@ -0,0 +1,41 @@
+//------------------------------------------------------------------------------ 
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+
+    EXPORT  __aeabi_lasr
+           
+    AREA    Math, CODE, READONLY
+
+;
+;UINT32
+;EFIAPI
+;__aeabi_lasr (
+;  IN UINT32  Dividen
+;  IN UINT32  Divisor
+;  );
+;
+__aeabi_lasr
+    SUBS     r3,r2,#0x20
+    BPL      {pc} + 0x18  ; 0x1c
+    RSB      r3,r2,#0x20
+    LSR      r0,r0,r2
+    ORR      r0,r0,r1,LSL r3
+    ASR      r1,r1,r2
+    BX       lr
+    ASR      r0,r1,r3
+    ASR      r1,r1,#31
+    BX       lr
+    
+    END
+
diff --git a/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.asm b/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/ldivmod.asm
new file mode 100644 (file)
index 0000000..cb81608
--- /dev/null
@@ -0,0 +1,54 @@
+//------------------------------------------------------------------------------ 
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+
+    EXPORT  __aeabi_ldivmod
+    EXTERN  __aeabi_uldivmod
+           
+    AREA    Math, CODE, READONLY
+
+;
+;UINT32
+;EFIAPI
+;__aeabi_uidivmode (
+;  IN UINT32  Dividen
+;  IN UINT32  Divisor
+;  );
+;
+
+__aeabi_ldivmod
+    PUSH     {r4,lr}
+    ASRS     r4,r1,#1
+    EOR      r4,r4,r3,LSR #1
+    BPL      {pc} + 0xc  ; 0x18
+    RSBS     r0,r0,#0
+    RSC      r1,r1,#0
+    TST      r3,r3
+    BPL      {pc} + 0xc  ; 0x28
+    RSBS     r2,r2,#0
+    RSC      r3,r3,#0
+    BL       __aeabi_uldivmod  ;
+    TST      r4,#0x40000000
+    BEQ      {pc} + 0xc  ; 0x3c
+    RSBS     r0,r0,#0
+    RSC      r1,r1,#0
+    TST      r4,#0x80000000
+    BEQ      {pc} + 0xc  ; 0x4c
+    RSBS     r2,r2,#0
+    RSC      r3,r3,#0
+    POP      {r4,pc}
+    END
+
+
diff --git a/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsl.asm b/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsl.asm
new file mode 100644 (file)
index 0000000..745b984
--- /dev/null
@@ -0,0 +1,43 @@
+//------------------------------------------------------------------------------ 
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+
+    EXPORT  __aeabi_llsl
+
+    AREA    Math, CODE, READONLY
+
+;
+;VOID
+;EFIAPI
+;__aeabi_llsl (
+; IN  VOID    *Destination,
+; IN  VOID    *Source,
+; IN  UINT32  Size
+; );
+;
+
+__aeabi_llsl
+    SUBS     r3,r2,#0x20
+    BPL      {pc} + 0x18  ; 0x1c
+    RSB      r3,r2,#0x20
+    LSL      r1,r1,r2
+    ORR      r1,r1,r0,LSR r3
+    LSL      r0,r0,r2
+    BX       lr
+    LSL      r1,r0,r3
+    MOV      r0,#0
+    BX       lr
+
+    END
+
diff --git a/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsr.asm b/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/llsr.asm
new file mode 100644 (file)
index 0000000..630b542
--- /dev/null
@@ -0,0 +1,44 @@
+//------------------------------------------------------------------------------ 
+//
+// Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+//
+// All rights reserved. This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+//------------------------------------------------------------------------------
+
+
+    EXPORT  __aeabi_llsr
+
+    AREA    Math, CODE, READONLY
+
+;
+;VOID
+;EFIAPI
+;__aeabi_llsr (
+; IN  VOID    *Destination,
+; IN  VOID    *Source,
+; IN  UINT32  Size
+; );
+;
+__aeabi_llsr
+    SUBS     r3,r2,#0x20
+    BPL      {pc} + 0x18  ; 0x1c
+    RSB      r3,r2,#0x20
+    LSR      r0,r0,r2
+    ORR      r0,r0,r1,LSL r3
+    LSR      r1,r1,r2
+    BX       lr
+    LSR      r0,r1,r3
+    MOV      r1,#0
+    BX       lr
+
+    END
+
+
+
diff --git a/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lshrdi3.S b/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lshrdi3.S
new file mode 100644 (file)
index 0000000..2257dee
--- /dev/null
@@ -0,0 +1,38 @@
+#------------------------------------------------------------------------------ 
+#
+# Copyright (c) 2008-2009 Apple Inc. All rights reserved.
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution.  The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#------------------------------------------------------------------------------
+
+       .text
+       .align 2
+       .globl ___lshrdi3
+___lshrdi3:
+       @ args = 0, pretend = 0, frame = 0
+       @ frame_needed = 0, uses_anonymous_args = 0
+       @ link register save eliminated.
+       cmp     r2, #31
+       @ lr needed for prologue
+       bls     L2
+       cmp     r2, #63
+       subls   r2, r2, #32
+       movls   r2, r1, lsr r2
+       movhi   r2, #0
+       mov     r0, r2
+       mov     r1, #0
+       bx      lr
+L2:
+       cmp     r2, #0
+       rsbne   r3, r2, #32
+       movne   r3, r1, asl r3
+       movne   r1, r1, lsr r2
+       orrne   r0, r3, r0, lsr r2
+       bx      lr
diff --git a/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lshrdi3.c b/edk2/ArmPkg/Library/CompilerIntrinsicsLib/Arm/lshrdi3.c
new file mode 100644 (file)
index 0000000..14b3c8f
--- /dev/null
@@ -0,0 +1,83 @@
+/** @file
+
+  Copyright (c) 2008-2009, Apple Inc. All rights reserved.
+  
+  All rights reserved. This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+/**
+  University of Illinois/NCSA
+  Open Source License
+  
+  Copyright (c) 2003-2008 University of Illinois at Urbana-Champaign.
+  All rights reserved.
+  
+  Developed by:
+  
+      LLVM Team
+  
+      University of Illinois at Urbana-Champaign
+  
+      http://llvm.org
+